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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @test_vadciq_s32(<4 x i32> %a, <4 x i32> %b, ptr %carry_out) {5; CHECK-LABEL: test_vadciq_s32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vadci.i32 q0, q0, q18; CHECK-NEXT: vmrs r1, fpscr_nzcvqc9; CHECK-NEXT: ubfx r1, r1, #29, #110; CHECK-NEXT: str r1, [r0]11; CHECK-NEXT: bx lr12entry:13 %0 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0)14 %1 = extractvalue { <4 x i32>, i32 } %0, 115 %2 = lshr i32 %1, 2916 %3 = and i32 %2, 117 store i32 %3, ptr %carry_out, align 418 %4 = extractvalue { <4 x i32>, i32 } %0, 019 ret <4 x i32> %420}21 22declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32>, <4 x i32>, i32)23 24define arm_aapcs_vfpcc <4 x i32> @test_vadcq_u32(<4 x i32> %a, <4 x i32> %b, ptr %carry) {25; CHECK-LABEL: test_vadcq_u32:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: ldr r1, [r0]28; CHECK-NEXT: lsls r1, r1, #2929; CHECK-NEXT: vmsr fpscr_nzcvqc, r130; CHECK-NEXT: vadc.i32 q0, q0, q131; CHECK-NEXT: vmrs r1, fpscr_nzcvqc32; CHECK-NEXT: ubfx r1, r1, #29, #133; CHECK-NEXT: str r1, [r0]34; CHECK-NEXT: bx lr35entry:36 %0 = load i32, ptr %carry, align 437 %1 = shl i32 %0, 2938 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %1)39 %3 = extractvalue { <4 x i32>, i32 } %2, 140 %4 = lshr i32 %3, 2941 %5 = and i32 %4, 142 store i32 %5, ptr %carry, align 443 %6 = extractvalue { <4 x i32>, i32 } %2, 044 ret <4 x i32> %645}46 47define arm_aapcs_vfpcc <4 x i32> @test_vadciq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, ptr %carry_out, i16 zeroext %p) {48; CHECK-LABEL: test_vadciq_m_u32:49; CHECK: @ %bb.0: @ %entry50; CHECK-NEXT: vmsr p0, r151; CHECK-NEXT: vpst52; CHECK-NEXT: vadcit.i32 q0, q1, q253; CHECK-NEXT: vmrs r1, fpscr_nzcvqc54; CHECK-NEXT: ubfx r1, r1, #29, #155; CHECK-NEXT: str r1, [r0]56; CHECK-NEXT: bx lr57entry:58 %0 = zext i16 %p to i3259 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)60 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1)61 %3 = extractvalue { <4 x i32>, i32 } %2, 162 %4 = lshr i32 %3, 2963 %5 = and i32 %4, 164 store i32 %5, ptr %carry_out, align 465 %6 = extractvalue { <4 x i32>, i32 } %2, 066 ret <4 x i32> %667}68 69declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)70 71declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>)72 73define arm_aapcs_vfpcc <4 x i32> @test_vadcq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, ptr %carry, i16 zeroext %p) {74; CHECK-LABEL: test_vadcq_m_s32:75; CHECK: @ %bb.0: @ %entry76; CHECK-NEXT: ldr r2, [r0]77; CHECK-NEXT: vmsr p0, r178; CHECK-NEXT: lsls r1, r2, #2979; CHECK-NEXT: vmsr fpscr_nzcvqc, r180; CHECK-NEXT: vpst81; CHECK-NEXT: vadct.i32 q0, q1, q282; CHECK-NEXT: vmrs r1, fpscr_nzcvqc83; CHECK-NEXT: ubfx r1, r1, #29, #184; CHECK-NEXT: str r1, [r0]85; CHECK-NEXT: bx lr86entry:87 %0 = load i32, ptr %carry, align 488 %1 = shl i32 %0, 2989 %2 = zext i16 %p to i3290 %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)91 %4 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 %1, <4 x i1> %3)92 %5 = extractvalue { <4 x i32>, i32 } %4, 193 %6 = lshr i32 %5, 2994 %7 = and i32 %6, 195 store i32 %7, ptr %carry, align 496 %8 = extractvalue { <4 x i32>, i32 } %4, 097 ret <4 x i32> %898}99 100declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32>, <4 x i32>, i32)101 102define arm_aapcs_vfpcc <4 x i32> @test_vsbciq_s32(<4 x i32> %a, <4 x i32> %b, ptr nocapture %carry_out) {103; CHECK-LABEL: test_vsbciq_s32:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vsbci.i32 q0, q0, q1106; CHECK-NEXT: vmrs r1, fpscr_nzcvqc107; CHECK-NEXT: ubfx r1, r1, #29, #1108; CHECK-NEXT: str r1, [r0]109; CHECK-NEXT: bx lr110entry:111 %0 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %a, <4 x i32> %b, i32 536870912)112 %1 = extractvalue { <4 x i32>, i32 } %0, 1113 %2 = lshr i32 %1, 29114 %3 = and i32 %2, 1115 store i32 %3, ptr %carry_out, align 4116 %4 = extractvalue { <4 x i32>, i32 } %0, 0117 ret <4 x i32> %4118}119 120define arm_aapcs_vfpcc <4 x i32> @test_vsbciq_u32(<4 x i32> %a, <4 x i32> %b, ptr nocapture %carry_out) {121; CHECK-LABEL: test_vsbciq_u32:122; CHECK: @ %bb.0: @ %entry123; CHECK-NEXT: vsbci.i32 q0, q0, q1124; CHECK-NEXT: vmrs r1, fpscr_nzcvqc125; CHECK-NEXT: ubfx r1, r1, #29, #1126; CHECK-NEXT: str r1, [r0]127; CHECK-NEXT: bx lr128entry:129 %0 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %a, <4 x i32> %b, i32 536870912)130 %1 = extractvalue { <4 x i32>, i32 } %0, 1131 %2 = lshr i32 %1, 29132 %3 = and i32 %2, 1133 store i32 %3, ptr %carry_out, align 4134 %4 = extractvalue { <4 x i32>, i32 } %0, 0135 ret <4 x i32> %4136}137 138define arm_aapcs_vfpcc <4 x i32> @test_vsbcq_s32_carry_in_zero(<4 x i32> %a, <4 x i32> %b, ptr nocapture %carry_out) {139; CHECK-LABEL: test_vsbcq_s32_carry_in_zero:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: movs r1, #0142; CHECK-NEXT: vmsr fpscr_nzcvqc, r1143; CHECK-NEXT: vsbc.i32 q0, q0, q1144; CHECK-NEXT: vmrs r1, fpscr_nzcvqc145; CHECK-NEXT: ubfx r1, r1, #29, #1146; CHECK-NEXT: str r1, [r0]147; CHECK-NEXT: bx lr148entry:149 %0 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0)150 %1 = extractvalue { <4 x i32>, i32 } %0, 1151 %2 = lshr i32 %1, 29152 %3 = and i32 %2, 1153 store i32 %3, ptr %carry_out, align 4154 %4 = extractvalue { <4 x i32>, i32 } %0, 0155 ret <4 x i32> %4156}157 158define arm_aapcs_vfpcc <4 x i32> @test_vsbcq_u32_carry_in_zero(<4 x i32> %a, <4 x i32> %b, ptr nocapture %carry_out) {159; CHECK-LABEL: test_vsbcq_u32_carry_in_zero:160; CHECK: @ %bb.0: @ %entry161; CHECK-NEXT: movs r1, #0162; CHECK-NEXT: vmsr fpscr_nzcvqc, r1163; CHECK-NEXT: vsbc.i32 q0, q0, q1164; CHECK-NEXT: vmrs r1, fpscr_nzcvqc165; CHECK-NEXT: ubfx r1, r1, #29, #1166; CHECK-NEXT: str r1, [r0]167; CHECK-NEXT: bx lr168entry:169 %0 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0)170 %1 = extractvalue { <4 x i32>, i32 } %0, 1171 %2 = lshr i32 %1, 29172 %3 = and i32 %2, 1173 store i32 %3, ptr %carry_out, align 4174 %4 = extractvalue { <4 x i32>, i32 } %0, 0175 ret <4 x i32> %4176}177 178define arm_aapcs_vfpcc <4 x i32> @test_vsbcq_s32(<4 x i32> %a, <4 x i32> %b, ptr nocapture %carry) {179; CHECK-LABEL: test_vsbcq_s32:180; CHECK: @ %bb.0: @ %entry181; CHECK-NEXT: ldr r1, [r0]182; CHECK-NEXT: lsls r1, r1, #29183; CHECK-NEXT: vmsr fpscr_nzcvqc, r1184; CHECK-NEXT: vsbc.i32 q0, q0, q1185; CHECK-NEXT: vmrs r1, fpscr_nzcvqc186; CHECK-NEXT: ubfx r1, r1, #29, #1187; CHECK-NEXT: str r1, [r0]188; CHECK-NEXT: bx lr189entry:190 %0 = load i32, ptr %carry, align 4191 %1 = shl i32 %0, 29192 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %1)193 %3 = extractvalue { <4 x i32>, i32 } %2, 1194 %4 = lshr i32 %3, 29195 %5 = and i32 %4, 1196 store i32 %5, ptr %carry, align 4197 %6 = extractvalue { <4 x i32>, i32 } %2, 0198 ret <4 x i32> %6199}200 201define arm_aapcs_vfpcc <4 x i32> @test_vsbcq_u32(<4 x i32> %a, <4 x i32> %b, ptr nocapture %carry) {202; CHECK-LABEL: test_vsbcq_u32:203; CHECK: @ %bb.0: @ %entry204; CHECK-NEXT: ldr r1, [r0]205; CHECK-NEXT: lsls r1, r1, #29206; CHECK-NEXT: vmsr fpscr_nzcvqc, r1207; CHECK-NEXT: vsbc.i32 q0, q0, q1208; CHECK-NEXT: vmrs r1, fpscr_nzcvqc209; CHECK-NEXT: ubfx r1, r1, #29, #1210; CHECK-NEXT: str r1, [r0]211; CHECK-NEXT: bx lr212entry:213 %0 = load i32, ptr %carry, align 4214 %1 = shl i32 %0, 29215 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %1)216 %3 = extractvalue { <4 x i32>, i32 } %2, 1217 %4 = lshr i32 %3, 29218 %5 = and i32 %4, 1219 store i32 %5, ptr %carry, align 4220 %6 = extractvalue { <4 x i32>, i32 } %2, 0221 ret <4 x i32> %6222}223 224declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>)225 226define arm_aapcs_vfpcc <4 x i32> @test_vsbciq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, ptr nocapture %carry_out, i16 zeroext %p) {227; CHECK-LABEL: test_vsbciq_m_s32:228; CHECK: @ %bb.0: @ %entry229; CHECK-NEXT: vmsr p0, r1230; CHECK-NEXT: vpst231; CHECK-NEXT: vsbcit.i32 q0, q1, q2232; CHECK-NEXT: vmrs r1, fpscr_nzcvqc233; CHECK-NEXT: ubfx r1, r1, #29, #1234; CHECK-NEXT: str r1, [r0]235; CHECK-NEXT: bx lr236entry:237 %0 = zext i16 %p to i32238 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)239 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 536870912, <4 x i1> %1)240 %3 = extractvalue { <4 x i32>, i32 } %2, 1241 %4 = lshr i32 %3, 29242 %5 = and i32 %4, 1243 store i32 %5, ptr %carry_out, align 4244 %6 = extractvalue { <4 x i32>, i32 } %2, 0245 ret <4 x i32> %6246}247 248define arm_aapcs_vfpcc <4 x i32> @test_vsbciq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, ptr nocapture %carry_out, i16 zeroext %p) {249; CHECK-LABEL: test_vsbciq_m_u32:250; CHECK: @ %bb.0: @ %entry251; CHECK-NEXT: vmsr p0, r1252; CHECK-NEXT: vpst253; CHECK-NEXT: vsbcit.i32 q0, q1, q2254; CHECK-NEXT: vmrs r1, fpscr_nzcvqc255; CHECK-NEXT: ubfx r1, r1, #29, #1256; CHECK-NEXT: str r1, [r0]257; CHECK-NEXT: bx lr258entry:259 %0 = zext i16 %p to i32260 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)261 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 536870912, <4 x i1> %1)262 %3 = extractvalue { <4 x i32>, i32 } %2, 1263 %4 = lshr i32 %3, 29264 %5 = and i32 %4, 1265 store i32 %5, ptr %carry_out, align 4266 %6 = extractvalue { <4 x i32>, i32 } %2, 0267 ret <4 x i32> %6268}269 270define arm_aapcs_vfpcc <4 x i32> @test_vsbcq_m_s32_carry_in_zero(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, ptr nocapture %carry_out, i16 zeroext %p) {271; CHECK-LABEL: test_vsbcq_m_s32_carry_in_zero:272; CHECK: @ %bb.0: @ %entry273; CHECK-NEXT: movs r2, #0274; CHECK-NEXT: vmsr p0, r1275; CHECK-NEXT: vmsr fpscr_nzcvqc, r2276; CHECK-NEXT: vpst277; CHECK-NEXT: vsbct.i32 q0, q1, q2278; CHECK-NEXT: vmrs r1, fpscr_nzcvqc279; CHECK-NEXT: ubfx r1, r1, #29, #1280; CHECK-NEXT: str r1, [r0]281; CHECK-NEXT: bx lr282entry:283 %0 = zext i16 %p to i32284 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)285 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1)286 %3 = extractvalue { <4 x i32>, i32 } %2, 1287 %4 = lshr i32 %3, 29288 %5 = and i32 %4, 1289 store i32 %5, ptr %carry_out, align 4290 %6 = extractvalue { <4 x i32>, i32 } %2, 0291 ret <4 x i32> %6292}293 294define arm_aapcs_vfpcc <4 x i32> @test_vsbcq_m_u32_carry_in_zero(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, ptr nocapture %carry_out, i16 zeroext %p) {295; CHECK-LABEL: test_vsbcq_m_u32_carry_in_zero:296; CHECK: @ %bb.0: @ %entry297; CHECK-NEXT: movs r2, #0298; CHECK-NEXT: vmsr p0, r1299; CHECK-NEXT: vmsr fpscr_nzcvqc, r2300; CHECK-NEXT: vpst301; CHECK-NEXT: vsbct.i32 q0, q1, q2302; CHECK-NEXT: vmrs r1, fpscr_nzcvqc303; CHECK-NEXT: ubfx r1, r1, #29, #1304; CHECK-NEXT: str r1, [r0]305; CHECK-NEXT: bx lr306entry:307 %0 = zext i16 %p to i32308 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)309 %2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1)310 %3 = extractvalue { <4 x i32>, i32 } %2, 1311 %4 = lshr i32 %3, 29312 %5 = and i32 %4, 1313 store i32 %5, ptr %carry_out, align 4314 %6 = extractvalue { <4 x i32>, i32 } %2, 0315 ret <4 x i32> %6316}317 318define arm_aapcs_vfpcc <4 x i32> @test_vsbcq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, ptr nocapture %carry, i16 zeroext %p) {319; CHECK-LABEL: test_vsbcq_m_s32:320; CHECK: @ %bb.0: @ %entry321; CHECK-NEXT: ldr r2, [r0]322; CHECK-NEXT: vmsr p0, r1323; CHECK-NEXT: lsls r1, r2, #29324; CHECK-NEXT: vmsr fpscr_nzcvqc, r1325; CHECK-NEXT: vpst326; CHECK-NEXT: vsbct.i32 q0, q1, q2327; CHECK-NEXT: vmrs r1, fpscr_nzcvqc328; CHECK-NEXT: ubfx r1, r1, #29, #1329; CHECK-NEXT: str r1, [r0]330; CHECK-NEXT: bx lr331entry:332 %0 = load i32, ptr %carry, align 4333 %1 = shl i32 %0, 29334 %2 = zext i16 %p to i32335 %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)336 %4 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 %1, <4 x i1> %3)337 %5 = extractvalue { <4 x i32>, i32 } %4, 1338 %6 = lshr i32 %5, 29339 %7 = and i32 %6, 1340 store i32 %7, ptr %carry, align 4341 %8 = extractvalue { <4 x i32>, i32 } %4, 0342 ret <4 x i32> %8343}344 345define arm_aapcs_vfpcc <4 x i32> @test_vsbcq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, ptr nocapture %carry, i16 zeroext %p) {346; CHECK-LABEL: test_vsbcq_m_u32:347; CHECK: @ %bb.0: @ %entry348; CHECK-NEXT: ldr r2, [r0]349; CHECK-NEXT: vmsr p0, r1350; CHECK-NEXT: lsls r1, r2, #29351; CHECK-NEXT: vmsr fpscr_nzcvqc, r1352; CHECK-NEXT: vpst353; CHECK-NEXT: vsbct.i32 q0, q1, q2354; CHECK-NEXT: vmrs r1, fpscr_nzcvqc355; CHECK-NEXT: ubfx r1, r1, #29, #1356; CHECK-NEXT: str r1, [r0]357; CHECK-NEXT: bx lr358entry:359 %0 = load i32, ptr %carry, align 4360 %1 = shl i32 %0, 29361 %2 = zext i16 %p to i32362 %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)363 %4 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 %1, <4 x i1> %3)364 %5 = extractvalue { <4 x i32>, i32 } %4, 1365 %6 = lshr i32 %5, 29366 %7 = and i32 %6, 1367 store i32 %7, ptr %carry, align 4368 %8 = extractvalue { <4 x i32>, i32 } %4, 0369 ret <4 x i32> %8370}371