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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc i32 @test_vaddvq_s8(<16 x i8> %a) {5; CHECK-LABEL: test_vaddvq_s8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vaddv.s8 r0, q08; CHECK-NEXT: bx lr9entry:10 %0 = tail call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %a, i32 0)11 ret i32 %012}13 14define arm_aapcs_vfpcc i32 @test_vaddvq_s16(<8 x i16> %a) {15; CHECK-LABEL: test_vaddvq_s16:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vaddv.s16 r0, q018; CHECK-NEXT: bx lr19entry:20 %0 = tail call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %a, i32 0)21 ret i32 %022}23 24define arm_aapcs_vfpcc i32 @test_vaddvq_s32(<4 x i32> %a) {25; CHECK-LABEL: test_vaddvq_s32:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vaddv.s32 r0, q028; CHECK-NEXT: bx lr29entry:30 %0 = tail call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %a, i32 0)31 ret i32 %032}33 34define arm_aapcs_vfpcc i32 @test_vaddvq_u8(<16 x i8> %a) {35; CHECK-LABEL: test_vaddvq_u8:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vaddv.u8 r0, q038; CHECK-NEXT: bx lr39entry:40 %0 = tail call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %a, i32 1)41 ret i32 %042}43 44define arm_aapcs_vfpcc i32 @test_vaddvq_u16(<8 x i16> %a) {45; CHECK-LABEL: test_vaddvq_u16:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vaddv.u16 r0, q048; CHECK-NEXT: bx lr49entry:50 %0 = tail call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %a, i32 1)51 ret i32 %052}53 54define arm_aapcs_vfpcc i32 @test_vaddvq_u32(<4 x i32> %a) {55; CHECK-LABEL: test_vaddvq_u32:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vaddv.u32 r0, q058; CHECK-NEXT: bx lr59entry:60 %0 = tail call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %a, i32 1)61 ret i32 %062}63 64define arm_aapcs_vfpcc i32 @test_vaddvaq_s8(i32 %a, <16 x i8> %b) {65; CHECK-LABEL: test_vaddvaq_s8:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vaddva.s8 r0, q068; CHECK-NEXT: bx lr69entry:70 %0 = tail call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %b, i32 0)71 %1 = add i32 %0, %a72 ret i32 %173}74 75define arm_aapcs_vfpcc i32 @test_vaddvaq_s16(i32 %a, <8 x i16> %b) {76; CHECK-LABEL: test_vaddvaq_s16:77; CHECK: @ %bb.0: @ %entry78; CHECK-NEXT: vaddva.s16 r0, q079; CHECK-NEXT: bx lr80entry:81 %0 = tail call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %b, i32 0)82 %1 = add i32 %0, %a83 ret i32 %184}85 86define arm_aapcs_vfpcc i32 @test_vaddvaq_s32(i32 %a, <4 x i32> %b) {87; CHECK-LABEL: test_vaddvaq_s32:88; CHECK: @ %bb.0: @ %entry89; CHECK-NEXT: vaddva.s32 r0, q090; CHECK-NEXT: bx lr91entry:92 %0 = tail call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %b, i32 0)93 %1 = add i32 %0, %a94 ret i32 %195}96 97define arm_aapcs_vfpcc i32 @test_vaddvaq_u8(i32 %a, <16 x i8> %b) {98; CHECK-LABEL: test_vaddvaq_u8:99; CHECK: @ %bb.0: @ %entry100; CHECK-NEXT: vaddva.u8 r0, q0101; CHECK-NEXT: bx lr102entry:103 %0 = tail call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %b, i32 1)104 %1 = add i32 %0, %a105 ret i32 %1106}107 108define arm_aapcs_vfpcc i32 @test_vaddvaq_u16(i32 %a, <8 x i16> %b) {109; CHECK-LABEL: test_vaddvaq_u16:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vaddva.u16 r0, q0112; CHECK-NEXT: bx lr113entry:114 %0 = tail call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %b, i32 1)115 %1 = add i32 %0, %a116 ret i32 %1117}118 119define arm_aapcs_vfpcc i32 @test_vaddvaq_u32(i32 %a, <4 x i32> %b) {120; CHECK-LABEL: test_vaddvaq_u32:121; CHECK: @ %bb.0: @ %entry122; CHECK-NEXT: vaddva.u32 r0, q0123; CHECK-NEXT: bx lr124entry:125 %0 = tail call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %b, i32 1)126 %1 = add i32 %0, %a127 ret i32 %1128}129 130define arm_aapcs_vfpcc i32 @test_vaddvq_p_s8(<16 x i8> %a, i16 zeroext %p) {131; CHECK-LABEL: test_vaddvq_p_s8:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: vmsr p0, r0134; CHECK-NEXT: vpst135; CHECK-NEXT: vaddvt.s8 r0, q0136; CHECK-NEXT: bx lr137entry:138 %0 = zext i16 %p to i32139 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)140 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %a, i32 0, <16 x i1> %1)141 ret i32 %2142}143 144define arm_aapcs_vfpcc i32 @test_vaddvq_p_s16(<8 x i16> %a, i16 zeroext %p) {145; CHECK-LABEL: test_vaddvq_p_s16:146; CHECK: @ %bb.0: @ %entry147; CHECK-NEXT: vmsr p0, r0148; CHECK-NEXT: vpst149; CHECK-NEXT: vaddvt.s16 r0, q0150; CHECK-NEXT: bx lr151entry:152 %0 = zext i16 %p to i32153 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)154 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %a, i32 0, <8 x i1> %1)155 ret i32 %2156}157 158define arm_aapcs_vfpcc i32 @test_vaddvq_p_s32(<4 x i32> %a, i16 zeroext %p) {159; CHECK-LABEL: test_vaddvq_p_s32:160; CHECK: @ %bb.0: @ %entry161; CHECK-NEXT: vmsr p0, r0162; CHECK-NEXT: vpst163; CHECK-NEXT: vaddvt.s32 r0, q0164; CHECK-NEXT: bx lr165entry:166 %0 = zext i16 %p to i32167 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)168 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %a, i32 0, <4 x i1> %1)169 ret i32 %2170}171 172define arm_aapcs_vfpcc i32 @test_vaddvq_p_u8(<16 x i8> %a, i16 zeroext %p) {173; CHECK-LABEL: test_vaddvq_p_u8:174; CHECK: @ %bb.0: @ %entry175; CHECK-NEXT: vmsr p0, r0176; CHECK-NEXT: vpst177; CHECK-NEXT: vaddvt.u8 r0, q0178; CHECK-NEXT: bx lr179entry:180 %0 = zext i16 %p to i32181 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)182 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %a, i32 1, <16 x i1> %1)183 ret i32 %2184}185 186define arm_aapcs_vfpcc i32 @test_vaddvq_p_u16(<8 x i16> %a, i16 zeroext %p) {187; CHECK-LABEL: test_vaddvq_p_u16:188; CHECK: @ %bb.0: @ %entry189; CHECK-NEXT: vmsr p0, r0190; CHECK-NEXT: vpst191; CHECK-NEXT: vaddvt.u16 r0, q0192; CHECK-NEXT: bx lr193entry:194 %0 = zext i16 %p to i32195 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)196 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %a, i32 1, <8 x i1> %1)197 ret i32 %2198}199 200define arm_aapcs_vfpcc i32 @test_vaddvq_p_u32(<4 x i32> %a, i16 zeroext %p) {201; CHECK-LABEL: test_vaddvq_p_u32:202; CHECK: @ %bb.0: @ %entry203; CHECK-NEXT: vmsr p0, r0204; CHECK-NEXT: vpst205; CHECK-NEXT: vaddvt.u32 r0, q0206; CHECK-NEXT: bx lr207entry:208 %0 = zext i16 %p to i32209 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)210 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %a, i32 1, <4 x i1> %1)211 ret i32 %2212}213 214define arm_aapcs_vfpcc i32 @test_vaddvaq_p_s8(i32 %a, <16 x i8> %b, i16 zeroext %p) {215; CHECK-LABEL: test_vaddvaq_p_s8:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vmsr p0, r1218; CHECK-NEXT: vpst219; CHECK-NEXT: vaddvat.s8 r0, q0220; CHECK-NEXT: bx lr221entry:222 %0 = zext i16 %p to i32223 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)224 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %b, i32 0, <16 x i1> %1)225 %3 = add i32 %2, %a226 ret i32 %3227}228 229define arm_aapcs_vfpcc i32 @test_vaddvaq_p_s16(i32 %a, <8 x i16> %b, i16 zeroext %p) {230; CHECK-LABEL: test_vaddvaq_p_s16:231; CHECK: @ %bb.0: @ %entry232; CHECK-NEXT: vmsr p0, r1233; CHECK-NEXT: vpst234; CHECK-NEXT: vaddvat.s16 r0, q0235; CHECK-NEXT: bx lr236entry:237 %0 = zext i16 %p to i32238 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)239 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %b, i32 0, <8 x i1> %1)240 %3 = add i32 %2, %a241 ret i32 %3242}243 244define arm_aapcs_vfpcc i32 @test_vaddvaq_p_s32(i32 %a, <4 x i32> %b, i16 zeroext %p) {245; CHECK-LABEL: test_vaddvaq_p_s32:246; CHECK: @ %bb.0: @ %entry247; CHECK-NEXT: vmsr p0, r1248; CHECK-NEXT: vpst249; CHECK-NEXT: vaddvat.s32 r0, q0250; CHECK-NEXT: bx lr251entry:252 %0 = zext i16 %p to i32253 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)254 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %b, i32 0, <4 x i1> %1)255 %3 = add i32 %2, %a256 ret i32 %3257}258 259define arm_aapcs_vfpcc i32 @test_vaddvaq_p_u8(i32 %a, <16 x i8> %b, i16 zeroext %p) {260; CHECK-LABEL: test_vaddvaq_p_u8:261; CHECK: @ %bb.0: @ %entry262; CHECK-NEXT: vmsr p0, r1263; CHECK-NEXT: vpst264; CHECK-NEXT: vaddvat.u8 r0, q0265; CHECK-NEXT: bx lr266entry:267 %0 = zext i16 %p to i32268 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)269 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %b, i32 1, <16 x i1> %1)270 %3 = add i32 %2, %a271 ret i32 %3272}273 274define arm_aapcs_vfpcc i32 @test_vaddvaq_p_u16(i32 %a, <8 x i16> %b, i16 zeroext %p) {275; CHECK-LABEL: test_vaddvaq_p_u16:276; CHECK: @ %bb.0: @ %entry277; CHECK-NEXT: vmsr p0, r1278; CHECK-NEXT: vpst279; CHECK-NEXT: vaddvat.u16 r0, q0280; CHECK-NEXT: bx lr281entry:282 %0 = zext i16 %p to i32283 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)284 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %b, i32 1, <8 x i1> %1)285 %3 = add i32 %2, %a286 ret i32 %3287}288 289define arm_aapcs_vfpcc i32 @test_vaddvaq_p_u32(i32 %a, <4 x i32> %b, i16 zeroext %p) {290; CHECK-LABEL: test_vaddvaq_p_u32:291; CHECK: @ %bb.0: @ %entry292; CHECK-NEXT: vmsr p0, r1293; CHECK-NEXT: vpst294; CHECK-NEXT: vaddvat.u32 r0, q0295; CHECK-NEXT: bx lr296entry:297 %0 = zext i16 %p to i32298 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)299 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %b, i32 1, <4 x i1> %1)300 %3 = add i32 %2, %a301 ret i32 %3302}303 304define arm_aapcs_vfpcc i64 @test_vaddlvq_s32(<4 x i32> %a) {305; CHECK-LABEL: test_vaddlvq_s32:306; CHECK: @ %bb.0: @ %entry307; CHECK-NEXT: vaddlv.s32 r0, r1, q0308; CHECK-NEXT: bx lr309entry:310 %0 = tail call i64 @llvm.arm.mve.addlv.v4i32(<4 x i32> %a, i32 0)311 ret i64 %0312}313 314define arm_aapcs_vfpcc i64 @test_vaddlvq_u32(<4 x i32> %a) {315; CHECK-LABEL: test_vaddlvq_u32:316; CHECK: @ %bb.0: @ %entry317; CHECK-NEXT: vaddlv.u32 r0, r1, q0318; CHECK-NEXT: bx lr319entry:320 %0 = tail call i64 @llvm.arm.mve.addlv.v4i32(<4 x i32> %a, i32 1)321 ret i64 %0322}323 324define arm_aapcs_vfpcc i64 @test_vaddlvaq_s32(i64 %a, <4 x i32> %b) {325; CHECK-LABEL: test_vaddlvaq_s32:326; CHECK: @ %bb.0: @ %entry327; CHECK-NEXT: vaddlva.s32 r0, r1, q0328; CHECK-NEXT: bx lr329entry:330 %0 = tail call i64 @llvm.arm.mve.addlv.v4i32(<4 x i32> %b, i32 0)331 %1 = add i64 %0, %a332 ret i64 %1333}334 335define arm_aapcs_vfpcc i64 @test_vaddlvaq_u32(i64 %a, <4 x i32> %b) {336; CHECK-LABEL: test_vaddlvaq_u32:337; CHECK: @ %bb.0: @ %entry338; CHECK-NEXT: vaddlva.u32 r0, r1, q0339; CHECK-NEXT: bx lr340entry:341 %0 = tail call i64 @llvm.arm.mve.addlv.v4i32(<4 x i32> %b, i32 1)342 %1 = add i64 %0, %a343 ret i64 %1344}345 346define arm_aapcs_vfpcc i64 @test_vaddlvq_p_s32(<4 x i32> %a, i16 zeroext %p) {347; CHECK-LABEL: test_vaddlvq_p_s32:348; CHECK: @ %bb.0: @ %entry349; CHECK-NEXT: vmsr p0, r0350; CHECK-NEXT: vpst351; CHECK-NEXT: vaddlvt.s32 r0, r1, q0352; CHECK-NEXT: bx lr353entry:354 %0 = zext i16 %p to i32355 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)356 %2 = tail call i64 @llvm.arm.mve.addlv.predicated.v4i32.v4i1(<4 x i32> %a, i32 0, <4 x i1> %1)357 ret i64 %2358}359 360define arm_aapcs_vfpcc i64 @test_vaddlvq_p_u32(<4 x i32> %a, i16 zeroext %p) {361; CHECK-LABEL: test_vaddlvq_p_u32:362; CHECK: @ %bb.0: @ %entry363; CHECK-NEXT: vmsr p0, r0364; CHECK-NEXT: vpst365; CHECK-NEXT: vaddlvt.u32 r0, r1, q0366; CHECK-NEXT: bx lr367entry:368 %0 = zext i16 %p to i32369 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)370 %2 = tail call i64 @llvm.arm.mve.addlv.predicated.v4i32.v4i1(<4 x i32> %a, i32 1, <4 x i1> %1)371 ret i64 %2372}373 374define arm_aapcs_vfpcc i64 @test_vaddlvaq_p_s32(i64 %a, <4 x i32> %b, i16 zeroext %p) {375; CHECK-LABEL: test_vaddlvaq_p_s32:376; CHECK: @ %bb.0: @ %entry377; CHECK-NEXT: vmsr p0, r2378; CHECK-NEXT: vpst379; CHECK-NEXT: vaddlvat.s32 r0, r1, q0380; CHECK-NEXT: bx lr381entry:382 %0 = zext i16 %p to i32383 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)384 %2 = tail call i64 @llvm.arm.mve.addlv.predicated.v4i32.v4i1(<4 x i32> %b, i32 0, <4 x i1> %1)385 %3 = add i64 %2, %a386 ret i64 %3387}388 389define arm_aapcs_vfpcc i64 @test_vaddlvaq_p_u32(i64 %a, <4 x i32> %b, i16 zeroext %p) {390; CHECK-LABEL: test_vaddlvaq_p_u32:391; CHECK: @ %bb.0: @ %entry392; CHECK-NEXT: vmsr p0, r2393; CHECK-NEXT: vpst394; CHECK-NEXT: vaddlvat.u32 r0, r1, q0395; CHECK-NEXT: bx lr396entry:397 %0 = zext i16 %p to i32398 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)399 %2 = tail call i64 @llvm.arm.mve.addlv.predicated.v4i32.v4i1(<4 x i32> %b, i32 1, <4 x i1> %1)400 %3 = add i64 %2, %a401 ret i64 %3402}403 404declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)405declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)406declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)407 408declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32)409declare i32 @llvm.arm.mve.addv.v8i16(<8 x i16>, i32)410declare i32 @llvm.arm.mve.addv.v4i32(<4 x i32>, i32)411declare i64 @llvm.arm.mve.addlv.v4i32(<4 x i32>, i32)412 413declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>)414declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>)415declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)416declare i64 @llvm.arm.mve.addlv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)417