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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {5; CHECK-LABEL: test_vandq_u8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vand q0, q1, q08; CHECK-NEXT: bx lr9entry:10 %0 = and <16 x i8> %b, %a11 ret <16 x i8> %012}13 14define arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {15; CHECK-LABEL: test_vandq_s16:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vand q0, q1, q018; CHECK-NEXT: bx lr19entry:20 %0 = and <8 x i16> %b, %a21 ret <8 x i16> %022}23 24define arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {25; CHECK-LABEL: test_vandq_u32:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vand q0, q1, q028; CHECK-NEXT: bx lr29entry:30 %0 = and <4 x i32> %b, %a31 ret <4 x i32> %032}33 34define arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {35; CHECK-LABEL: test_vandq_f32:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vand q0, q1, q038; CHECK-NEXT: bx lr39entry:40 %0 = bitcast <4 x float> %a to <4 x i32>41 %1 = bitcast <4 x float> %b to <4 x i32>42 %2 = and <4 x i32> %1, %043 %3 = bitcast <4 x i32> %2 to <4 x float>44 ret <4 x float> %345}46 47define arm_aapcs_vfpcc <16 x i8> @test_vandq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {48; CHECK-LABEL: test_vandq_m_s8:49; CHECK: @ %bb.0: @ %entry50; CHECK-NEXT: vmsr p0, r051; CHECK-NEXT: vpst52; CHECK-NEXT: vandt q0, q1, q253; CHECK-NEXT: bx lr54entry:55 %0 = zext i16 %p to i3256 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)57 %2 = tail call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)58 ret <16 x i8> %259}60 61declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #262 63declare <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #264 65define arm_aapcs_vfpcc <8 x i16> @test_vandq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {66; CHECK-LABEL: test_vandq_m_u16:67; CHECK: @ %bb.0: @ %entry68; CHECK-NEXT: vmsr p0, r069; CHECK-NEXT: vpst70; CHECK-NEXT: vandt q0, q1, q271; CHECK-NEXT: bx lr72entry:73 %0 = zext i16 %p to i3274 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)75 %2 = tail call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)76 ret <8 x i16> %277}78 79declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #280 81declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #282 83define arm_aapcs_vfpcc <4 x i32> @test_vandq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {84; CHECK-LABEL: test_vandq_m_s32:85; CHECK: @ %bb.0: @ %entry86; CHECK-NEXT: vmsr p0, r087; CHECK-NEXT: vpst88; CHECK-NEXT: vandt q0, q1, q289; CHECK-NEXT: bx lr90entry:91 %0 = zext i16 %p to i3292 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)93 %2 = tail call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)94 ret <4 x i32> %295}96 97declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #298 99declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2100 101define arm_aapcs_vfpcc <8 x half> @test_vandq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {102; CHECK-LABEL: test_vandq_m_f16:103; CHECK: @ %bb.0: @ %entry104; CHECK-NEXT: vmsr p0, r0105; CHECK-NEXT: vpst106; CHECK-NEXT: vandt q0, q1, q2107; CHECK-NEXT: bx lr108entry:109 %0 = bitcast <8 x half> %a to <8 x i16>110 %1 = bitcast <8 x half> %b to <8 x i16>111 %2 = zext i16 %p to i32112 %3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)113 %4 = bitcast <8 x half> %inactive to <8 x i16>114 %5 = tail call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %3, <8 x i16> %4)115 %6 = bitcast <8 x i16> %5 to <8 x half>116 ret <8 x half> %6117}118 119define arm_aapcs_vfpcc <16 x i8> @test_vandq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {120; CHECK-LABEL: test_vandq_x_u8:121; CHECK: @ %bb.0: @ %entry122; CHECK-NEXT: vmsr p0, r0123; CHECK-NEXT: vpst124; CHECK-NEXT: vandt q0, q0, q1125; CHECK-NEXT: bx lr126entry:127 %0 = zext i16 %p to i32128 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)129 %2 = tail call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)130 ret <16 x i8> %2131}132 133define arm_aapcs_vfpcc <8 x i16> @test_vandq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {134; CHECK-LABEL: test_vandq_x_s16:135; CHECK: @ %bb.0: @ %entry136; CHECK-NEXT: vmsr p0, r0137; CHECK-NEXT: vpst138; CHECK-NEXT: vandt q0, q0, q1139; CHECK-NEXT: bx lr140entry:141 %0 = zext i16 %p to i32142 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)143 %2 = tail call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)144 ret <8 x i16> %2145}146 147define arm_aapcs_vfpcc <4 x i32> @test_vandq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {148; CHECK-LABEL: test_vandq_x_u32:149; CHECK: @ %bb.0: @ %entry150; CHECK-NEXT: vmsr p0, r0151; CHECK-NEXT: vpst152; CHECK-NEXT: vandt q0, q0, q1153; CHECK-NEXT: bx lr154entry:155 %0 = zext i16 %p to i32156 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)157 %2 = tail call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)158 ret <4 x i32> %2159}160 161define arm_aapcs_vfpcc <4 x float> @test_vandq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {162; CHECK-LABEL: test_vandq_m_f32:163; CHECK: @ %bb.0: @ %entry164; CHECK-NEXT: vmsr p0, r0165; CHECK-NEXT: vpst166; CHECK-NEXT: vandt q0, q0, q1167; CHECK-NEXT: bx lr168entry:169 %0 = bitcast <4 x float> %a to <4 x i32>170 %1 = bitcast <4 x float> %b to <4 x i32>171 %2 = zext i16 %p to i32172 %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)173 %4 = tail call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> undef)174 %5 = bitcast <4 x i32> %4 to <4 x float>175 ret <4 x float> %5176}177 178