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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {5; CHECK-LABEL: test_vbicq_u8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vbic q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>11 %1 = and <16 x i8> %0, %a12 ret <16 x i8> %113}14 15define arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {16; CHECK-LABEL: test_vbicq_s16:17; CHECK: @ %bb.0: @ %entry18; CHECK-NEXT: vbic q0, q0, q119; CHECK-NEXT: bx lr20entry:21 %0 = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>22 %1 = and <8 x i16> %0, %a23 ret <8 x i16> %124}25 26define arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {27; CHECK-LABEL: test_vbicq_u32:28; CHECK: @ %bb.0: @ %entry29; CHECK-NEXT: vbic q0, q0, q130; CHECK-NEXT: bx lr31entry:32 %0 = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>33 %1 = and <4 x i32> %0, %a34 ret <4 x i32> %135}36 37define arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {38; CHECK-LABEL: test_vbicq_f32:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: vbic q0, q0, q141; CHECK-NEXT: bx lr42entry:43 %0 = bitcast <4 x float> %a to <4 x i32>44 %1 = bitcast <4 x float> %b to <4 x i32>45 %2 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>46 %3 = and <4 x i32> %2, %047 %4 = bitcast <4 x i32> %3 to <4 x float>48 ret <4 x float> %449}50 51define arm_aapcs_vfpcc <16 x i8> @test_vbicq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {52; CHECK-LABEL: test_vbicq_m_s8:53; CHECK: @ %bb.0: @ %entry54; CHECK-NEXT: vmsr p0, r055; CHECK-NEXT: vpst56; CHECK-NEXT: vbict q0, q1, q257; CHECK-NEXT: bx lr58entry:59 %0 = zext i16 %p to i3260 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)61 %2 = tail call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)62 ret <16 x i8> %263}64 65declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #266 67declare <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #268 69define arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {70; CHECK-LABEL: test_vbicq_m_u16:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: vmsr p0, r073; CHECK-NEXT: vpst74; CHECK-NEXT: vbict q0, q1, q275; CHECK-NEXT: bx lr76entry:77 %0 = zext i16 %p to i3278 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)79 %2 = tail call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)80 ret <8 x i16> %281}82 83declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #284 85declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #286 87define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {88; CHECK-LABEL: test_vbicq_m_s32:89; CHECK: @ %bb.0: @ %entry90; CHECK-NEXT: vmsr p0, r091; CHECK-NEXT: vpst92; CHECK-NEXT: vbict q0, q1, q293; CHECK-NEXT: bx lr94entry:95 %0 = zext i16 %p to i3296 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)97 %2 = tail call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)98 ret <4 x i32> %299}100 101declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2102 103declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2104 105define arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {106; CHECK-LABEL: test_vbicq_m_f16:107; CHECK: @ %bb.0: @ %entry108; CHECK-NEXT: vmsr p0, r0109; CHECK-NEXT: vpst110; CHECK-NEXT: vbict q0, q1, q2111; CHECK-NEXT: bx lr112entry:113 %0 = bitcast <8 x half> %a to <8 x i16>114 %1 = bitcast <8 x half> %b to <8 x i16>115 %2 = zext i16 %p to i32116 %3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)117 %4 = bitcast <8 x half> %inactive to <8 x i16>118 %5 = tail call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %3, <8 x i16> %4)119 %6 = bitcast <8 x i16> %5 to <8 x half>120 ret <8 x half> %6121}122 123define arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {124; CHECK-LABEL: test_vbicq_x_u8:125; CHECK: @ %bb.0: @ %entry126; CHECK-NEXT: vmsr p0, r0127; CHECK-NEXT: vpst128; CHECK-NEXT: vbict q0, q0, q1129; CHECK-NEXT: bx lr130entry:131 %0 = zext i16 %p to i32132 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)133 %2 = tail call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)134 ret <16 x i8> %2135}136 137define arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {138; CHECK-LABEL: test_vbicq_x_s16:139; CHECK: @ %bb.0: @ %entry140; CHECK-NEXT: vmsr p0, r0141; CHECK-NEXT: vpst142; CHECK-NEXT: vbict q0, q0, q1143; CHECK-NEXT: bx lr144entry:145 %0 = zext i16 %p to i32146 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)147 %2 = tail call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)148 ret <8 x i16> %2149}150 151define arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {152; CHECK-LABEL: test_vbicq_x_u32:153; CHECK: @ %bb.0: @ %entry154; CHECK-NEXT: vmsr p0, r0155; CHECK-NEXT: vpst156; CHECK-NEXT: vbict q0, q0, q1157; CHECK-NEXT: bx lr158entry:159 %0 = zext i16 %p to i32160 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)161 %2 = tail call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)162 ret <4 x i32> %2163}164 165define arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {166; CHECK-LABEL: test_vbicq_m_f32:167; CHECK: @ %bb.0: @ %entry168; CHECK-NEXT: vmsr p0, r0169; CHECK-NEXT: vpst170; CHECK-NEXT: vbict q0, q0, q1171; CHECK-NEXT: bx lr172entry:173 %0 = bitcast <4 x float> %a to <4 x i32>174 %1 = bitcast <4 x float> %b to <4 x i32>175 %2 = zext i16 %p to i32176 %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)177 %4 = tail call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> undef)178 %5 = bitcast <4 x i32> %4 to <4 x float>179 ret <4 x float> %5180}181 182