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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)5declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)6declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)7 8declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>)9declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>)10declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>)11declare <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32, i32, <8 x half>, <8 x half>)12declare <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32, i32, <4 x float>, <4 x float>)13 14declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i1>)15declare <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>)16declare <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i1>)17declare <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32, i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>)18declare <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32, i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>)19 20define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> %a, <16 x i8> %b) {21; CHECK-LABEL: test_vcaddq_rot90_u8:22; CHECK: @ %bb.0: @ %entry23; CHECK-NEXT: vcadd.i8 q0, q0, q1, #9024; CHECK-NEXT: bx lr25entry:26 %0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %a, <16 x i8> %b)27 ret <16 x i8> %028}29 30define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> %a, <8 x i16> %b) {31; CHECK-LABEL: test_vcaddq_rot90_u16:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: vcadd.i16 q0, q0, q1, #9034; CHECK-NEXT: bx lr35entry:36 %0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %a, <8 x i16> %b)37 ret <8 x i16> %038}39 40define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> %a, <4 x i32> %b) {41; CHECK-LABEL: test_vcaddq_rot90_u32:42; CHECK: @ %bb.0: @ %entry43; CHECK-NEXT: vcadd.i32 q2, q0, q1, #9044; CHECK-NEXT: vmov q0, q245; CHECK-NEXT: bx lr46entry:47 %0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %a, <4 x i32> %b)48 ret <4 x i32> %049}50 51define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> %a, <16 x i8> %b) {52; CHECK-LABEL: test_vcaddq_rot90_s8:53; CHECK: @ %bb.0: @ %entry54; CHECK-NEXT: vcadd.i8 q0, q0, q1, #9055; CHECK-NEXT: bx lr56entry:57 %0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %a, <16 x i8> %b)58 ret <16 x i8> %059}60 61define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> %a, <8 x i16> %b) {62; CHECK-LABEL: test_vcaddq_rot90_s16:63; CHECK: @ %bb.0: @ %entry64; CHECK-NEXT: vcadd.i16 q0, q0, q1, #9065; CHECK-NEXT: bx lr66entry:67 %0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %a, <8 x i16> %b)68 ret <8 x i16> %069}70 71define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> %a, <4 x i32> %b) {72; CHECK-LABEL: test_vcaddq_rot90_s32:73; CHECK: @ %bb.0: @ %entry74; CHECK-NEXT: vcadd.i32 q2, q0, q1, #9075; CHECK-NEXT: vmov q0, q276; CHECK-NEXT: bx lr77entry:78 %0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %a, <4 x i32> %b)79 ret <4 x i32> %080}81 82define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> %a, <8 x half> %b) {83; CHECK-LABEL: test_vcaddq_rot90_f16:84; CHECK: @ %bb.0: @ %entry85; CHECK-NEXT: vcadd.f16 q0, q0, q1, #9086; CHECK-NEXT: bx lr87entry:88 %0 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> %a, <8 x half> %b)89 ret <8 x half> %090}91 92define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> %a, <4 x float> %b) {93; CHECK-LABEL: test_vcaddq_rot90_f32:94; CHECK: @ %bb.0: @ %entry95; CHECK-NEXT: vcadd.f32 q2, q0, q1, #9096; CHECK-NEXT: vmov q0, q297; CHECK-NEXT: bx lr98entry:99 %0 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> %a, <4 x float> %b)100 ret <4 x float> %0101}102 103define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> %a, <16 x i8> %b) {104; CHECK-LABEL: test_vcaddq_rot270_u8:105; CHECK: @ %bb.0: @ %entry106; CHECK-NEXT: vcadd.i8 q0, q0, q1, #270107; CHECK-NEXT: bx lr108entry:109 %0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %a, <16 x i8> %b)110 ret <16 x i8> %0111}112 113define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> %a, <8 x i16> %b) {114; CHECK-LABEL: test_vcaddq_rot270_u16:115; CHECK: @ %bb.0: @ %entry116; CHECK-NEXT: vcadd.i16 q0, q0, q1, #270117; CHECK-NEXT: bx lr118entry:119 %0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %a, <8 x i16> %b)120 ret <8 x i16> %0121}122 123define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> %a, <4 x i32> %b) {124; CHECK-LABEL: test_vcaddq_rot270_u32:125; CHECK: @ %bb.0: @ %entry126; CHECK-NEXT: vcadd.i32 q2, q0, q1, #270127; CHECK-NEXT: vmov q0, q2128; CHECK-NEXT: bx lr129entry:130 %0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %a, <4 x i32> %b)131 ret <4 x i32> %0132}133 134define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> %a, <16 x i8> %b) {135; CHECK-LABEL: test_vcaddq_rot270_s8:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vcadd.i8 q0, q0, q1, #270138; CHECK-NEXT: bx lr139entry:140 %0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %a, <16 x i8> %b)141 ret <16 x i8> %0142}143 144define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> %a, <8 x i16> %b) {145; CHECK-LABEL: test_vcaddq_rot270_s16:146; CHECK: @ %bb.0: @ %entry147; CHECK-NEXT: vcadd.i16 q0, q0, q1, #270148; CHECK-NEXT: bx lr149entry:150 %0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %a, <8 x i16> %b)151 ret <8 x i16> %0152}153 154define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> %a, <4 x i32> %b) {155; CHECK-LABEL: test_vcaddq_rot270_s32:156; CHECK: @ %bb.0: @ %entry157; CHECK-NEXT: vcadd.i32 q2, q0, q1, #270158; CHECK-NEXT: vmov q0, q2159; CHECK-NEXT: bx lr160entry:161 %0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %a, <4 x i32> %b)162 ret <4 x i32> %0163}164 165define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> %a, <8 x half> %b) {166; CHECK-LABEL: test_vcaddq_rot270_f16:167; CHECK: @ %bb.0: @ %entry168; CHECK-NEXT: vcadd.f16 q0, q0, q1, #270169; CHECK-NEXT: bx lr170entry:171 %0 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> %a, <8 x half> %b)172 ret <8 x half> %0173}174 175define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> %a, <4 x float> %b) {176; CHECK-LABEL: test_vcaddq_rot270_f32:177; CHECK: @ %bb.0: @ %entry178; CHECK-NEXT: vcadd.f32 q2, q0, q1, #270179; CHECK-NEXT: vmov q0, q2180; CHECK-NEXT: bx lr181entry:182 %0 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> %a, <4 x float> %b)183 ret <4 x float> %0184}185 186define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {187; CHECK-LABEL: test_vcaddq_rot90_m_u8:188; CHECK: @ %bb.0: @ %entry189; CHECK-NEXT: vmsr p0, r0190; CHECK-NEXT: vpst191; CHECK-NEXT: vcaddt.i8 q0, q1, q2, #90192; CHECK-NEXT: bx lr193entry:194 %0 = zext i16 %p to i32195 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)196 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)197 ret <16 x i8> %2198}199 200define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {201; CHECK-LABEL: test_vcaddq_rot90_m_u16:202; CHECK: @ %bb.0: @ %entry203; CHECK-NEXT: vmsr p0, r0204; CHECK-NEXT: vpst205; CHECK-NEXT: vcaddt.i16 q0, q1, q2, #90206; CHECK-NEXT: bx lr207entry:208 %0 = zext i16 %p to i32209 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)210 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)211 ret <8 x i16> %2212}213 214define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {215; CHECK-LABEL: test_vcaddq_rot90_m_u32:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vmsr p0, r0218; CHECK-NEXT: vpst219; CHECK-NEXT: vcaddt.i32 q0, q1, q2, #90220; CHECK-NEXT: bx lr221entry:222 %0 = zext i16 %p to i32223 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)224 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)225 ret <4 x i32> %2226}227 228define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {229; CHECK-LABEL: test_vcaddq_rot90_m_s8:230; CHECK: @ %bb.0: @ %entry231; CHECK-NEXT: vmsr p0, r0232; CHECK-NEXT: vpst233; CHECK-NEXT: vcaddt.i8 q0, q1, q2, #90234; CHECK-NEXT: bx lr235entry:236 %0 = zext i16 %p to i32237 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)238 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)239 ret <16 x i8> %2240}241 242define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {243; CHECK-LABEL: test_vcaddq_rot90_m_s16:244; CHECK: @ %bb.0: @ %entry245; CHECK-NEXT: vmsr p0, r0246; CHECK-NEXT: vpst247; CHECK-NEXT: vcaddt.i16 q0, q1, q2, #90248; CHECK-NEXT: bx lr249entry:250 %0 = zext i16 %p to i32251 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)252 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)253 ret <8 x i16> %2254}255 256define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {257; CHECK-LABEL: test_vcaddq_rot90_m_s32:258; CHECK: @ %bb.0: @ %entry259; CHECK-NEXT: vmsr p0, r0260; CHECK-NEXT: vpst261; CHECK-NEXT: vcaddt.i32 q0, q1, q2, #90262; CHECK-NEXT: bx lr263entry:264 %0 = zext i16 %p to i32265 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)266 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)267 ret <4 x i32> %2268}269 270define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {271; CHECK-LABEL: test_vcaddq_rot90_m_f16:272; CHECK: @ %bb.0: @ %entry273; CHECK-NEXT: vmsr p0, r0274; CHECK-NEXT: vpst275; CHECK-NEXT: vcaddt.f16 q0, q1, q2, #90276; CHECK-NEXT: bx lr277entry:278 %0 = zext i16 %p to i32279 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)280 %2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 0, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)281 ret <8 x half> %2282}283 284define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {285; CHECK-LABEL: test_vcaddq_rot90_m_f32:286; CHECK: @ %bb.0: @ %entry287; CHECK-NEXT: vmsr p0, r0288; CHECK-NEXT: vpst289; CHECK-NEXT: vcaddt.f32 q0, q1, q2, #90290; CHECK-NEXT: bx lr291entry:292 %0 = zext i16 %p to i32293 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)294 %2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 0, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)295 ret <4 x float> %2296}297 298define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {299; CHECK-LABEL: test_vcaddq_rot270_m_u8:300; CHECK: @ %bb.0: @ %entry301; CHECK-NEXT: vmsr p0, r0302; CHECK-NEXT: vpst303; CHECK-NEXT: vcaddt.i8 q0, q1, q2, #270304; CHECK-NEXT: bx lr305entry:306 %0 = zext i16 %p to i32307 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)308 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)309 ret <16 x i8> %2310}311 312define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {313; CHECK-LABEL: test_vcaddq_rot270_m_u16:314; CHECK: @ %bb.0: @ %entry315; CHECK-NEXT: vmsr p0, r0316; CHECK-NEXT: vpst317; CHECK-NEXT: vcaddt.i16 q0, q1, q2, #270318; CHECK-NEXT: bx lr319entry:320 %0 = zext i16 %p to i32321 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)322 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)323 ret <8 x i16> %2324}325 326define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {327; CHECK-LABEL: test_vcaddq_rot270_m_u32:328; CHECK: @ %bb.0: @ %entry329; CHECK-NEXT: vmsr p0, r0330; CHECK-NEXT: vpst331; CHECK-NEXT: vcaddt.i32 q0, q1, q2, #270332; CHECK-NEXT: bx lr333entry:334 %0 = zext i16 %p to i32335 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)336 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)337 ret <4 x i32> %2338}339 340define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {341; CHECK-LABEL: test_vcaddq_rot270_m_s8:342; CHECK: @ %bb.0: @ %entry343; CHECK-NEXT: vmsr p0, r0344; CHECK-NEXT: vpst345; CHECK-NEXT: vcaddt.i8 q0, q1, q2, #270346; CHECK-NEXT: bx lr347entry:348 %0 = zext i16 %p to i32349 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)350 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)351 ret <16 x i8> %2352}353 354define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {355; CHECK-LABEL: test_vcaddq_rot270_m_s16:356; CHECK: @ %bb.0: @ %entry357; CHECK-NEXT: vmsr p0, r0358; CHECK-NEXT: vpst359; CHECK-NEXT: vcaddt.i16 q0, q1, q2, #270360; CHECK-NEXT: bx lr361entry:362 %0 = zext i16 %p to i32363 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)364 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)365 ret <8 x i16> %2366}367 368define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {369; CHECK-LABEL: test_vcaddq_rot270_m_s32:370; CHECK: @ %bb.0: @ %entry371; CHECK-NEXT: vmsr p0, r0372; CHECK-NEXT: vpst373; CHECK-NEXT: vcaddt.i32 q0, q1, q2, #270374; CHECK-NEXT: bx lr375entry:376 %0 = zext i16 %p to i32377 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)378 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)379 ret <4 x i32> %2380}381 382define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {383; CHECK-LABEL: test_vcaddq_rot270_m_f16:384; CHECK: @ %bb.0: @ %entry385; CHECK-NEXT: vmsr p0, r0386; CHECK-NEXT: vpst387; CHECK-NEXT: vcaddt.f16 q0, q1, q2, #270388; CHECK-NEXT: bx lr389entry:390 %0 = zext i16 %p to i32391 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)392 %2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 1, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)393 ret <8 x half> %2394}395 396define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {397; CHECK-LABEL: test_vcaddq_rot270_m_f32:398; CHECK: @ %bb.0: @ %entry399; CHECK-NEXT: vmsr p0, r0400; CHECK-NEXT: vpst401; CHECK-NEXT: vcaddt.f32 q0, q1, q2, #270402; CHECK-NEXT: bx lr403entry:404 %0 = zext i16 %p to i32405 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)406 %2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 1, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)407 ret <4 x float> %2408}409 410define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {411; CHECK-LABEL: test_vcaddq_rot90_x_u8:412; CHECK: @ %bb.0: @ %entry413; CHECK-NEXT: vmsr p0, r0414; CHECK-NEXT: vpst415; CHECK-NEXT: vcaddt.i8 q0, q0, q1, #90416; CHECK-NEXT: bx lr417entry:418 %0 = zext i16 %p to i32419 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)420 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)421 ret <16 x i8> %2422}423 424define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {425; CHECK-LABEL: test_vcaddq_rot90_x_u16:426; CHECK: @ %bb.0: @ %entry427; CHECK-NEXT: vmsr p0, r0428; CHECK-NEXT: vpst429; CHECK-NEXT: vcaddt.i16 q0, q0, q1, #90430; CHECK-NEXT: bx lr431entry:432 %0 = zext i16 %p to i32433 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)434 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)435 ret <8 x i16> %2436}437 438define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {439; CHECK-LABEL: test_vcaddq_rot90_x_u32:440; CHECK: @ %bb.0: @ %entry441; CHECK-NEXT: vmsr p0, r0442; CHECK-NEXT: vpst443; CHECK-NEXT: vcaddt.i32 q2, q0, q1, #90444; CHECK-NEXT: vmov q0, q2445; CHECK-NEXT: bx lr446entry:447 %0 = zext i16 %p to i32448 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)449 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)450 ret <4 x i32> %2451}452 453define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {454; CHECK-LABEL: test_vcaddq_rot90_x_s8:455; CHECK: @ %bb.0: @ %entry456; CHECK-NEXT: vmsr p0, r0457; CHECK-NEXT: vpst458; CHECK-NEXT: vcaddt.i8 q0, q0, q1, #90459; CHECK-NEXT: bx lr460entry:461 %0 = zext i16 %p to i32462 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)463 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)464 ret <16 x i8> %2465}466 467define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {468; CHECK-LABEL: test_vcaddq_rot90_x_s16:469; CHECK: @ %bb.0: @ %entry470; CHECK-NEXT: vmsr p0, r0471; CHECK-NEXT: vpst472; CHECK-NEXT: vcaddt.i16 q0, q0, q1, #90473; CHECK-NEXT: bx lr474entry:475 %0 = zext i16 %p to i32476 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)477 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)478 ret <8 x i16> %2479}480 481define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {482; CHECK-LABEL: test_vcaddq_rot90_x_s32:483; CHECK: @ %bb.0: @ %entry484; CHECK-NEXT: vmsr p0, r0485; CHECK-NEXT: vpst486; CHECK-NEXT: vcaddt.i32 q2, q0, q1, #90487; CHECK-NEXT: vmov q0, q2488; CHECK-NEXT: bx lr489entry:490 %0 = zext i16 %p to i32491 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)492 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)493 ret <4 x i32> %2494}495 496define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {497; CHECK-LABEL: test_vcaddq_rot90_x_f16:498; CHECK: @ %bb.0: @ %entry499; CHECK-NEXT: vmsr p0, r0500; CHECK-NEXT: vpst501; CHECK-NEXT: vcaddt.f16 q0, q0, q1, #90502; CHECK-NEXT: bx lr503entry:504 %0 = zext i16 %p to i32505 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)506 %2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 0, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)507 ret <8 x half> %2508}509 510define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {511; CHECK-LABEL: test_vcaddq_rot90_x_f32:512; CHECK: @ %bb.0: @ %entry513; CHECK-NEXT: vmsr p0, r0514; CHECK-NEXT: vpst515; CHECK-NEXT: vcaddt.f32 q2, q0, q1, #90516; CHECK-NEXT: vmov q0, q2517; CHECK-NEXT: bx lr518entry:519 %0 = zext i16 %p to i32520 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)521 %2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 0, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)522 ret <4 x float> %2523}524 525define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {526; CHECK-LABEL: test_vcaddq_rot270_x_u8:527; CHECK: @ %bb.0: @ %entry528; CHECK-NEXT: vmsr p0, r0529; CHECK-NEXT: vpst530; CHECK-NEXT: vcaddt.i8 q0, q0, q1, #270531; CHECK-NEXT: bx lr532entry:533 %0 = zext i16 %p to i32534 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)535 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)536 ret <16 x i8> %2537}538 539define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {540; CHECK-LABEL: test_vcaddq_rot270_x_u16:541; CHECK: @ %bb.0: @ %entry542; CHECK-NEXT: vmsr p0, r0543; CHECK-NEXT: vpst544; CHECK-NEXT: vcaddt.i16 q0, q0, q1, #270545; CHECK-NEXT: bx lr546entry:547 %0 = zext i16 %p to i32548 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)549 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)550 ret <8 x i16> %2551}552 553define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {554; CHECK-LABEL: test_vcaddq_rot270_x_u32:555; CHECK: @ %bb.0: @ %entry556; CHECK-NEXT: vmsr p0, r0557; CHECK-NEXT: vpst558; CHECK-NEXT: vcaddt.i32 q2, q0, q1, #270559; CHECK-NEXT: vmov q0, q2560; CHECK-NEXT: bx lr561entry:562 %0 = zext i16 %p to i32563 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)564 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)565 ret <4 x i32> %2566}567 568define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {569; CHECK-LABEL: test_vcaddq_rot270_x_s8:570; CHECK: @ %bb.0: @ %entry571; CHECK-NEXT: vmsr p0, r0572; CHECK-NEXT: vpst573; CHECK-NEXT: vcaddt.i8 q0, q0, q1, #270574; CHECK-NEXT: bx lr575entry:576 %0 = zext i16 %p to i32577 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)578 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)579 ret <16 x i8> %2580}581 582define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {583; CHECK-LABEL: test_vcaddq_rot270_x_s16:584; CHECK: @ %bb.0: @ %entry585; CHECK-NEXT: vmsr p0, r0586; CHECK-NEXT: vpst587; CHECK-NEXT: vcaddt.i16 q0, q0, q1, #270588; CHECK-NEXT: bx lr589entry:590 %0 = zext i16 %p to i32591 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)592 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)593 ret <8 x i16> %2594}595 596define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {597; CHECK-LABEL: test_vcaddq_rot270_x_s32:598; CHECK: @ %bb.0: @ %entry599; CHECK-NEXT: vmsr p0, r0600; CHECK-NEXT: vpst601; CHECK-NEXT: vcaddt.i32 q2, q0, q1, #270602; CHECK-NEXT: vmov q0, q2603; CHECK-NEXT: bx lr604entry:605 %0 = zext i16 %p to i32606 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)607 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)608 ret <4 x i32> %2609}610 611define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {612; CHECK-LABEL: test_vcaddq_rot270_x_f16:613; CHECK: @ %bb.0: @ %entry614; CHECK-NEXT: vmsr p0, r0615; CHECK-NEXT: vpst616; CHECK-NEXT: vcaddt.f16 q0, q0, q1, #270617; CHECK-NEXT: bx lr618entry:619 %0 = zext i16 %p to i32620 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)621 %2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 1, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)622 ret <8 x half> %2623}624 625define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {626; CHECK-LABEL: test_vcaddq_rot270_x_f32:627; CHECK: @ %bb.0: @ %entry628; CHECK-NEXT: vmsr p0, r0629; CHECK-NEXT: vpst630; CHECK-NEXT: vcaddt.f32 q2, q0, q1, #270631; CHECK-NEXT: vmov q0, q2632; CHECK-NEXT: bx lr633entry:634 %0 = zext i16 %p to i32635 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)636 %2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 1, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)637 ret <4 x float> %2638}639 640define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> %a, <16 x i8> %b) {641; CHECK-LABEL: test_vhcaddq_rot90_s8:642; CHECK: @ %bb.0: @ %entry643; CHECK-NEXT: vhcadd.s8 q0, q0, q1, #90644; CHECK-NEXT: bx lr645entry:646 %0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %a, <16 x i8> %b)647 ret <16 x i8> %0648}649 650define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> %a, <8 x i16> %b) {651; CHECK-LABEL: test_vhcaddq_rot90_s16:652; CHECK: @ %bb.0: @ %entry653; CHECK-NEXT: vhcadd.s16 q0, q0, q1, #90654; CHECK-NEXT: bx lr655entry:656 %0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %a, <8 x i16> %b)657 ret <8 x i16> %0658}659 660define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> %a, <4 x i32> %b) {661; CHECK-LABEL: test_vhcaddq_rot90_s32:662; CHECK: @ %bb.0: @ %entry663; CHECK-NEXT: vhcadd.s32 q2, q0, q1, #90664; CHECK-NEXT: vmov q0, q2665; CHECK-NEXT: bx lr666entry:667 %0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %a, <4 x i32> %b)668 ret <4 x i32> %0669}670 671define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> %a, <16 x i8> %b) {672; CHECK-LABEL: test_vhcaddq_rot270_s8:673; CHECK: @ %bb.0: @ %entry674; CHECK-NEXT: vhcadd.s8 q0, q0, q1, #270675; CHECK-NEXT: bx lr676entry:677 %0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %a, <16 x i8> %b)678 ret <16 x i8> %0679}680 681define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> %a, <8 x i16> %b) {682; CHECK-LABEL: test_vhcaddq_rot270_s16:683; CHECK: @ %bb.0: @ %entry684; CHECK-NEXT: vhcadd.s16 q0, q0, q1, #270685; CHECK-NEXT: bx lr686entry:687 %0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %a, <8 x i16> %b)688 ret <8 x i16> %0689}690 691define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> %a, <4 x i32> %b) {692; CHECK-LABEL: test_vhcaddq_rot270_s32:693; CHECK: @ %bb.0: @ %entry694; CHECK-NEXT: vhcadd.s32 q2, q0, q1, #270695; CHECK-NEXT: vmov q0, q2696; CHECK-NEXT: bx lr697entry:698 %0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %a, <4 x i32> %b)699 ret <4 x i32> %0700}701 702define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32_undef() {703; CHECK-LABEL: test_vhcaddq_rot270_s32_undef:704; CHECK: @ %bb.0: @ %entry705; CHECK-NEXT: vhcadd.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}, #270706; CHECK-NOT: vhcadd.s32 q[[REG:[0-9]+]], q{{[0-9]+}}, q[[REG]], #270707; CHECK-NEXT: bx lr708entry:709 %0 = tail call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> undef, <4 x i32> undef)710 ret <4 x i32> %0711}712 713define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32_undef_inline_asm() {714; CHECK-LABEL: test_vhcaddq_rot270_s32_undef_inline_asm:715; CHECK: @ %bb.0: @ %entry716; CHECK-NEXT: @APP717; CHECK-NEXT: vhcadd.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}, #270718; CHECK-NOT: vhcadd.s32 q[[REG:[0-9]+]], q{{[0-9]+}}, q[[REG]], #270719; CHECK-NEXT: @NO_APP720; CHECK-NEXT: bx lr721entry:722 %0 = call <4 x i32> asm sideeffect "vhcadd.s32 ${0}, ${1}, ${2}, #270", "=&w,w,w,~{memory}"(<4 x i32> undef, <4 x i32> undef)723 ret <4 x i32> %0724}725 726define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {727; CHECK-LABEL: test_vhcaddq_rot90_x_s8:728; CHECK: @ %bb.0: @ %entry729; CHECK-NEXT: vmsr p0, r0730; CHECK-NEXT: vpst731; CHECK-NEXT: vhcaddt.s8 q0, q0, q1, #90732; CHECK-NEXT: bx lr733entry:734 %0 = zext i16 %p to i32735 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)736 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)737 ret <16 x i8> %2738}739 740define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {741; CHECK-LABEL: test_vhcaddq_rot90_x_s16:742; CHECK: @ %bb.0: @ %entry743; CHECK-NEXT: vmsr p0, r0744; CHECK-NEXT: vpst745; CHECK-NEXT: vhcaddt.s16 q0, q0, q1, #90746; CHECK-NEXT: bx lr747entry:748 %0 = zext i16 %p to i32749 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)750 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)751 ret <8 x i16> %2752}753 754define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {755; CHECK-LABEL: test_vhcaddq_rot90_x_s32:756; CHECK: @ %bb.0: @ %entry757; CHECK-NEXT: vmsr p0, r0758; CHECK-NEXT: vpst759; CHECK-NEXT: vhcaddt.s32 q2, q0, q1, #90760; CHECK-NEXT: vmov q0, q2761; CHECK-NEXT: bx lr762entry:763 %0 = zext i16 %p to i32764 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)765 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)766 ret <4 x i32> %2767}768 769define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {770; CHECK-LABEL: test_vhcaddq_rot270_x_s8:771; CHECK: @ %bb.0: @ %entry772; CHECK-NEXT: vmsr p0, r0773; CHECK-NEXT: vpst774; CHECK-NEXT: vhcaddt.s8 q0, q0, q1, #270775; CHECK-NEXT: bx lr776entry:777 %0 = zext i16 %p to i32778 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)779 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)780 ret <16 x i8> %2781}782 783define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {784; CHECK-LABEL: test_vhcaddq_rot270_x_s16:785; CHECK: @ %bb.0: @ %entry786; CHECK-NEXT: vmsr p0, r0787; CHECK-NEXT: vpst788; CHECK-NEXT: vhcaddt.s16 q0, q0, q1, #270789; CHECK-NEXT: bx lr790entry:791 %0 = zext i16 %p to i32792 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)793 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)794 ret <8 x i16> %2795}796 797define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {798; CHECK-LABEL: test_vhcaddq_rot270_x_s32:799; CHECK: @ %bb.0: @ %entry800; CHECK-NEXT: vmsr p0, r0801; CHECK-NEXT: vpst802; CHECK-NEXT: vhcaddt.s32 q2, q0, q1, #270803; CHECK-NEXT: vmov q0, q2804; CHECK-NEXT: bx lr805entry:806 %0 = zext i16 %p to i32807 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)808 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)809 ret <4 x i32> %2810}811 812define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {813; CHECK-LABEL: test_vhcaddq_rot90_m_s8:814; CHECK: @ %bb.0: @ %entry815; CHECK-NEXT: vmsr p0, r0816; CHECK-NEXT: vpst817; CHECK-NEXT: vhcaddt.s8 q0, q1, q2, #90818; CHECK-NEXT: bx lr819entry:820 %0 = zext i16 %p to i32821 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)822 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)823 ret <16 x i8> %2824}825 826define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {827; CHECK-LABEL: test_vhcaddq_rot90_m_s16:828; CHECK: @ %bb.0: @ %entry829; CHECK-NEXT: vmsr p0, r0830; CHECK-NEXT: vpst831; CHECK-NEXT: vhcaddt.s16 q0, q1, q2, #90832; CHECK-NEXT: bx lr833entry:834 %0 = zext i16 %p to i32835 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)836 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)837 ret <8 x i16> %2838}839 840define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {841; CHECK-LABEL: test_vhcaddq_rot90_m_s32:842; CHECK: @ %bb.0: @ %entry843; CHECK-NEXT: vmsr p0, r0844; CHECK-NEXT: vpst845; CHECK-NEXT: vhcaddt.s32 q0, q1, q2, #90846; CHECK-NEXT: bx lr847entry:848 %0 = zext i16 %p to i32849 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)850 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)851 ret <4 x i32> %2852}853 854define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {855; CHECK-LABEL: test_vhcaddq_rot270_m_s8:856; CHECK: @ %bb.0: @ %entry857; CHECK-NEXT: vmsr p0, r0858; CHECK-NEXT: vpst859; CHECK-NEXT: vhcaddt.s8 q0, q1, q2, #270860; CHECK-NEXT: bx lr861entry:862 %0 = zext i16 %p to i32863 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)864 %2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)865 ret <16 x i8> %2866}867 868define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {869; CHECK-LABEL: test_vhcaddq_rot270_m_s16:870; CHECK: @ %bb.0: @ %entry871; CHECK-NEXT: vmsr p0, r0872; CHECK-NEXT: vpst873; CHECK-NEXT: vhcaddt.s16 q0, q1, q2, #270874; CHECK-NEXT: bx lr875entry:876 %0 = zext i16 %p to i32877 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)878 %2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)879 ret <8 x i16> %2880}881 882define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {883; CHECK-LABEL: test_vhcaddq_rot270_m_s32:884; CHECK: @ %bb.0: @ %entry885; CHECK-NEXT: vmsr p0, r0886; CHECK-NEXT: vpst887; CHECK-NEXT: vhcaddt.s32 q0, q1, q2, #270888; CHECK-NEXT: bx lr889entry:890 %0 = zext i16 %p to i32891 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)892 %2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)893 ret <4 x i32> %2894}895