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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)5declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)6 7declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>)8declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>)9 10declare <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>)11declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>)12 13 14define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {15; CHECK-LABEL: test_vcmlaq_f16:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vcmla.f16 q0, q1, q2, #018; CHECK-NEXT: bx lr19entry:20 %0 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> %a, <8 x half> %b, <8 x half> %c)21 ret <8 x half> %022}23 24define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {25; CHECK-LABEL: test_vcmlaq_f32:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vcmla.f32 q0, q1, q2, #028; CHECK-NEXT: bx lr29entry:30 %0 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %a, <4 x float> %b, <4 x float> %c)31 ret <4 x float> %032}33 34 35define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {36; CHECK-LABEL: test_vcmlaq_rot90_f16:37; CHECK: @ %bb.0: @ %entry38; CHECK-NEXT: vcmla.f16 q0, q1, q2, #9039; CHECK-NEXT: bx lr40entry:41 %0 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 1, <8 x half> %a, <8 x half> %b, <8 x half> %c)42 ret <8 x half> %043}44 45define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {46; CHECK-LABEL: test_vcmlaq_rot90_f32:47; CHECK: @ %bb.0: @ %entry48; CHECK-NEXT: vcmla.f32 q0, q1, q2, #9049; CHECK-NEXT: bx lr50entry:51 %0 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %a, <4 x float> %b, <4 x float> %c)52 ret <4 x float> %053}54 55define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {56; CHECK-LABEL: test_vcmlaq_rot180_f16:57; CHECK: @ %bb.0: @ %entry58; CHECK-NEXT: vcmla.f16 q0, q1, q2, #18059; CHECK-NEXT: bx lr60entry:61 %0 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> %a, <8 x half> %b, <8 x half> %c)62 ret <8 x half> %063}64 65define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {66; CHECK-LABEL: test_vcmlaq_rot180_f32:67; CHECK: @ %bb.0: @ %entry68; CHECK-NEXT: vcmla.f32 q0, q1, q2, #18069; CHECK-NEXT: bx lr70entry:71 %0 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 2, <4 x float> %a, <4 x float> %b, <4 x float> %c)72 ret <4 x float> %073}74 75define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {76; CHECK-LABEL: test_vcmlaq_rot270_f16:77; CHECK: @ %bb.0: @ %entry78; CHECK-NEXT: vcmla.f16 q0, q1, q2, #27079; CHECK-NEXT: bx lr80entry:81 %0 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> %a, <8 x half> %b, <8 x half> %c)82 ret <8 x half> %083}84 85define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {86; CHECK-LABEL: test_vcmlaq_rot270_f32:87; CHECK: @ %bb.0: @ %entry88; CHECK-NEXT: vcmla.f32 q0, q1, q2, #27089; CHECK-NEXT: bx lr90entry:91 %0 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 3, <4 x float> %a, <4 x float> %b, <4 x float> %c)92 ret <4 x float> %093}94 95define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {96; CHECK-LABEL: test_vcmlaq_m_f16:97; CHECK: @ %bb.0: @ %entry98; CHECK-NEXT: vmsr p0, r099; CHECK-NEXT: vpst100; CHECK-NEXT: vcmlat.f16 q0, q1, q2, #0101; CHECK-NEXT: bx lr102entry:103 %0 = zext i16 %p to i32104 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)105 %2 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 0, <8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> %1)106 ret <8 x half> %2107}108 109define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_m_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, i16 zeroext %p) {110; CHECK-LABEL: test_vcmlaq_m_f32:111; CHECK: @ %bb.0: @ %entry112; CHECK-NEXT: vmsr p0, r0113; CHECK-NEXT: vpst114; CHECK-NEXT: vcmlat.f32 q0, q1, q2, #0115; CHECK-NEXT: bx lr116entry:117 %0 = zext i16 %p to i32118 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)119 %2 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %1)120 ret <4 x float> %2121}122 123define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {124; CHECK-LABEL: test_vcmlaq_rot90_m_f16:125; CHECK: @ %bb.0: @ %entry126; CHECK-NEXT: vmsr p0, r0127; CHECK-NEXT: vpst128; CHECK-NEXT: vcmlat.f16 q0, q1, q2, #90129; CHECK-NEXT: bx lr130entry:131 %0 = zext i16 %p to i32132 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)133 %2 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 1, <8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> %1)134 ret <8 x half> %2135}136 137define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_m_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, i16 zeroext %p) {138; CHECK-LABEL: test_vcmlaq_rot90_m_f32:139; CHECK: @ %bb.0: @ %entry140; CHECK-NEXT: vmsr p0, r0141; CHECK-NEXT: vpst142; CHECK-NEXT: vcmlat.f32 q0, q1, q2, #90143; CHECK-NEXT: bx lr144entry:145 %0 = zext i16 %p to i32146 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)147 %2 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 1, <4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %1)148 ret <4 x float> %2149}150 151define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {152; CHECK-LABEL: test_vcmlaq_rot180_m_f16:153; CHECK: @ %bb.0: @ %entry154; CHECK-NEXT: vmsr p0, r0155; CHECK-NEXT: vpst156; CHECK-NEXT: vcmlat.f16 q0, q1, q2, #180157; CHECK-NEXT: bx lr158entry:159 %0 = zext i16 %p to i32160 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)161 %2 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 2, <8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> %1)162 ret <8 x half> %2163}164 165define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_m_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, i16 zeroext %p) {166; CHECK-LABEL: test_vcmlaq_rot180_m_f32:167; CHECK: @ %bb.0: @ %entry168; CHECK-NEXT: vmsr p0, r0169; CHECK-NEXT: vpst170; CHECK-NEXT: vcmlat.f32 q0, q1, q2, #180171; CHECK-NEXT: bx lr172entry:173 %0 = zext i16 %p to i32174 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)175 %2 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 2, <4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %1)176 ret <4 x float> %2177}178 179define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {180; CHECK-LABEL: test_vcmlaq_rot270_m_f16:181; CHECK: @ %bb.0: @ %entry182; CHECK-NEXT: vmsr p0, r0183; CHECK-NEXT: vpst184; CHECK-NEXT: vcmlat.f16 q0, q1, q2, #270185; CHECK-NEXT: bx lr186entry:187 %0 = zext i16 %p to i32188 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)189 %2 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 3, <8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> %1)190 ret <8 x half> %2191}192 193define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_m_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, i16 zeroext %p) {194; CHECK-LABEL: test_vcmlaq_rot270_m_f32:195; CHECK: @ %bb.0: @ %entry196; CHECK-NEXT: vmsr p0, r0197; CHECK-NEXT: vpst198; CHECK-NEXT: vcmlat.f32 q0, q1, q2, #270199; CHECK-NEXT: bx lr200entry:201 %0 = zext i16 %p to i32202 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)203 %2 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 3, <4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %1)204 ret <4 x float> %2205}206