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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)5declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)6 7declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>)8declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>)9 10declare <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>)11declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>)12 13define arm_aapcs_vfpcc <8 x half> @test_vcmulq_f16(<8 x half> %a, <8 x half> %b) {14; CHECK-LABEL: test_vcmulq_f16:15; CHECK: @ %bb.0: @ %entry16; CHECK-NEXT: vcmul.f16 q0, q0, q1, #017; CHECK-NEXT: bx lr18entry:19 %0 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> %a, <8 x half> %b)20 ret <8 x half> %021}22 23define arm_aapcs_vfpcc <4 x float> @test_vcmulq_f32(<4 x float> %a, <4 x float> %b) {24; CHECK-LABEL: test_vcmulq_f32:25; CHECK: @ %bb.0: @ %entry26; CHECK-NEXT: vcmul.f32 q2, q0, q1, #027; CHECK-NEXT: vmov q0, q228; CHECK-NEXT: bx lr29entry:30 %0 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %a, <4 x float> %b)31 ret <4 x float> %032}33 34define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_f16(<8 x half> %a, <8 x half> %b) {35; CHECK-LABEL: test_vcmulq_rot90_f16:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vcmul.f16 q0, q0, q1, #9038; CHECK-NEXT: bx lr39entry:40 %0 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> %a, <8 x half> %b)41 ret <8 x half> %042}43 44define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_f32(<4 x float> %a, <4 x float> %b) {45; CHECK-LABEL: test_vcmulq_rot90_f32:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vcmul.f32 q2, q0, q1, #9048; CHECK-NEXT: vmov q0, q249; CHECK-NEXT: bx lr50entry:51 %0 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %a, <4 x float> %b)52 ret <4 x float> %053}54 55define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_f16(<8 x half> %a, <8 x half> %b) {56; CHECK-LABEL: test_vcmulq_rot180_f16:57; CHECK: @ %bb.0: @ %entry58; CHECK-NEXT: vcmul.f16 q0, q0, q1, #18059; CHECK-NEXT: bx lr60entry:61 %0 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %a, <8 x half> %b)62 ret <8 x half> %063}64 65define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_f32(<4 x float> %a, <4 x float> %b) {66; CHECK-LABEL: test_vcmulq_rot180_f32:67; CHECK: @ %bb.0: @ %entry68; CHECK-NEXT: vcmul.f32 q2, q0, q1, #18069; CHECK-NEXT: vmov q0, q270; CHECK-NEXT: bx lr71entry:72 %0 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> %a, <4 x float> %b)73 ret <4 x float> %074}75 76define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_f16(<8 x half> %a, <8 x half> %b) {77; CHECK-LABEL: test_vcmulq_rot270_f16:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vcmul.f16 q0, q0, q1, #27080; CHECK-NEXT: bx lr81entry:82 %0 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %a, <8 x half> %b)83 ret <8 x half> %084}85 86define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_f32(<4 x float> %a, <4 x float> %b) {87; CHECK-LABEL: test_vcmulq_rot270_f32:88; CHECK: @ %bb.0: @ %entry89; CHECK-NEXT: vcmul.f32 q2, q0, q1, #27090; CHECK-NEXT: vmov q0, q291; CHECK-NEXT: bx lr92entry:93 %0 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> %a, <4 x float> %b)94 ret <4 x float> %095}96 97define arm_aapcs_vfpcc <8 x half> @test_vcmulq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {98; CHECK-LABEL: test_vcmulq_m_f16:99; CHECK: @ %bb.0: @ %entry100; CHECK-NEXT: vmsr p0, r0101; CHECK-NEXT: vpst102; CHECK-NEXT: vcmult.f16 q0, q1, q2, #0103; CHECK-NEXT: bx lr104entry:105 %0 = zext i16 %p to i32106 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)107 %2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)108 ret <8 x half> %2109}110 111define arm_aapcs_vfpcc <4 x float> @test_vcmulq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {112; CHECK-LABEL: test_vcmulq_m_f32:113; CHECK: @ %bb.0: @ %entry114; CHECK-NEXT: vmsr p0, r0115; CHECK-NEXT: vpst116; CHECK-NEXT: vcmult.f32 q0, q1, q2, #0117; CHECK-NEXT: bx lr118entry:119 %0 = zext i16 %p to i32120 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)121 %2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)122 ret <4 x float> %2123}124 125define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {126; CHECK-LABEL: test_vcmulq_rot90_m_f16:127; CHECK: @ %bb.0: @ %entry128; CHECK-NEXT: vmsr p0, r0129; CHECK-NEXT: vpst130; CHECK-NEXT: vcmult.f16 q0, q1, q2, #90131; CHECK-NEXT: bx lr132entry:133 %0 = zext i16 %p to i32134 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)135 %2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)136 ret <8 x half> %2137}138 139define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {140; CHECK-LABEL: test_vcmulq_rot90_m_f32:141; CHECK: @ %bb.0: @ %entry142; CHECK-NEXT: vmsr p0, r0143; CHECK-NEXT: vpst144; CHECK-NEXT: vcmult.f32 q0, q1, q2, #90145; CHECK-NEXT: bx lr146entry:147 %0 = zext i16 %p to i32148 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)149 %2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)150 ret <4 x float> %2151}152 153define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {154; CHECK-LABEL: test_vcmulq_rot180_m_f16:155; CHECK: @ %bb.0: @ %entry156; CHECK-NEXT: vmsr p0, r0157; CHECK-NEXT: vpst158; CHECK-NEXT: vcmult.f16 q0, q1, q2, #180159; CHECK-NEXT: bx lr160entry:161 %0 = zext i16 %p to i32162 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)163 %2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 2, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)164 ret <8 x half> %2165}166 167define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {168; CHECK-LABEL: test_vcmulq_rot180_m_f32:169; CHECK: @ %bb.0: @ %entry170; CHECK-NEXT: vmsr p0, r0171; CHECK-NEXT: vpst172; CHECK-NEXT: vcmult.f32 q0, q1, q2, #180173; CHECK-NEXT: bx lr174entry:175 %0 = zext i16 %p to i32176 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)177 %2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 2, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)178 ret <4 x float> %2179}180 181define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {182; CHECK-LABEL: test_vcmulq_rot270_m_f16:183; CHECK: @ %bb.0: @ %entry184; CHECK-NEXT: vmsr p0, r0185; CHECK-NEXT: vpst186; CHECK-NEXT: vcmult.f16 q0, q1, q2, #270187; CHECK-NEXT: bx lr188entry:189 %0 = zext i16 %p to i32190 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)191 %2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 3, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)192 ret <8 x half> %2193}194 195define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {196; CHECK-LABEL: test_vcmulq_rot270_m_f32:197; CHECK: @ %bb.0: @ %entry198; CHECK-NEXT: vmsr p0, r0199; CHECK-NEXT: vpst200; CHECK-NEXT: vcmult.f32 q0, q1, q2, #270201; CHECK-NEXT: bx lr202entry:203 %0 = zext i16 %p to i32204 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)205 %2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 3, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)206 ret <4 x float> %2207}208 209define arm_aapcs_vfpcc <8 x half> @test_vcmulq_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {210; CHECK-LABEL: test_vcmulq_x_f16:211; CHECK: @ %bb.0: @ %entry212; CHECK-NEXT: vmsr p0, r0213; CHECK-NEXT: vpst214; CHECK-NEXT: vcmult.f16 q0, q0, q1, #0215; CHECK-NEXT: bx lr216entry:217 %0 = zext i16 %p to i32218 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)219 %2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)220 ret <8 x half> %2221}222 223define arm_aapcs_vfpcc <4 x float> @test_vcmulq_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {224; CHECK-LABEL: test_vcmulq_x_f32:225; CHECK: @ %bb.0: @ %entry226; CHECK-NEXT: vmsr p0, r0227; CHECK-NEXT: vpst228; CHECK-NEXT: vcmult.f32 q2, q0, q1, #0229; CHECK-NEXT: vmov q0, q2230; CHECK-NEXT: bx lr231entry:232 %0 = zext i16 %p to i32233 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)234 %2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)235 ret <4 x float> %2236}237 238define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {239; CHECK-LABEL: test_vcmulq_rot90_x_f16:240; CHECK: @ %bb.0: @ %entry241; CHECK-NEXT: vmsr p0, r0242; CHECK-NEXT: vpst243; CHECK-NEXT: vcmult.f16 q0, q0, q1, #90244; CHECK-NEXT: bx lr245entry:246 %0 = zext i16 %p to i32247 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)248 %2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)249 ret <8 x half> %2250}251 252define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {253; CHECK-LABEL: test_vcmulq_rot90_x_f32:254; CHECK: @ %bb.0: @ %entry255; CHECK-NEXT: vmsr p0, r0256; CHECK-NEXT: vpst257; CHECK-NEXT: vcmult.f32 q2, q0, q1, #90258; CHECK-NEXT: vmov q0, q2259; CHECK-NEXT: bx lr260entry:261 %0 = zext i16 %p to i32262 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)263 %2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)264 ret <4 x float> %2265}266 267define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {268; CHECK-LABEL: test_vcmulq_rot180_x_f16:269; CHECK: @ %bb.0: @ %entry270; CHECK-NEXT: vmsr p0, r0271; CHECK-NEXT: vpst272; CHECK-NEXT: vcmult.f16 q0, q0, q1, #180273; CHECK-NEXT: bx lr274entry:275 %0 = zext i16 %p to i32276 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)277 %2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 2, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)278 ret <8 x half> %2279}280 281define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {282; CHECK-LABEL: test_vcmulq_rot180_x_f32:283; CHECK: @ %bb.0: @ %entry284; CHECK-NEXT: vmsr p0, r0285; CHECK-NEXT: vpst286; CHECK-NEXT: vcmult.f32 q2, q0, q1, #180287; CHECK-NEXT: vmov q0, q2288; CHECK-NEXT: bx lr289entry:290 %0 = zext i16 %p to i32291 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)292 %2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 2, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)293 ret <4 x float> %2294}295 296define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {297; CHECK-LABEL: test_vcmulq_rot270_x_f16:298; CHECK: @ %bb.0: @ %entry299; CHECK-NEXT: vmsr p0, r0300; CHECK-NEXT: vpst301; CHECK-NEXT: vcmult.f16 q0, q0, q1, #270302; CHECK-NEXT: bx lr303entry:304 %0 = zext i16 %p to i32305 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)306 %2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 3, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)307 ret <8 x half> %2308}309 310define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {311; CHECK-LABEL: test_vcmulq_rot270_x_f32:312; CHECK: @ %bb.0: @ %entry313; CHECK-NEXT: vmsr p0, r0314; CHECK-NEXT: vpst315; CHECK-NEXT: vcmult.f32 q2, q0, q1, #270316; CHECK-NEXT: vmov q0, q2317; CHECK-NEXT: bx lr318entry:319 %0 = zext i16 %p to i32320 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)321 %2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 3, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)322 ret <4 x float> %2323}324