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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_s16(<8 x half> %inactive, <8 x i16> %a, i16 zeroext %p) {5; CHECK-LABEL: test_vcvtq_m_f16_s16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmsr p0, r08; CHECK-NEXT: vpst9; CHECK-NEXT: vcvtt.f16.s16 q0, q110; CHECK-NEXT: bx lr11entry:12 %0 = zext i16 %p to i3213 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)14 %2 = tail call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %a, i32 0, <8 x i1> %1, <8 x half> %inactive)15 ret <8 x half> %216}17 18define arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_u16(<8 x half> %inactive, <8 x i16> %a, i16 zeroext %p) {19; CHECK-LABEL: test_vcvtq_m_f16_u16:20; CHECK: @ %bb.0: @ %entry21; CHECK-NEXT: vmsr p0, r022; CHECK-NEXT: vpst23; CHECK-NEXT: vcvtt.f16.u16 q0, q124; CHECK-NEXT: bx lr25entry:26 %0 = zext i16 %p to i3227 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)28 %2 = tail call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %a, i32 1, <8 x i1> %1, <8 x half> %inactive)29 ret <8 x half> %230}31 32define arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_s32(<4 x float> %inactive, <4 x i32> %a, i16 zeroext %p) {33; CHECK-LABEL: test_vcvtq_m_f32_s32:34; CHECK: @ %bb.0: @ %entry35; CHECK-NEXT: vmsr p0, r036; CHECK-NEXT: vpst37; CHECK-NEXT: vcvtt.f32.s32 q0, q138; CHECK-NEXT: bx lr39entry:40 %0 = zext i16 %p to i3241 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)42 %2 = tail call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %a, i32 0, <4 x i1> %1, <4 x float> %inactive)43 ret <4 x float> %244}45 46define arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_u32(<4 x float> %inactive, <4 x i32> %a, i16 zeroext %p) {47; CHECK-LABEL: test_vcvtq_m_f32_u32:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: vmsr p0, r050; CHECK-NEXT: vpst51; CHECK-NEXT: vcvtt.f32.u32 q0, q152; CHECK-NEXT: bx lr53entry:54 %0 = zext i16 %p to i3255 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)56 %2 = tail call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %a, i32 1, <4 x i1> %1, <4 x float> %inactive)57 ret <4 x float> %258}59 60define arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_s16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {61; CHECK-LABEL: test_vcvtq_m_s16_f16:62; CHECK: @ %bb.0: @ %entry63; CHECK-NEXT: vmsr p0, r064; CHECK-NEXT: vpst65; CHECK-NEXT: vcvtt.s16.f16 q0, q166; CHECK-NEXT: bx lr67entry:68 %0 = zext i16 %p to i3269 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)70 %2 = tail call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %a, i32 0, <8 x i1> %1, <8 x i16> %inactive)71 ret <8 x i16> %272}73 74define arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_s32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {75; CHECK-LABEL: test_vcvtq_m_s32_f32:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vmsr p0, r078; CHECK-NEXT: vpst79; CHECK-NEXT: vcvtt.s32.f32 q0, q180; CHECK-NEXT: bx lr81entry:82 %0 = zext i16 %p to i3283 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)84 %2 = tail call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %a, i32 0, <4 x i1> %1, <4 x i32> %inactive)85 ret <4 x i32> %286}87 88define arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_u16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {89; CHECK-LABEL: test_vcvtq_m_u16_f16:90; CHECK: @ %bb.0: @ %entry91; CHECK-NEXT: vmsr p0, r092; CHECK-NEXT: vpst93; CHECK-NEXT: vcvtt.u16.f16 q0, q194; CHECK-NEXT: bx lr95entry:96 %0 = zext i16 %p to i3297 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)98 %2 = tail call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %a, i32 1, <8 x i1> %1, <8 x i16> %inactive)99 ret <8 x i16> %2100}101 102define arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_u32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {103; CHECK-LABEL: test_vcvtq_m_u32_f32:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vmsr p0, r0106; CHECK-NEXT: vpst107; CHECK-NEXT: vcvtt.u32.f32 q0, q1108; CHECK-NEXT: bx lr109entry:110 %0 = zext i16 %p to i32111 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)112 %2 = tail call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %a, i32 1, <4 x i1> %1, <4 x i32> %inactive)113 ret <4 x i32> %2114}115 116declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)117declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)118 119declare <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x half>)120declare <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x float>)121declare <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x i16>)122declare <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float>, i32, <4 x i1>, <4 x i32>)123