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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)5declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)6 7declare <8 x half> @llvm.arm.mve.vcvt.narrow(<8 x half>, <4 x float>, i32)8declare <8 x half> @llvm.arm.mve.vcvt.narrow.predicated(<8 x half>, <4 x float>, i32, <4 x i1>)9declare <4 x float> @llvm.arm.mve.vcvt.widen(<8 x half>, i32)10declare <4 x float> @llvm.arm.mve.vcvt.widen.predicated(<4 x float>, <8 x half>, i32, <4 x i1>)11 12declare <8 x half> @llvm.arm.mve.vcvt.fix.v8f16.v8i16(i32, <8 x i16>, i32)13declare <4 x float> @llvm.arm.mve.vcvt.fix.v4f32.v4i32(i32, <4 x i32>, i32)14declare <8 x i16> @llvm.arm.mve.vcvt.fix.v8i16.v8f16(i32, <8 x half>, i32)15declare <4 x i32> @llvm.arm.mve.vcvt.fix.v4i32.v4f32(i32, <4 x float>, i32)16declare <8 x half> @llvm.arm.mve.vcvt.fix.predicated.v8f16.v8i16.v8i1(i32, <8 x half>, <8 x i16>, i32, <8 x i1>)17declare <4 x float> @llvm.arm.mve.vcvt.fix.predicated.v4f32.v4i32.v4i1(i32, <4 x float>, <4 x i32>, i32, <4 x i1>)18declare <8 x i16> @llvm.arm.mve.vcvt.fix.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, i32, <8 x i1>)19declare <4 x i32> @llvm.arm.mve.vcvt.fix.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, i32, <4 x i1>)20 21define arm_aapcs_vfpcc <8 x half> @test_vcvttq_f16_f32(<8 x half> %a, <4 x float> %b) {22; CHECK-LABEL: test_vcvttq_f16_f32:23; CHECK: @ %bb.0: @ %entry24; CHECK-NEXT: vcvtt.f16.f32 q0, q125; CHECK-NEXT: bx lr26entry:27 %0 = tail call <8 x half> @llvm.arm.mve.vcvt.narrow(<8 x half> %a, <4 x float> %b, i32 1)28 ret <8 x half> %029}30 31define arm_aapcs_vfpcc <8 x half> @test_vcvtbq_f16_f32(<8 x half> %a, <4 x float> %b) {32; CHECK-LABEL: test_vcvtbq_f16_f32:33; CHECK: @ %bb.0: @ %entry34; CHECK-NEXT: vcvtb.f16.f32 q0, q135; CHECK-NEXT: bx lr36entry:37 %0 = tail call <8 x half> @llvm.arm.mve.vcvt.narrow(<8 x half> %a, <4 x float> %b, i32 0)38 ret <8 x half> %039}40 41define arm_aapcs_vfpcc <8 x half> @test_vcvttq_m_f16_f32(<8 x half> %a, <4 x float> %b, i16 zeroext %p) {42; CHECK-LABEL: test_vcvttq_m_f16_f32:43; CHECK: @ %bb.0: @ %entry44; CHECK-NEXT: vmsr p0, r045; CHECK-NEXT: vpst46; CHECK-NEXT: vcvttt.f16.f32 q0, q147; CHECK-NEXT: bx lr48entry:49 %0 = zext i16 %p to i3250 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)51 %2 = tail call <8 x half> @llvm.arm.mve.vcvt.narrow.predicated(<8 x half> %a, <4 x float> %b, i32 1, <4 x i1> %1)52 ret <8 x half> %253}54 55define arm_aapcs_vfpcc <8 x half> @test_vcvtbq_m_f16_f32(<8 x half> %a, <4 x float> %b, i16 zeroext %p) {56; CHECK-LABEL: test_vcvtbq_m_f16_f32:57; CHECK: @ %bb.0: @ %entry58; CHECK-NEXT: vmsr p0, r059; CHECK-NEXT: vpst60; CHECK-NEXT: vcvtbt.f16.f32 q0, q161; CHECK-NEXT: bx lr62entry:63 %0 = zext i16 %p to i3264 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)65 %2 = tail call <8 x half> @llvm.arm.mve.vcvt.narrow.predicated(<8 x half> %a, <4 x float> %b, i32 0, <4 x i1> %1)66 ret <8 x half> %267}68 69define arm_aapcs_vfpcc <8 x half> @test_vcvtq_n_f16_s16(<8 x i16> %a) {70; CHECK-LABEL: test_vcvtq_n_f16_s16:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: vcvt.f16.s16 q0, q0, #173; CHECK-NEXT: bx lr74entry:75 %0 = call <8 x half> @llvm.arm.mve.vcvt.fix.v8f16.v8i16(i32 0, <8 x i16> %a, i32 1)76 ret <8 x half> %077}78 79define arm_aapcs_vfpcc <8 x half> @test_vcvtq_n_f16_u16(<8 x i16> %a) {80; CHECK-LABEL: test_vcvtq_n_f16_u16:81; CHECK: @ %bb.0: @ %entry82; CHECK-NEXT: vcvt.f16.u16 q0, q0, #283; CHECK-NEXT: bx lr84entry:85 %0 = call <8 x half> @llvm.arm.mve.vcvt.fix.v8f16.v8i16(i32 1, <8 x i16> %a, i32 2)86 ret <8 x half> %087}88 89define arm_aapcs_vfpcc <4 x float> @test_vcvtq_n_f32_s32(<4 x i32> %a) {90; CHECK-LABEL: test_vcvtq_n_f32_s32:91; CHECK: @ %bb.0: @ %entry92; CHECK-NEXT: vcvt.f32.s32 q0, q0, #393; CHECK-NEXT: bx lr94entry:95 %0 = call <4 x float> @llvm.arm.mve.vcvt.fix.v4f32.v4i32(i32 0, <4 x i32> %a, i32 3)96 ret <4 x float> %097}98 99define arm_aapcs_vfpcc <4 x float> @test_vcvtq_n_f32_u32(<4 x i32> %a) {100; CHECK-LABEL: test_vcvtq_n_f32_u32:101; CHECK: @ %bb.0: @ %entry102; CHECK-NEXT: vcvt.f32.u32 q0, q0, #32103; CHECK-NEXT: bx lr104entry:105 %0 = call <4 x float> @llvm.arm.mve.vcvt.fix.v4f32.v4i32(i32 1, <4 x i32> %a, i32 32)106 ret <4 x float> %0107}108 109define arm_aapcs_vfpcc <8 x i16> @test_vcvtq_n_s16_f16(<8 x half> %a) {110; CHECK-LABEL: test_vcvtq_n_s16_f16:111; CHECK: @ %bb.0: @ %entry112; CHECK-NEXT: vcvt.s16.f16 q0, q0, #1113; CHECK-NEXT: bx lr114entry:115 %0 = call <8 x i16> @llvm.arm.mve.vcvt.fix.v8i16.v8f16(i32 0, <8 x half> %a, i32 1)116 ret <8 x i16> %0117}118 119define arm_aapcs_vfpcc <8 x i16> @test_vcvtq_n_u16_f16(<8 x half> %a) {120; CHECK-LABEL: test_vcvtq_n_u16_f16:121; CHECK: @ %bb.0: @ %entry122; CHECK-NEXT: vcvt.u16.f16 q0, q0, #2123; CHECK-NEXT: bx lr124entry:125 %0 = call <8 x i16> @llvm.arm.mve.vcvt.fix.v8i16.v8f16(i32 1, <8 x half> %a, i32 2)126 ret <8 x i16> %0127}128 129define arm_aapcs_vfpcc <4 x i32> @test_vcvtq_n_s32_f32(<4 x float> %a) {130; CHECK-LABEL: test_vcvtq_n_s32_f32:131; CHECK: @ %bb.0: @ %entry132; CHECK-NEXT: vcvt.s32.f32 q0, q0, #3133; CHECK-NEXT: bx lr134entry:135 %0 = call <4 x i32> @llvm.arm.mve.vcvt.fix.v4i32.v4f32(i32 0, <4 x float> %a, i32 3)136 ret <4 x i32> %0137}138 139define arm_aapcs_vfpcc <4 x i32> @test_vcvtq_n_u32_f32(<4 x float> %a) {140; CHECK-LABEL: test_vcvtq_n_u32_f32:141; CHECK: @ %bb.0: @ %entry142; CHECK-NEXT: vcvt.u32.f32 q0, q0, #32143; CHECK-NEXT: bx lr144entry:145 %0 = call <4 x i32> @llvm.arm.mve.vcvt.fix.v4i32.v4f32(i32 1, <4 x float> %a, i32 32)146 ret <4 x i32> %0147}148 149define arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_n_f16_s16(<8 x half> %inactive, <8 x i16> %a, i16 zeroext %p) {150; CHECK-LABEL: test_vcvtq_m_n_f16_s16:151; CHECK: @ %bb.0: @ %entry152; CHECK-NEXT: vmsr p0, r0153; CHECK-NEXT: vpst154; CHECK-NEXT: vcvtt.f16.s16 q0, q1, #1155; CHECK-NEXT: bx lr156entry:157 %0 = zext i16 %p to i32158 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)159 %2 = call <8 x half> @llvm.arm.mve.vcvt.fix.predicated.v8f16.v8i16.v8i1(i32 0, <8 x half> %inactive, <8 x i16> %a, i32 1, <8 x i1> %1)160 ret <8 x half> %2161}162 163define arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_n_f16_u16(<8 x half> %inactive, <8 x i16> %a, i16 zeroext %p) {164; CHECK-LABEL: test_vcvtq_m_n_f16_u16:165; CHECK: @ %bb.0: @ %entry166; CHECK-NEXT: vmsr p0, r0167; CHECK-NEXT: vpst168; CHECK-NEXT: vcvtt.f16.u16 q0, q1, #2169; CHECK-NEXT: bx lr170entry:171 %0 = zext i16 %p to i32172 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)173 %2 = call <8 x half> @llvm.arm.mve.vcvt.fix.predicated.v8f16.v8i16.v8i1(i32 1, <8 x half> %inactive, <8 x i16> %a, i32 2, <8 x i1> %1)174 ret <8 x half> %2175}176 177define arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_n_f32_s32(<4 x float> %inactive, <4 x i32> %a, i16 zeroext %p) {178; CHECK-LABEL: test_vcvtq_m_n_f32_s32:179; CHECK: @ %bb.0: @ %entry180; CHECK-NEXT: vmsr p0, r0181; CHECK-NEXT: vpst182; CHECK-NEXT: vcvtt.f32.s32 q0, q1, #3183; CHECK-NEXT: bx lr184entry:185 %0 = zext i16 %p to i32186 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)187 %2 = call <4 x float> @llvm.arm.mve.vcvt.fix.predicated.v4f32.v4i32.v4i1(i32 0, <4 x float> %inactive, <4 x i32> %a, i32 3, <4 x i1> %1)188 ret <4 x float> %2189}190 191define arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_n_f32_u32(<4 x float> %inactive, <4 x i32> %a, i16 zeroext %p) {192; CHECK-LABEL: test_vcvtq_m_n_f32_u32:193; CHECK: @ %bb.0: @ %entry194; CHECK-NEXT: vmsr p0, r0195; CHECK-NEXT: vpst196; CHECK-NEXT: vcvtt.f32.u32 q0, q1, #32197; CHECK-NEXT: bx lr198entry:199 %0 = zext i16 %p to i32200 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)201 %2 = call <4 x float> @llvm.arm.mve.vcvt.fix.predicated.v4f32.v4i32.v4i1(i32 1, <4 x float> %inactive, <4 x i32> %a, i32 32, <4 x i1> %1)202 ret <4 x float> %2203}204 205define arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_n_s16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {206; CHECK-LABEL: test_vcvtq_m_n_s16_f16:207; CHECK: @ %bb.0: @ %entry208; CHECK-NEXT: vmsr p0, r0209; CHECK-NEXT: vpst210; CHECK-NEXT: vcvtt.s16.f16 q0, q1, #1211; CHECK-NEXT: bx lr212entry:213 %0 = zext i16 %p to i32214 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)215 %2 = call <8 x i16> @llvm.arm.mve.vcvt.fix.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %inactive, <8 x half> %a, i32 1, <8 x i1> %1)216 ret <8 x i16> %2217}218 219define arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_n_u16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {220; CHECK-LABEL: test_vcvtq_m_n_u16_f16:221; CHECK: @ %bb.0: @ %entry222; CHECK-NEXT: vmsr p0, r0223; CHECK-NEXT: vpst224; CHECK-NEXT: vcvtt.u16.f16 q0, q1, #2225; CHECK-NEXT: bx lr226entry:227 %0 = zext i16 %p to i32228 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)229 %2 = call <8 x i16> @llvm.arm.mve.vcvt.fix.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> %inactive, <8 x half> %a, i32 2, <8 x i1> %1)230 ret <8 x i16> %2231}232 233define arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_n_s32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {234; CHECK-LABEL: test_vcvtq_m_n_s32_f32:235; CHECK: @ %bb.0: @ %entry236; CHECK-NEXT: vmsr p0, r0237; CHECK-NEXT: vpst238; CHECK-NEXT: vcvtt.s32.f32 q0, q1, #3239; CHECK-NEXT: bx lr240entry:241 %0 = zext i16 %p to i32242 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)243 %2 = call <4 x i32> @llvm.arm.mve.vcvt.fix.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %inactive, <4 x float> %a, i32 3, <4 x i1> %1)244 ret <4 x i32> %2245}246 247define arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_n_u32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {248; CHECK-LABEL: test_vcvtq_m_n_u32_f32:249; CHECK: @ %bb.0: @ %entry250; CHECK-NEXT: vmsr p0, r0251; CHECK-NEXT: vpst252; CHECK-NEXT: vcvtt.u32.f32 q0, q1, #32253; CHECK-NEXT: bx lr254entry:255 %0 = zext i16 %p to i32256 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)257 %2 = call <4 x i32> @llvm.arm.mve.vcvt.fix.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> %inactive, <4 x float> %a, i32 32, <4 x i1> %1)258 ret <4 x i32> %2259}260 261define arm_aapcs_vfpcc <8 x half> @test_vcvtq_x_n_f16_s16(<8 x i16> %a, i16 zeroext %p) {262; CHECK-LABEL: test_vcvtq_x_n_f16_s16:263; CHECK: @ %bb.0: @ %entry264; CHECK-NEXT: vmsr p0, r0265; CHECK-NEXT: vpst266; CHECK-NEXT: vcvtt.f16.s16 q0, q0, #1267; CHECK-NEXT: bx lr268entry:269 %0 = zext i16 %p to i32270 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)271 %2 = call <8 x half> @llvm.arm.mve.vcvt.fix.predicated.v8f16.v8i16.v8i1(i32 0, <8 x half> undef, <8 x i16> %a, i32 1, <8 x i1> %1)272 ret <8 x half> %2273}274 275define arm_aapcs_vfpcc <8 x half> @test_vcvtq_x_n_f16_u16(<8 x i16> %a, i16 zeroext %p) {276; CHECK-LABEL: test_vcvtq_x_n_f16_u16:277; CHECK: @ %bb.0: @ %entry278; CHECK-NEXT: vmsr p0, r0279; CHECK-NEXT: vpst280; CHECK-NEXT: vcvtt.f16.u16 q0, q0, #2281; CHECK-NEXT: bx lr282entry:283 %0 = zext i16 %p to i32284 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)285 %2 = call <8 x half> @llvm.arm.mve.vcvt.fix.predicated.v8f16.v8i16.v8i1(i32 1, <8 x half> undef, <8 x i16> %a, i32 2, <8 x i1> %1)286 ret <8 x half> %2287}288 289define arm_aapcs_vfpcc <4 x float> @test_vcvtq_x_n_f32_s32(<4 x i32> %a, i16 zeroext %p) {290; CHECK-LABEL: test_vcvtq_x_n_f32_s32:291; CHECK: @ %bb.0: @ %entry292; CHECK-NEXT: vmsr p0, r0293; CHECK-NEXT: vpst294; CHECK-NEXT: vcvtt.f32.s32 q0, q0, #3295; CHECK-NEXT: bx lr296entry:297 %0 = zext i16 %p to i32298 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)299 %2 = call <4 x float> @llvm.arm.mve.vcvt.fix.predicated.v4f32.v4i32.v4i1(i32 0, <4 x float> undef, <4 x i32> %a, i32 3, <4 x i1> %1)300 ret <4 x float> %2301}302 303define arm_aapcs_vfpcc <4 x float> @test_vcvtq_x_n_f32_u32(<4 x i32> %a, i16 zeroext %p) {304; CHECK-LABEL: test_vcvtq_x_n_f32_u32:305; CHECK: @ %bb.0: @ %entry306; CHECK-NEXT: vmsr p0, r0307; CHECK-NEXT: vpst308; CHECK-NEXT: vcvtt.f32.u32 q0, q0, #32309; CHECK-NEXT: bx lr310entry:311 %0 = zext i16 %p to i32312 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)313 %2 = call <4 x float> @llvm.arm.mve.vcvt.fix.predicated.v4f32.v4i32.v4i1(i32 1, <4 x float> undef, <4 x i32> %a, i32 32, <4 x i1> %1)314 ret <4 x float> %2315}316 317define arm_aapcs_vfpcc <8 x i16> @test_vcvtq_x_n_s16_f16(<8 x half> %a, i16 zeroext %p) {318; CHECK-LABEL: test_vcvtq_x_n_s16_f16:319; CHECK: @ %bb.0: @ %entry320; CHECK-NEXT: vmsr p0, r0321; CHECK-NEXT: vpst322; CHECK-NEXT: vcvtt.s16.f16 q0, q0, #1323; CHECK-NEXT: bx lr324entry:325 %0 = zext i16 %p to i32326 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)327 %2 = call <8 x i16> @llvm.arm.mve.vcvt.fix.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> %a, i32 1, <8 x i1> %1)328 ret <8 x i16> %2329}330 331define arm_aapcs_vfpcc <8 x i16> @test_vcvtq_x_n_u16_f16(<8 x half> %a, i16 zeroext %p) {332; CHECK-LABEL: test_vcvtq_x_n_u16_f16:333; CHECK: @ %bb.0: @ %entry334; CHECK-NEXT: vmsr p0, r0335; CHECK-NEXT: vpst336; CHECK-NEXT: vcvtt.u16.f16 q0, q0, #2337; CHECK-NEXT: bx lr338entry:339 %0 = zext i16 %p to i32340 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)341 %2 = call <8 x i16> @llvm.arm.mve.vcvt.fix.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> %a, i32 2, <8 x i1> %1)342 ret <8 x i16> %2343}344 345define arm_aapcs_vfpcc <4 x i32> @test_vcvtq_x_n_s32_f32(<4 x float> %a, i16 zeroext %p) {346; CHECK-LABEL: test_vcvtq_x_n_s32_f32:347; CHECK: @ %bb.0: @ %entry348; CHECK-NEXT: vmsr p0, r0349; CHECK-NEXT: vpst350; CHECK-NEXT: vcvtt.s32.f32 q0, q0, #3351; CHECK-NEXT: bx lr352entry:353 %0 = zext i16 %p to i32354 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)355 %2 = call <4 x i32> @llvm.arm.mve.vcvt.fix.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> %a, i32 3, <4 x i1> %1)356 ret <4 x i32> %2357}358 359define arm_aapcs_vfpcc <4 x i32> @test_vcvtq_x_n_u32_f32(<4 x float> %a, i16 zeroext %p) {360; CHECK-LABEL: test_vcvtq_x_n_u32_f32:361; CHECK: @ %bb.0: @ %entry362; CHECK-NEXT: vmsr p0, r0363; CHECK-NEXT: vpst364; CHECK-NEXT: vcvtt.u32.f32 q0, q0, #32365; CHECK-NEXT: bx lr366entry:367 %0 = zext i16 %p to i32368 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)369 %2 = call <4 x i32> @llvm.arm.mve.vcvt.fix.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> %a, i32 32, <4 x i1> %1)370 ret <4 x i32> %2371}372 373define arm_aapcs_vfpcc <4 x float> @test_vcvtbq_f32_f16(<8 x half> %a) {374; CHECK-LABEL: test_vcvtbq_f32_f16:375; CHECK: @ %bb.0: @ %entry376; CHECK-NEXT: vcvtb.f32.f16 q0, q0377; CHECK-NEXT: bx lr378entry:379 %0 = tail call <4 x float> @llvm.arm.mve.vcvt.widen(<8 x half> %a, i32 0)380 ret <4 x float> %0381}382 383define arm_aapcs_vfpcc <4 x float> @test_vcvttq_f32_f16(<8 x half> %a) {384; CHECK-LABEL: test_vcvttq_f32_f16:385; CHECK: @ %bb.0: @ %entry386; CHECK-NEXT: vcvtt.f32.f16 q0, q0387; CHECK-NEXT: bx lr388entry:389 %0 = tail call <4 x float> @llvm.arm.mve.vcvt.widen(<8 x half> %a, i32 1)390 ret <4 x float> %0391}392 393define arm_aapcs_vfpcc <4 x float> @test_vcvtbq_m_f32_f16(<4 x float> %inactive, <8 x half> %a, i16 zeroext %p) {394; CHECK-LABEL: test_vcvtbq_m_f32_f16:395; CHECK: @ %bb.0: @ %entry396; CHECK-NEXT: vmsr p0, r0397; CHECK-NEXT: vpst398; CHECK-NEXT: vcvtbt.f32.f16 q0, q1399; CHECK-NEXT: bx lr400entry:401 %0 = zext i16 %p to i32402 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)403 %2 = tail call <4 x float> @llvm.arm.mve.vcvt.widen.predicated(<4 x float> %inactive, <8 x half> %a, i32 0, <4 x i1> %1)404 ret <4 x float> %2405}406 407define arm_aapcs_vfpcc <4 x float> @test_vcvttq_m_f32_f16(<4 x float> %inactive, <8 x half> %a, i16 zeroext %p) {408; CHECK-LABEL: test_vcvttq_m_f32_f16:409; CHECK: @ %bb.0: @ %entry410; CHECK-NEXT: vmsr p0, r0411; CHECK-NEXT: vpst412; CHECK-NEXT: vcvttt.f32.f16 q0, q1413; CHECK-NEXT: bx lr414entry:415 %0 = zext i16 %p to i32416 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)417 %2 = tail call <4 x float> @llvm.arm.mve.vcvt.widen.predicated(<4 x float> %inactive, <8 x half> %a, i32 1, <4 x i1> %1)418 ret <4 x float> %2419}420