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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_s16_f16(<8 x half> %a) {5; CHECK-LABEL: test_vcvtaq_s16_f16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vcvta.s16.f16 q0, q08; CHECK-NEXT: bx lr9entry:10 %0 = tail call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> %a)11 ret <8 x i16> %012}13 14define arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_s32_f32(<4 x float> %a) {15; CHECK-LABEL: test_vcvtaq_s32_f32:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vcvta.s32.f32 q0, q018; CHECK-NEXT: bx lr19entry:20 %0 = tail call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> %a)21 ret <4 x i32> %022}23 24define arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_u16_f16(<8 x half> %a) {25; CHECK-LABEL: test_vcvtaq_u16_f16:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vcvta.u16.f16 q0, q028; CHECK-NEXT: bx lr29entry:30 %0 = tail call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> %a)31 ret <8 x i16> %032}33 34define arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_u32_f32(<4 x float> %a) {35; CHECK-LABEL: test_vcvtaq_u32_f32:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vcvta.u32.f32 q0, q038; CHECK-NEXT: bx lr39entry:40 %0 = tail call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> %a)41 ret <4 x i32> %042}43 44define arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_s16_f16(<8 x half> %a) {45; CHECK-LABEL: test_vcvtmq_s16_f16:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vcvtm.s16.f16 q0, q048; CHECK-NEXT: bx lr49entry:50 %0 = tail call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> %a)51 ret <8 x i16> %052}53 54define arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_s32_f32(<4 x float> %a) {55; CHECK-LABEL: test_vcvtmq_s32_f32:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vcvtm.s32.f32 q0, q058; CHECK-NEXT: bx lr59entry:60 %0 = tail call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> %a)61 ret <4 x i32> %062}63 64define arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_u16_f16(<8 x half> %a) {65; CHECK-LABEL: test_vcvtmq_u16_f16:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vcvtm.u16.f16 q0, q068; CHECK-NEXT: bx lr69entry:70 %0 = tail call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> %a)71 ret <8 x i16> %072}73 74define arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_u32_f32(<4 x float> %a) {75; CHECK-LABEL: test_vcvtmq_u32_f32:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vcvtm.u32.f32 q0, q078; CHECK-NEXT: bx lr79entry:80 %0 = tail call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> %a)81 ret <4 x i32> %082}83 84define arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_s16_f16(<8 x half> %a) {85; CHECK-LABEL: test_vcvtnq_s16_f16:86; CHECK: @ %bb.0: @ %entry87; CHECK-NEXT: vcvtn.s16.f16 q0, q088; CHECK-NEXT: bx lr89entry:90 %0 = tail call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> %a)91 ret <8 x i16> %092}93 94define arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_s32_f32(<4 x float> %a) {95; CHECK-LABEL: test_vcvtnq_s32_f32:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: vcvtn.s32.f32 q0, q098; CHECK-NEXT: bx lr99entry:100 %0 = tail call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> %a)101 ret <4 x i32> %0102}103 104define arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_u16_f16(<8 x half> %a) {105; CHECK-LABEL: test_vcvtnq_u16_f16:106; CHECK: @ %bb.0: @ %entry107; CHECK-NEXT: vcvtn.u16.f16 q0, q0108; CHECK-NEXT: bx lr109entry:110 %0 = tail call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> %a)111 ret <8 x i16> %0112}113 114define arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_u32_f32(<4 x float> %a) {115; CHECK-LABEL: test_vcvtnq_u32_f32:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: vcvtn.u32.f32 q0, q0118; CHECK-NEXT: bx lr119entry:120 %0 = tail call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> %a)121 ret <4 x i32> %0122}123 124define arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_s16_f16(<8 x half> %a) {125; CHECK-LABEL: test_vcvtpq_s16_f16:126; CHECK: @ %bb.0: @ %entry127; CHECK-NEXT: vcvtp.s16.f16 q0, q0128; CHECK-NEXT: bx lr129entry:130 %0 = tail call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> %a)131 ret <8 x i16> %0132}133 134define arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_s32_f32(<4 x float> %a) {135; CHECK-LABEL: test_vcvtpq_s32_f32:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vcvtp.s32.f32 q0, q0138; CHECK-NEXT: bx lr139entry:140 %0 = tail call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> %a)141 ret <4 x i32> %0142}143 144define arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_u16_f16(<8 x half> %a) {145; CHECK-LABEL: test_vcvtpq_u16_f16:146; CHECK: @ %bb.0: @ %entry147; CHECK-NEXT: vcvtp.u16.f16 q0, q0148; CHECK-NEXT: bx lr149entry:150 %0 = tail call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> %a)151 ret <8 x i16> %0152}153 154define arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_u32_f32(<4 x float> %a) {155; CHECK-LABEL: test_vcvtpq_u32_f32:156; CHECK: @ %bb.0: @ %entry157; CHECK-NEXT: vcvtp.u32.f32 q0, q0158; CHECK-NEXT: bx lr159entry:160 %0 = tail call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> %a)161 ret <4 x i32> %0162}163 164define arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_s16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {165; CHECK-LABEL: test_vcvtaq_m_s16_f16:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: vmsr p0, r0168; CHECK-NEXT: vpst169; CHECK-NEXT: vcvtat.s16.f16 q0, q1170; CHECK-NEXT: bx lr171entry:172 %0 = zext i16 %p to i32173 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)174 %2 = tail call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %inactive, <8 x half> %a, <8 x i1> %1)175 ret <8 x i16> %2176}177 178define arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_m_s32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {179; CHECK-LABEL: test_vcvtaq_m_s32_f32:180; CHECK: @ %bb.0: @ %entry181; CHECK-NEXT: vmsr p0, r0182; CHECK-NEXT: vpst183; CHECK-NEXT: vcvtat.s32.f32 q0, q1184; CHECK-NEXT: bx lr185entry:186 %0 = zext i16 %p to i32187 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)188 %2 = tail call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %inactive, <4 x float> %a, <4 x i1> %1)189 ret <4 x i32> %2190}191 192define arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_u16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {193; CHECK-LABEL: test_vcvtaq_m_u16_f16:194; CHECK: @ %bb.0: @ %entry195; CHECK-NEXT: vmsr p0, r0196; CHECK-NEXT: vpst197; CHECK-NEXT: vcvtat.u16.f16 q0, q1198; CHECK-NEXT: bx lr199entry:200 %0 = zext i16 %p to i32201 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)202 %2 = tail call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> %inactive, <8 x half> %a, <8 x i1> %1)203 ret <8 x i16> %2204}205 206define arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_m_u32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {207; CHECK-LABEL: test_vcvtaq_m_u32_f32:208; CHECK: @ %bb.0: @ %entry209; CHECK-NEXT: vmsr p0, r0210; CHECK-NEXT: vpst211; CHECK-NEXT: vcvtat.u32.f32 q0, q1212; CHECK-NEXT: bx lr213entry:214 %0 = zext i16 %p to i32215 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)216 %2 = tail call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> %inactive, <4 x float> %a, <4 x i1> %1)217 ret <4 x i32> %2218}219 220define arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_m_s16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {221; CHECK-LABEL: test_vcvtmq_m_s16_f16:222; CHECK: @ %bb.0: @ %entry223; CHECK-NEXT: vmsr p0, r0224; CHECK-NEXT: vpst225; CHECK-NEXT: vcvtmt.s16.f16 q0, q1226; CHECK-NEXT: bx lr227entry:228 %0 = zext i16 %p to i32229 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)230 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %inactive, <8 x half> %a, <8 x i1> %1)231 ret <8 x i16> %2232}233 234define arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_m_s32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {235; CHECK-LABEL: test_vcvtmq_m_s32_f32:236; CHECK: @ %bb.0: @ %entry237; CHECK-NEXT: vmsr p0, r0238; CHECK-NEXT: vpst239; CHECK-NEXT: vcvtmt.s32.f32 q0, q1240; CHECK-NEXT: bx lr241entry:242 %0 = zext i16 %p to i32243 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)244 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %inactive, <4 x float> %a, <4 x i1> %1)245 ret <4 x i32> %2246}247 248define arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_m_u16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {249; CHECK-LABEL: test_vcvtmq_m_u16_f16:250; CHECK: @ %bb.0: @ %entry251; CHECK-NEXT: vmsr p0, r0252; CHECK-NEXT: vpst253; CHECK-NEXT: vcvtmt.u16.f16 q0, q1254; CHECK-NEXT: bx lr255entry:256 %0 = zext i16 %p to i32257 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)258 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> %inactive, <8 x half> %a, <8 x i1> %1)259 ret <8 x i16> %2260}261 262define arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_m_u32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {263; CHECK-LABEL: test_vcvtmq_m_u32_f32:264; CHECK: @ %bb.0: @ %entry265; CHECK-NEXT: vmsr p0, r0266; CHECK-NEXT: vpst267; CHECK-NEXT: vcvtmt.u32.f32 q0, q1268; CHECK-NEXT: bx lr269entry:270 %0 = zext i16 %p to i32271 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)272 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> %inactive, <4 x float> %a, <4 x i1> %1)273 ret <4 x i32> %2274}275 276define arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_m_s16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {277; CHECK-LABEL: test_vcvtnq_m_s16_f16:278; CHECK: @ %bb.0: @ %entry279; CHECK-NEXT: vmsr p0, r0280; CHECK-NEXT: vpst281; CHECK-NEXT: vcvtnt.s16.f16 q0, q1282; CHECK-NEXT: bx lr283entry:284 %0 = zext i16 %p to i32285 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)286 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %inactive, <8 x half> %a, <8 x i1> %1)287 ret <8 x i16> %2288}289 290define arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_m_s32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {291; CHECK-LABEL: test_vcvtnq_m_s32_f32:292; CHECK: @ %bb.0: @ %entry293; CHECK-NEXT: vmsr p0, r0294; CHECK-NEXT: vpst295; CHECK-NEXT: vcvtnt.s32.f32 q0, q1296; CHECK-NEXT: bx lr297entry:298 %0 = zext i16 %p to i32299 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)300 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %inactive, <4 x float> %a, <4 x i1> %1)301 ret <4 x i32> %2302}303 304define arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_m_u16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {305; CHECK-LABEL: test_vcvtnq_m_u16_f16:306; CHECK: @ %bb.0: @ %entry307; CHECK-NEXT: vmsr p0, r0308; CHECK-NEXT: vpst309; CHECK-NEXT: vcvtnt.u16.f16 q0, q1310; CHECK-NEXT: bx lr311entry:312 %0 = zext i16 %p to i32313 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)314 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> %inactive, <8 x half> %a, <8 x i1> %1)315 ret <8 x i16> %2316}317 318define arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_m_u32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {319; CHECK-LABEL: test_vcvtnq_m_u32_f32:320; CHECK: @ %bb.0: @ %entry321; CHECK-NEXT: vmsr p0, r0322; CHECK-NEXT: vpst323; CHECK-NEXT: vcvtnt.u32.f32 q0, q1324; CHECK-NEXT: bx lr325entry:326 %0 = zext i16 %p to i32327 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)328 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> %inactive, <4 x float> %a, <4 x i1> %1)329 ret <4 x i32> %2330}331 332define arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_m_s16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {333; CHECK-LABEL: test_vcvtpq_m_s16_f16:334; CHECK: @ %bb.0: @ %entry335; CHECK-NEXT: vmsr p0, r0336; CHECK-NEXT: vpst337; CHECK-NEXT: vcvtpt.s16.f16 q0, q1338; CHECK-NEXT: bx lr339entry:340 %0 = zext i16 %p to i32341 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)342 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %inactive, <8 x half> %a, <8 x i1> %1)343 ret <8 x i16> %2344}345 346define arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_m_s32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {347; CHECK-LABEL: test_vcvtpq_m_s32_f32:348; CHECK: @ %bb.0: @ %entry349; CHECK-NEXT: vmsr p0, r0350; CHECK-NEXT: vpst351; CHECK-NEXT: vcvtpt.s32.f32 q0, q1352; CHECK-NEXT: bx lr353entry:354 %0 = zext i16 %p to i32355 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)356 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %inactive, <4 x float> %a, <4 x i1> %1)357 ret <4 x i32> %2358}359 360define arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_m_u16_f16(<8 x i16> %inactive, <8 x half> %a, i16 zeroext %p) {361; CHECK-LABEL: test_vcvtpq_m_u16_f16:362; CHECK: @ %bb.0: @ %entry363; CHECK-NEXT: vmsr p0, r0364; CHECK-NEXT: vpst365; CHECK-NEXT: vcvtpt.u16.f16 q0, q1366; CHECK-NEXT: bx lr367entry:368 %0 = zext i16 %p to i32369 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)370 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> %inactive, <8 x half> %a, <8 x i1> %1)371 ret <8 x i16> %2372}373 374define arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_m_u32_f32(<4 x i32> %inactive, <4 x float> %a, i16 zeroext %p) {375; CHECK-LABEL: test_vcvtpq_m_u32_f32:376; CHECK: @ %bb.0: @ %entry377; CHECK-NEXT: vmsr p0, r0378; CHECK-NEXT: vpst379; CHECK-NEXT: vcvtpt.u32.f32 q0, q1380; CHECK-NEXT: bx lr381entry:382 %0 = zext i16 %p to i32383 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)384 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> %inactive, <4 x float> %a, <4 x i1> %1)385 ret <4 x i32> %2386}387 388define arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_x_s16_f16(<8 x half> %a, i16 zeroext %p) {389; CHECK-LABEL: test_vcvtaq_x_s16_f16:390; CHECK: @ %bb.0: @ %entry391; CHECK-NEXT: vmsr p0, r0392; CHECK-NEXT: vpst393; CHECK-NEXT: vcvtat.s16.f16 q0, q0394; CHECK-NEXT: bx lr395entry:396 %0 = zext i16 %p to i32397 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)398 %2 = tail call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> %a, <8 x i1> %1)399 ret <8 x i16> %2400}401 402define arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_x_s32_f32(<4 x float> %a, i16 zeroext %p) {403; CHECK-LABEL: test_vcvtaq_x_s32_f32:404; CHECK: @ %bb.0: @ %entry405; CHECK-NEXT: vmsr p0, r0406; CHECK-NEXT: vpst407; CHECK-NEXT: vcvtat.s32.f32 q0, q0408; CHECK-NEXT: bx lr409entry:410 %0 = zext i16 %p to i32411 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)412 %2 = tail call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> %a, <4 x i1> %1)413 ret <4 x i32> %2414}415 416define arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_x_u16_f16(<8 x half> %a, i16 zeroext %p) {417; CHECK-LABEL: test_vcvtaq_x_u16_f16:418; CHECK: @ %bb.0: @ %entry419; CHECK-NEXT: vmsr p0, r0420; CHECK-NEXT: vpst421; CHECK-NEXT: vcvtat.u16.f16 q0, q0422; CHECK-NEXT: bx lr423entry:424 %0 = zext i16 %p to i32425 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)426 %2 = tail call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> %a, <8 x i1> %1)427 ret <8 x i16> %2428}429 430define arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_x_u32_f32(<4 x float> %a, i16 zeroext %p) {431; CHECK-LABEL: test_vcvtaq_x_u32_f32:432; CHECK: @ %bb.0: @ %entry433; CHECK-NEXT: vmsr p0, r0434; CHECK-NEXT: vpst435; CHECK-NEXT: vcvtat.u32.f32 q0, q0436; CHECK-NEXT: bx lr437entry:438 %0 = zext i16 %p to i32439 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)440 %2 = tail call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> %a, <4 x i1> %1)441 ret <4 x i32> %2442}443 444define arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_x_s16_f16(<8 x half> %a, i16 zeroext %p) {445; CHECK-LABEL: test_vcvtmq_x_s16_f16:446; CHECK: @ %bb.0: @ %entry447; CHECK-NEXT: vmsr p0, r0448; CHECK-NEXT: vpst449; CHECK-NEXT: vcvtmt.s16.f16 q0, q0450; CHECK-NEXT: bx lr451entry:452 %0 = zext i16 %p to i32453 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)454 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> %a, <8 x i1> %1)455 ret <8 x i16> %2456}457 458define arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_x_s32_f32(<4 x float> %a, i16 zeroext %p) {459; CHECK-LABEL: test_vcvtmq_x_s32_f32:460; CHECK: @ %bb.0: @ %entry461; CHECK-NEXT: vmsr p0, r0462; CHECK-NEXT: vpst463; CHECK-NEXT: vcvtmt.s32.f32 q0, q0464; CHECK-NEXT: bx lr465entry:466 %0 = zext i16 %p to i32467 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)468 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> %a, <4 x i1> %1)469 ret <4 x i32> %2470}471 472define arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_x_u16_f16(<8 x half> %a, i16 zeroext %p) {473; CHECK-LABEL: test_vcvtmq_x_u16_f16:474; CHECK: @ %bb.0: @ %entry475; CHECK-NEXT: vmsr p0, r0476; CHECK-NEXT: vpst477; CHECK-NEXT: vcvtmt.u16.f16 q0, q0478; CHECK-NEXT: bx lr479entry:480 %0 = zext i16 %p to i32481 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)482 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> %a, <8 x i1> %1)483 ret <8 x i16> %2484}485 486define arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_x_u32_f32(<4 x float> %a, i16 zeroext %p) {487; CHECK-LABEL: test_vcvtmq_x_u32_f32:488; CHECK: @ %bb.0: @ %entry489; CHECK-NEXT: vmsr p0, r0490; CHECK-NEXT: vpst491; CHECK-NEXT: vcvtmt.u32.f32 q0, q0492; CHECK-NEXT: bx lr493entry:494 %0 = zext i16 %p to i32495 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)496 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> %a, <4 x i1> %1)497 ret <4 x i32> %2498}499 500define arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_x_s16_f16(<8 x half> %a, i16 zeroext %p) {501; CHECK-LABEL: test_vcvtnq_x_s16_f16:502; CHECK: @ %bb.0: @ %entry503; CHECK-NEXT: vmsr p0, r0504; CHECK-NEXT: vpst505; CHECK-NEXT: vcvtnt.s16.f16 q0, q0506; CHECK-NEXT: bx lr507entry:508 %0 = zext i16 %p to i32509 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)510 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> %a, <8 x i1> %1)511 ret <8 x i16> %2512}513 514define arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_x_s32_f32(<4 x float> %a, i16 zeroext %p) {515; CHECK-LABEL: test_vcvtnq_x_s32_f32:516; CHECK: @ %bb.0: @ %entry517; CHECK-NEXT: vmsr p0, r0518; CHECK-NEXT: vpst519; CHECK-NEXT: vcvtnt.s32.f32 q0, q0520; CHECK-NEXT: bx lr521entry:522 %0 = zext i16 %p to i32523 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)524 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> %a, <4 x i1> %1)525 ret <4 x i32> %2526}527 528define arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_x_u16_f16(<8 x half> %a, i16 zeroext %p) {529; CHECK-LABEL: test_vcvtnq_x_u16_f16:530; CHECK: @ %bb.0: @ %entry531; CHECK-NEXT: vmsr p0, r0532; CHECK-NEXT: vpst533; CHECK-NEXT: vcvtnt.u16.f16 q0, q0534; CHECK-NEXT: bx lr535entry:536 %0 = zext i16 %p to i32537 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)538 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> %a, <8 x i1> %1)539 ret <8 x i16> %2540}541 542define arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_x_u32_f32(<4 x float> %a, i16 zeroext %p) {543; CHECK-LABEL: test_vcvtnq_x_u32_f32:544; CHECK: @ %bb.0: @ %entry545; CHECK-NEXT: vmsr p0, r0546; CHECK-NEXT: vpst547; CHECK-NEXT: vcvtnt.u32.f32 q0, q0548; CHECK-NEXT: bx lr549entry:550 %0 = zext i16 %p to i32551 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)552 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> %a, <4 x i1> %1)553 ret <4 x i32> %2554}555 556define arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_x_s16_f16(<8 x half> %a, i16 zeroext %p) {557; CHECK-LABEL: test_vcvtpq_x_s16_f16:558; CHECK: @ %bb.0: @ %entry559; CHECK-NEXT: vmsr p0, r0560; CHECK-NEXT: vpst561; CHECK-NEXT: vcvtpt.s16.f16 q0, q0562; CHECK-NEXT: bx lr563entry:564 %0 = zext i16 %p to i32565 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)566 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> %a, <8 x i1> %1)567 ret <8 x i16> %2568}569 570define arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_x_s32_f32(<4 x float> %a, i16 zeroext %p) {571; CHECK-LABEL: test_vcvtpq_x_s32_f32:572; CHECK: @ %bb.0: @ %entry573; CHECK-NEXT: vmsr p0, r0574; CHECK-NEXT: vpst575; CHECK-NEXT: vcvtpt.s32.f32 q0, q0576; CHECK-NEXT: bx lr577entry:578 %0 = zext i16 %p to i32579 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)580 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> %a, <4 x i1> %1)581 ret <4 x i32> %2582}583 584define arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_x_u16_f16(<8 x half> %a, i16 zeroext %p) {585; CHECK-LABEL: test_vcvtpq_x_u16_f16:586; CHECK: @ %bb.0: @ %entry587; CHECK-NEXT: vmsr p0, r0588; CHECK-NEXT: vpst589; CHECK-NEXT: vcvtpt.u16.f16 q0, q0590; CHECK-NEXT: bx lr591entry:592 %0 = zext i16 %p to i32593 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)594 %2 = tail call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> %a, <8 x i1> %1)595 ret <8 x i16> %2596}597 598define arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_x_u32_f32(<4 x float> %a, i16 zeroext %p) {599; CHECK-LABEL: test_vcvtpq_x_u32_f32:600; CHECK: @ %bb.0: @ %entry601; CHECK-NEXT: vmsr p0, r0602; CHECK-NEXT: vpst603; CHECK-NEXT: vcvtpt.u32.f32 q0, q0604; CHECK-NEXT: bx lr605entry:606 %0 = zext i16 %p to i32607 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)608 %2 = tail call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> %a, <4 x i1> %1)609 ret <4 x i32> %2610}611 612declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)613declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)614 615declare <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32, <8 x half>)616declare <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32, <4 x float>)617declare <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32, <8 x half>)618declare <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32, <4 x float>)619declare <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32, <8 x half>)620declare <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32, <4 x float>)621declare <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32, <8 x half>)622declare <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32, <4 x float>)623 624declare <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>)625declare <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>)626declare <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>)627declare <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>)628declare <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>)629declare <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>)630declare <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>)631declare <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>)632