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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_s16(<16 x i8> %a, <8 x i16> %b) {5; CHECK-LABEL: test_vshrnbq_n_s16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vshrnb.i16 q0, q1, #38; CHECK-NEXT: bx lr9entry:10 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0)11 ret <16 x i8> %012}13 14define arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_s32(<8 x i16> %a, <4 x i32> %b) {15; CHECK-LABEL: test_vshrnbq_n_s32:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vshrnb.i32 q0, q1, #918; CHECK-NEXT: bx lr19entry:20 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0)21 ret <8 x i16> %022}23 24define arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_u16(<16 x i8> %a, <8 x i16> %b) {25; CHECK-LABEL: test_vshrnbq_n_u16:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vshrnb.i16 q0, q1, #128; CHECK-NEXT: bx lr29entry:30 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 0, i32 1, i32 1, i32 0)31 ret <16 x i8> %032}33 34define arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_u32(<8 x i16> %a, <4 x i32> %b) {35; CHECK-LABEL: test_vshrnbq_n_u32:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vshrnb.i32 q0, q1, #338; CHECK-NEXT: bx lr39entry:40 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 3, i32 0, i32 0, i32 1, i32 1, i32 0)41 ret <8 x i16> %042}43 44define arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_s16(<16 x i8> %a, <8 x i16> %b) {45; CHECK-LABEL: test_vshrntq_n_s16:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vshrnt.i16 q0, q1, #148; CHECK-NEXT: bx lr49entry:50 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1)51 ret <16 x i8> %052}53 54define arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_s32(<8 x i16> %a, <4 x i32> %b) {55; CHECK-LABEL: test_vshrntq_n_s32:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vshrnt.i32 q0, q1, #1058; CHECK-NEXT: bx lr59entry:60 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 10, i32 0, i32 0, i32 0, i32 0, i32 1)61 ret <8 x i16> %062}63 64define arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_u16(<16 x i8> %a, <8 x i16> %b) {65; CHECK-LABEL: test_vshrntq_n_u16:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vshrnt.i16 q0, q1, #668; CHECK-NEXT: bx lr69entry:70 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 6, i32 0, i32 0, i32 1, i32 1, i32 1)71 ret <16 x i8> %072}73 74define arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_u32(<8 x i16> %a, <4 x i32> %b) {75; CHECK-LABEL: test_vshrntq_n_u32:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vshrnt.i32 q0, q1, #1078; CHECK-NEXT: bx lr79entry:80 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 10, i32 0, i32 0, i32 1, i32 1, i32 1)81 ret <8 x i16> %082}83 84define arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {85; CHECK-LABEL: test_vshrnbq_m_n_s16:86; CHECK: @ %bb.0: @ %entry87; CHECK-NEXT: vmsr p0, r088; CHECK-NEXT: vpst89; CHECK-NEXT: vshrnbt.i16 q0, q1, #490; CHECK-NEXT: bx lr91entry:92 %0 = zext i16 %p to i3293 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)94 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i1> %1)95 ret <16 x i8> %296}97 98define arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {99; CHECK-LABEL: test_vshrnbq_m_n_s32:100; CHECK: @ %bb.0: @ %entry101; CHECK-NEXT: vmsr p0, r0102; CHECK-NEXT: vpst103; CHECK-NEXT: vshrnbt.i32 q0, q1, #13104; CHECK-NEXT: bx lr105entry:106 %0 = zext i16 %p to i32107 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)108 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 13, i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i1> %1)109 ret <8 x i16> %2110}111 112define arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {113; CHECK-LABEL: test_vshrnbq_m_n_u16:114; CHECK: @ %bb.0: @ %entry115; CHECK-NEXT: vmsr p0, r0116; CHECK-NEXT: vpst117; CHECK-NEXT: vshrnbt.i16 q0, q1, #7118; CHECK-NEXT: bx lr119entry:120 %0 = zext i16 %p to i32121 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)122 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 7, i32 0, i32 0, i32 1, i32 1, i32 0, <8 x i1> %1)123 ret <16 x i8> %2124}125 126define arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {127; CHECK-LABEL: test_vshrnbq_m_n_u32:128; CHECK: @ %bb.0: @ %entry129; CHECK-NEXT: vmsr p0, r0130; CHECK-NEXT: vpst131; CHECK-NEXT: vshrnbt.i32 q0, q1, #15132; CHECK-NEXT: bx lr133entry:134 %0 = zext i16 %p to i32135 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)136 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 15, i32 0, i32 0, i32 1, i32 1, i32 0, <4 x i1> %1)137 ret <8 x i16> %2138}139 140define arm_aapcs_vfpcc <16 x i8> @test_vshrntq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {141; CHECK-LABEL: test_vshrntq_m_n_s16:142; CHECK: @ %bb.0: @ %entry143; CHECK-NEXT: vmsr p0, r0144; CHECK-NEXT: vpst145; CHECK-NEXT: vshrntt.i16 q0, q1, #6146; CHECK-NEXT: bx lr147entry:148 %0 = zext i16 %p to i32149 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)150 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 6, i32 0, i32 0, i32 0, i32 0, i32 1, <8 x i1> %1)151 ret <16 x i8> %2152}153 154define arm_aapcs_vfpcc <8 x i16> @test_vshrntq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {155; CHECK-LABEL: test_vshrntq_m_n_s32:156; CHECK: @ %bb.0: @ %entry157; CHECK-NEXT: vmsr p0, r0158; CHECK-NEXT: vpst159; CHECK-NEXT: vshrntt.i32 q0, q1, #13160; CHECK-NEXT: bx lr161entry:162 %0 = zext i16 %p to i32163 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)164 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 13, i32 0, i32 0, i32 0, i32 0, i32 1, <4 x i1> %1)165 ret <8 x i16> %2166}167 168define arm_aapcs_vfpcc <16 x i8> @test_vshrntq_m_n_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {169; CHECK-LABEL: test_vshrntq_m_n_u16:170; CHECK: @ %bb.0: @ %entry171; CHECK-NEXT: vmsr p0, r0172; CHECK-NEXT: vpst173; CHECK-NEXT: vshrntt.i16 q0, q1, #1174; CHECK-NEXT: bx lr175entry:176 %0 = zext i16 %p to i32177 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)178 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 0, i32 1, i32 1, i32 1, <8 x i1> %1)179 ret <16 x i8> %2180}181 182define arm_aapcs_vfpcc <8 x i16> @test_vshrntq_m_n_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {183; CHECK-LABEL: test_vshrntq_m_n_u32:184; CHECK: @ %bb.0: @ %entry185; CHECK-NEXT: vmsr p0, r0186; CHECK-NEXT: vpst187; CHECK-NEXT: vshrntt.i32 q0, q1, #10188; CHECK-NEXT: bx lr189entry:190 %0 = zext i16 %p to i32191 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)192 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 10, i32 0, i32 0, i32 1, i32 1, i32 1, <4 x i1> %1)193 ret <8 x i16> %2194}195 196define arm_aapcs_vfpcc <16 x i8> @test_vrshrnbq_n_s16(<16 x i8> %a, <8 x i16> %b) {197; CHECK-LABEL: test_vrshrnbq_n_s16:198; CHECK: @ %bb.0: @ %entry199; CHECK-NEXT: vrshrnb.i16 q0, q1, #5200; CHECK-NEXT: bx lr201entry:202 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 5, i32 0, i32 1, i32 0, i32 0, i32 0)203 ret <16 x i8> %0204}205 206define arm_aapcs_vfpcc <8 x i16> @test_vrshrnbq_n_s32(<8 x i16> %a, <4 x i32> %b) {207; CHECK-LABEL: test_vrshrnbq_n_s32:208; CHECK: @ %bb.0: @ %entry209; CHECK-NEXT: vrshrnb.i32 q0, q1, #10210; CHECK-NEXT: bx lr211entry:212 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 10, i32 0, i32 1, i32 0, i32 0, i32 0)213 ret <8 x i16> %0214}215 216define arm_aapcs_vfpcc <16 x i8> @test_vrshrnbq_n_u16(<16 x i8> %a, <8 x i16> %b) {217; CHECK-LABEL: test_vrshrnbq_n_u16:218; CHECK: @ %bb.0: @ %entry219; CHECK-NEXT: vrshrnb.i16 q0, q1, #2220; CHECK-NEXT: bx lr221entry:222 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 2, i32 0, i32 1, i32 1, i32 1, i32 0)223 ret <16 x i8> %0224}225 226define arm_aapcs_vfpcc <8 x i16> @test_vrshrnbq_n_u32(<8 x i16> %a, <4 x i32> %b) {227; CHECK-LABEL: test_vrshrnbq_n_u32:228; CHECK: @ %bb.0: @ %entry229; CHECK-NEXT: vrshrnb.i32 q0, q1, #12230; CHECK-NEXT: bx lr231entry:232 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 12, i32 0, i32 1, i32 1, i32 1, i32 0)233 ret <8 x i16> %0234}235 236define arm_aapcs_vfpcc <16 x i8> @test_vrshrntq_n_s16(<16 x i8> %a, <8 x i16> %b) {237; CHECK-LABEL: test_vrshrntq_n_s16:238; CHECK: @ %bb.0: @ %entry239; CHECK-NEXT: vrshrnt.i16 q0, q1, #4240; CHECK-NEXT: bx lr241entry:242 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 4, i32 0, i32 1, i32 0, i32 0, i32 1)243 ret <16 x i8> %0244}245 246define arm_aapcs_vfpcc <8 x i16> @test_vrshrntq_n_s32(<8 x i16> %a, <4 x i32> %b) {247; CHECK-LABEL: test_vrshrntq_n_s32:248; CHECK: @ %bb.0: @ %entry249; CHECK-NEXT: vrshrnt.i32 q0, q1, #11250; CHECK-NEXT: bx lr251entry:252 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 11, i32 0, i32 1, i32 0, i32 0, i32 1)253 ret <8 x i16> %0254}255 256define arm_aapcs_vfpcc <16 x i8> @test_vrshrntq_n_u16(<16 x i8> %a, <8 x i16> %b) {257; CHECK-LABEL: test_vrshrntq_n_u16:258; CHECK: @ %bb.0: @ %entry259; CHECK-NEXT: vrshrnt.i16 q0, q1, #1260; CHECK-NEXT: bx lr261entry:262 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 1, i32 1, i32 1, i32 1)263 ret <16 x i8> %0264}265 266define arm_aapcs_vfpcc <8 x i16> @test_vrshrntq_n_u32(<8 x i16> %a, <4 x i32> %b) {267; CHECK-LABEL: test_vrshrntq_n_u32:268; CHECK: @ %bb.0: @ %entry269; CHECK-NEXT: vrshrnt.i32 q0, q1, #6270; CHECK-NEXT: bx lr271entry:272 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 6, i32 0, i32 1, i32 1, i32 1, i32 1)273 ret <8 x i16> %0274}275 276define arm_aapcs_vfpcc <16 x i8> @test_vrshrnbq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {277; CHECK-LABEL: test_vrshrnbq_m_n_s16:278; CHECK: @ %bb.0: @ %entry279; CHECK-NEXT: vmsr p0, r0280; CHECK-NEXT: vpst281; CHECK-NEXT: vrshrnbt.i16 q0, q1, #1282; CHECK-NEXT: bx lr283entry:284 %0 = zext i16 %p to i32285 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)286 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 1, i32 0, i32 0, i32 0, <8 x i1> %1)287 ret <16 x i8> %2288}289 290define arm_aapcs_vfpcc <8 x i16> @test_vrshrnbq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {291; CHECK-LABEL: test_vrshrnbq_m_n_s32:292; CHECK: @ %bb.0: @ %entry293; CHECK-NEXT: vmsr p0, r0294; CHECK-NEXT: vpst295; CHECK-NEXT: vrshrnbt.i32 q0, q1, #14296; CHECK-NEXT: bx lr297entry:298 %0 = zext i16 %p to i32299 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)300 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 14, i32 0, i32 1, i32 0, i32 0, i32 0, <4 x i1> %1)301 ret <8 x i16> %2302}303 304define arm_aapcs_vfpcc <16 x i8> @test_vrshrnbq_m_n_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {305; CHECK-LABEL: test_vrshrnbq_m_n_u16:306; CHECK: @ %bb.0: @ %entry307; CHECK-NEXT: vmsr p0, r0308; CHECK-NEXT: vpst309; CHECK-NEXT: vrshrnbt.i16 q0, q1, #2310; CHECK-NEXT: bx lr311entry:312 %0 = zext i16 %p to i32313 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)314 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 2, i32 0, i32 1, i32 1, i32 1, i32 0, <8 x i1> %1)315 ret <16 x i8> %2316}317 318define arm_aapcs_vfpcc <8 x i16> @test_vrshrnbq_m_n_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {319; CHECK-LABEL: test_vrshrnbq_m_n_u32:320; CHECK: @ %bb.0: @ %entry321; CHECK-NEXT: vmsr p0, r0322; CHECK-NEXT: vpst323; CHECK-NEXT: vrshrnbt.i32 q0, q1, #12324; CHECK-NEXT: bx lr325entry:326 %0 = zext i16 %p to i32327 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)328 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 12, i32 0, i32 1, i32 1, i32 1, i32 0, <4 x i1> %1)329 ret <8 x i16> %2330}331 332define arm_aapcs_vfpcc <16 x i8> @test_vrshrntq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {333; CHECK-LABEL: test_vrshrntq_m_n_s16:334; CHECK: @ %bb.0: @ %entry335; CHECK-NEXT: vmsr p0, r0336; CHECK-NEXT: vpst337; CHECK-NEXT: vrshrntt.i16 q0, q1, #4338; CHECK-NEXT: bx lr339entry:340 %0 = zext i16 %p to i32341 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)342 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 4, i32 0, i32 1, i32 0, i32 0, i32 1, <8 x i1> %1)343 ret <16 x i8> %2344}345 346define arm_aapcs_vfpcc <8 x i16> @test_vrshrntq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {347; CHECK-LABEL: test_vrshrntq_m_n_s32:348; CHECK: @ %bb.0: @ %entry349; CHECK-NEXT: vmsr p0, r0350; CHECK-NEXT: vpst351; CHECK-NEXT: vrshrntt.i32 q0, q1, #6352; CHECK-NEXT: bx lr353entry:354 %0 = zext i16 %p to i32355 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)356 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 6, i32 0, i32 1, i32 0, i32 0, i32 1, <4 x i1> %1)357 ret <8 x i16> %2358}359 360define arm_aapcs_vfpcc <16 x i8> @test_vrshrntq_m_n_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {361; CHECK-LABEL: test_vrshrntq_m_n_u16:362; CHECK: @ %bb.0: @ %entry363; CHECK-NEXT: vmsr p0, r0364; CHECK-NEXT: vpst365; CHECK-NEXT: vrshrntt.i16 q0, q1, #6366; CHECK-NEXT: bx lr367entry:368 %0 = zext i16 %p to i32369 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)370 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 6, i32 0, i32 1, i32 1, i32 1, i32 1, <8 x i1> %1)371 ret <16 x i8> %2372}373 374define arm_aapcs_vfpcc <8 x i16> @test_vrshrntq_m_n_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {375; CHECK-LABEL: test_vrshrntq_m_n_u32:376; CHECK: @ %bb.0: @ %entry377; CHECK-NEXT: vmsr p0, r0378; CHECK-NEXT: vpst379; CHECK-NEXT: vrshrntt.i32 q0, q1, #10380; CHECK-NEXT: bx lr381entry:382 %0 = zext i16 %p to i32383 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)384 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 10, i32 0, i32 1, i32 1, i32 1, i32 1, <4 x i1> %1)385 ret <8 x i16> %2386}387 388define arm_aapcs_vfpcc <16 x i8> @test_vqshrnbq_n_s16(<16 x i8> %a, <8 x i16> %b) {389; CHECK-LABEL: test_vqshrnbq_n_s16:390; CHECK: @ %bb.0: @ %entry391; CHECK-NEXT: vqshrnb.s16 q0, q1, #7392; CHECK-NEXT: bx lr393entry:394 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 7, i32 1, i32 0, i32 0, i32 0, i32 0)395 ret <16 x i8> %0396}397 398define arm_aapcs_vfpcc <8 x i16> @test_vqshrnbq_n_s32(<8 x i16> %a, <4 x i32> %b) {399; CHECK-LABEL: test_vqshrnbq_n_s32:400; CHECK: @ %bb.0: @ %entry401; CHECK-NEXT: vqshrnb.s32 q0, q1, #15402; CHECK-NEXT: bx lr403entry:404 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 15, i32 1, i32 0, i32 0, i32 0, i32 0)405 ret <8 x i16> %0406}407 408define arm_aapcs_vfpcc <16 x i8> @test_vqshrnbq_n_u16(<16 x i8> %a, <8 x i16> %b) {409; CHECK-LABEL: test_vqshrnbq_n_u16:410; CHECK: @ %bb.0: @ %entry411; CHECK-NEXT: vqshrnb.u16 q0, q1, #3412; CHECK-NEXT: bx lr413entry:414 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 3, i32 1, i32 0, i32 1, i32 1, i32 0)415 ret <16 x i8> %0416}417 418define arm_aapcs_vfpcc <8 x i16> @test_vqshrnbq_n_u32(<8 x i16> %a, <4 x i32> %b) {419; CHECK-LABEL: test_vqshrnbq_n_u32:420; CHECK: @ %bb.0: @ %entry421; CHECK-NEXT: vqshrnb.u32 q0, q1, #3422; CHECK-NEXT: bx lr423entry:424 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 3, i32 1, i32 0, i32 1, i32 1, i32 0)425 ret <8 x i16> %0426}427 428define arm_aapcs_vfpcc <16 x i8> @test_vqshrntq_n_s16(<16 x i8> %a, <8 x i16> %b) {429; CHECK-LABEL: test_vqshrntq_n_s16:430; CHECK: @ %bb.0: @ %entry431; CHECK-NEXT: vqshrnt.s16 q0, q1, #5432; CHECK-NEXT: bx lr433entry:434 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 5, i32 1, i32 0, i32 0, i32 0, i32 1)435 ret <16 x i8> %0436}437 438define arm_aapcs_vfpcc <8 x i16> @test_vqshrntq_n_s32(<8 x i16> %a, <4 x i32> %b) {439; CHECK-LABEL: test_vqshrntq_n_s32:440; CHECK: @ %bb.0: @ %entry441; CHECK-NEXT: vqshrnt.s32 q0, q1, #6442; CHECK-NEXT: bx lr443entry:444 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 6, i32 1, i32 0, i32 0, i32 0, i32 1)445 ret <8 x i16> %0446}447 448define arm_aapcs_vfpcc <16 x i8> @test_vqshrntq_n_u16(<16 x i8> %a, <8 x i16> %b) {449; CHECK-LABEL: test_vqshrntq_n_u16:450; CHECK: @ %bb.0: @ %entry451; CHECK-NEXT: vqshrnt.u16 q0, q1, #1452; CHECK-NEXT: bx lr453entry:454 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 0, i32 1, i32 1, i32 1)455 ret <16 x i8> %0456}457 458define arm_aapcs_vfpcc <8 x i16> @test_vqshrntq_n_u32(<8 x i16> %a, <4 x i32> %b) {459; CHECK-LABEL: test_vqshrntq_n_u32:460; CHECK: @ %bb.0: @ %entry461; CHECK-NEXT: vqshrnt.u32 q0, q1, #15462; CHECK-NEXT: bx lr463entry:464 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 15, i32 1, i32 0, i32 1, i32 1, i32 1)465 ret <8 x i16> %0466}467 468define arm_aapcs_vfpcc <16 x i8> @test_vqshrnbq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {469; CHECK-LABEL: test_vqshrnbq_m_n_s16:470; CHECK: @ %bb.0: @ %entry471; CHECK-NEXT: vmsr p0, r0472; CHECK-NEXT: vpst473; CHECK-NEXT: vqshrnbt.s16 q0, q1, #7474; CHECK-NEXT: bx lr475entry:476 %0 = zext i16 %p to i32477 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)478 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 7, i32 1, i32 0, i32 0, i32 0, i32 0, <8 x i1> %1)479 ret <16 x i8> %2480}481 482define arm_aapcs_vfpcc <8 x i16> @test_vqshrnbq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {483; CHECK-LABEL: test_vqshrnbq_m_n_s32:484; CHECK: @ %bb.0: @ %entry485; CHECK-NEXT: vmsr p0, r0486; CHECK-NEXT: vpst487; CHECK-NEXT: vqshrnbt.s32 q0, q1, #1488; CHECK-NEXT: bx lr489entry:490 %0 = zext i16 %p to i32491 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)492 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, <4 x i1> %1)493 ret <8 x i16> %2494}495 496define arm_aapcs_vfpcc <16 x i8> @test_vqshrnbq_m_n_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {497; CHECK-LABEL: test_vqshrnbq_m_n_u16:498; CHECK: @ %bb.0: @ %entry499; CHECK-NEXT: vmsr p0, r0500; CHECK-NEXT: vpst501; CHECK-NEXT: vqshrnbt.u16 q0, q1, #1502; CHECK-NEXT: bx lr503entry:504 %0 = zext i16 %p to i32505 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)506 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 0, i32 1, i32 1, i32 0, <8 x i1> %1)507 ret <16 x i8> %2508}509 510define arm_aapcs_vfpcc <8 x i16> @test_vqshrnbq_m_n_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {511; CHECK-LABEL: test_vqshrnbq_m_n_u32:512; CHECK: @ %bb.0: @ %entry513; CHECK-NEXT: vmsr p0, r0514; CHECK-NEXT: vpst515; CHECK-NEXT: vqshrnbt.u32 q0, q1, #8516; CHECK-NEXT: bx lr517entry:518 %0 = zext i16 %p to i32519 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)520 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 8, i32 1, i32 0, i32 1, i32 1, i32 0, <4 x i1> %1)521 ret <8 x i16> %2522}523 524define arm_aapcs_vfpcc <16 x i8> @test_vqshrntq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {525; CHECK-LABEL: test_vqshrntq_m_n_s16:526; CHECK: @ %bb.0: @ %entry527; CHECK-NEXT: vmsr p0, r0528; CHECK-NEXT: vpst529; CHECK-NEXT: vqshrntt.s16 q0, q1, #1530; CHECK-NEXT: bx lr531entry:532 %0 = zext i16 %p to i32533 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)534 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 0, i32 0, i32 0, i32 1, <8 x i1> %1)535 ret <16 x i8> %2536}537 538define arm_aapcs_vfpcc <8 x i16> @test_vqshrntq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {539; CHECK-LABEL: test_vqshrntq_m_n_s32:540; CHECK: @ %bb.0: @ %entry541; CHECK-NEXT: vmsr p0, r0542; CHECK-NEXT: vpst543; CHECK-NEXT: vqshrntt.s32 q0, q1, #11544; CHECK-NEXT: bx lr545entry:546 %0 = zext i16 %p to i32547 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)548 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 11, i32 1, i32 0, i32 0, i32 0, i32 1, <4 x i1> %1)549 ret <8 x i16> %2550}551 552define arm_aapcs_vfpcc <16 x i8> @test_vqshrntq_m_n_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {553; CHECK-LABEL: test_vqshrntq_m_n_u16:554; CHECK: @ %bb.0: @ %entry555; CHECK-NEXT: vmsr p0, r0556; CHECK-NEXT: vpst557; CHECK-NEXT: vqshrntt.u16 q0, q1, #3558; CHECK-NEXT: bx lr559entry:560 %0 = zext i16 %p to i32561 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)562 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 3, i32 1, i32 0, i32 1, i32 1, i32 1, <8 x i1> %1)563 ret <16 x i8> %2564}565 566define arm_aapcs_vfpcc <8 x i16> @test_vqshrntq_m_n_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {567; CHECK-LABEL: test_vqshrntq_m_n_u32:568; CHECK: @ %bb.0: @ %entry569; CHECK-NEXT: vmsr p0, r0570; CHECK-NEXT: vpst571; CHECK-NEXT: vqshrntt.u32 q0, q1, #1572; CHECK-NEXT: bx lr573entry:574 %0 = zext i16 %p to i32575 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)576 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, i32 1, i32 0, i32 1, i32 1, i32 1, <4 x i1> %1)577 ret <8 x i16> %2578}579 580define arm_aapcs_vfpcc <16 x i8> @test_vqshrunbq_n_s16(<16 x i8> %a, <8 x i16> %b) {581; CHECK-LABEL: test_vqshrunbq_n_s16:582; CHECK: @ %bb.0: @ %entry583; CHECK-NEXT: vqshrunb.s16 q0, q1, #5584; CHECK-NEXT: bx lr585entry:586 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 5, i32 1, i32 0, i32 1, i32 0, i32 0)587 ret <16 x i8> %0588}589 590define arm_aapcs_vfpcc <8 x i16> @test_vqshrunbq_n_s32(<8 x i16> %a, <4 x i32> %b) {591; CHECK-LABEL: test_vqshrunbq_n_s32:592; CHECK: @ %bb.0: @ %entry593; CHECK-NEXT: vqshrunb.s32 q0, q1, #13594; CHECK-NEXT: bx lr595entry:596 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 13, i32 1, i32 0, i32 1, i32 0, i32 0)597 ret <8 x i16> %0598}599 600define arm_aapcs_vfpcc <16 x i8> @test_vqshruntq_n_s16(<16 x i8> %a, <8 x i16> %b) {601; CHECK-LABEL: test_vqshruntq_n_s16:602; CHECK: @ %bb.0: @ %entry603; CHECK-NEXT: vqshrunt.s16 q0, q1, #2604; CHECK-NEXT: bx lr605entry:606 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 2, i32 1, i32 0, i32 1, i32 0, i32 1)607 ret <16 x i8> %0608}609 610define arm_aapcs_vfpcc <8 x i16> @test_vqshruntq_n_s32(<8 x i16> %a, <4 x i32> %b) {611; CHECK-LABEL: test_vqshruntq_n_s32:612; CHECK: @ %bb.0: @ %entry613; CHECK-NEXT: vqshrunt.s32 q0, q1, #7614; CHECK-NEXT: bx lr615entry:616 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 7, i32 1, i32 0, i32 1, i32 0, i32 1)617 ret <8 x i16> %0618}619 620define arm_aapcs_vfpcc <16 x i8> @test_vqshrunbq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {621; CHECK-LABEL: test_vqshrunbq_m_n_s16:622; CHECK: @ %bb.0: @ %entry623; CHECK-NEXT: vmsr p0, r0624; CHECK-NEXT: vpst625; CHECK-NEXT: vqshrunbt.s16 q0, q1, #7626; CHECK-NEXT: bx lr627entry:628 %0 = zext i16 %p to i32629 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)630 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 7, i32 1, i32 0, i32 1, i32 0, i32 0, <8 x i1> %1)631 ret <16 x i8> %2632}633 634define arm_aapcs_vfpcc <8 x i16> @test_vqshrunbq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {635; CHECK-LABEL: test_vqshrunbq_m_n_s32:636; CHECK: @ %bb.0: @ %entry637; CHECK-NEXT: vmsr p0, r0638; CHECK-NEXT: vpst639; CHECK-NEXT: vqshrunbt.s32 q0, q1, #7640; CHECK-NEXT: bx lr641entry:642 %0 = zext i16 %p to i32643 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)644 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 7, i32 1, i32 0, i32 1, i32 0, i32 0, <4 x i1> %1)645 ret <8 x i16> %2646}647 648define arm_aapcs_vfpcc <16 x i8> @test_vqshruntq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {649; CHECK-LABEL: test_vqshruntq_m_n_s16:650; CHECK: @ %bb.0: @ %entry651; CHECK-NEXT: vmsr p0, r0652; CHECK-NEXT: vpst653; CHECK-NEXT: vqshruntt.s16 q0, q1, #7654; CHECK-NEXT: bx lr655entry:656 %0 = zext i16 %p to i32657 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)658 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 7, i32 1, i32 0, i32 1, i32 0, i32 1, <8 x i1> %1)659 ret <16 x i8> %2660}661 662define arm_aapcs_vfpcc <8 x i16> @test_vqshruntq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {663; CHECK-LABEL: test_vqshruntq_m_n_s32:664; CHECK: @ %bb.0: @ %entry665; CHECK-NEXT: vmsr p0, r0666; CHECK-NEXT: vpst667; CHECK-NEXT: vqshruntt.s32 q0, q1, #7668; CHECK-NEXT: bx lr669entry:670 %0 = zext i16 %p to i32671 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)672 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 7, i32 1, i32 0, i32 1, i32 0, i32 1, <4 x i1> %1)673 ret <8 x i16> %2674}675 676define arm_aapcs_vfpcc <16 x i8> @test_vqrshrnbq_n_s16(<16 x i8> %a, <8 x i16> %b) {677; CHECK-LABEL: test_vqrshrnbq_n_s16:678; CHECK: @ %bb.0: @ %entry679; CHECK-NEXT: vqrshrnb.s16 q0, q1, #5680; CHECK-NEXT: bx lr681entry:682 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 5, i32 1, i32 1, i32 0, i32 0, i32 0)683 ret <16 x i8> %0684}685 686define arm_aapcs_vfpcc <8 x i16> @test_vqrshrnbq_n_s32(<8 x i16> %a, <4 x i32> %b) {687; CHECK-LABEL: test_vqrshrnbq_n_s32:688; CHECK: @ %bb.0: @ %entry689; CHECK-NEXT: vqrshrnb.s32 q0, q1, #13690; CHECK-NEXT: bx lr691entry:692 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 13, i32 1, i32 1, i32 0, i32 0, i32 0)693 ret <8 x i16> %0694}695 696define arm_aapcs_vfpcc <16 x i8> @test_vqrshrnbq_n_u16(<16 x i8> %a, <8 x i16> %b) {697; CHECK-LABEL: test_vqrshrnbq_n_u16:698; CHECK: @ %bb.0: @ %entry699; CHECK-NEXT: vqrshrnb.u16 q0, q1, #7700; CHECK-NEXT: bx lr701entry:702 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 7, i32 1, i32 1, i32 1, i32 1, i32 0)703 ret <16 x i8> %0704}705 706define arm_aapcs_vfpcc <8 x i16> @test_vqrshrnbq_n_u32(<8 x i16> %a, <4 x i32> %b) {707; CHECK-LABEL: test_vqrshrnbq_n_u32:708; CHECK: @ %bb.0: @ %entry709; CHECK-NEXT: vqrshrnb.u32 q0, q1, #8710; CHECK-NEXT: bx lr711entry:712 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 8, i32 1, i32 1, i32 1, i32 1, i32 0)713 ret <8 x i16> %0714}715 716define arm_aapcs_vfpcc <16 x i8> @test_vqrshrntq_n_s16(<16 x i8> %a, <8 x i16> %b) {717; CHECK-LABEL: test_vqrshrntq_n_s16:718; CHECK: @ %bb.0: @ %entry719; CHECK-NEXT: vqrshrnt.s16 q0, q1, #7720; CHECK-NEXT: bx lr721entry:722 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 7, i32 1, i32 1, i32 0, i32 0, i32 1)723 ret <16 x i8> %0724}725 726define arm_aapcs_vfpcc <8 x i16> @test_vqrshrntq_n_s32(<8 x i16> %a, <4 x i32> %b) {727; CHECK-LABEL: test_vqrshrntq_n_s32:728; CHECK: @ %bb.0: @ %entry729; CHECK-NEXT: vqrshrnt.s32 q0, q1, #2730; CHECK-NEXT: bx lr731entry:732 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 2, i32 1, i32 1, i32 0, i32 0, i32 1)733 ret <8 x i16> %0734}735 736define arm_aapcs_vfpcc <16 x i8> @test_vqrshrntq_n_u16(<16 x i8> %a, <8 x i16> %b) {737; CHECK-LABEL: test_vqrshrntq_n_u16:738; CHECK: @ %bb.0: @ %entry739; CHECK-NEXT: vqrshrnt.u16 q0, q1, #1740; CHECK-NEXT: bx lr741entry:742 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1)743 ret <16 x i8> %0744}745 746define arm_aapcs_vfpcc <8 x i16> @test_vqrshrntq_n_u32(<8 x i16> %a, <4 x i32> %b) {747; CHECK-LABEL: test_vqrshrntq_n_u32:748; CHECK: @ %bb.0: @ %entry749; CHECK-NEXT: vqrshrnt.u32 q0, q1, #11750; CHECK-NEXT: bx lr751entry:752 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 11, i32 1, i32 1, i32 1, i32 1, i32 1)753 ret <8 x i16> %0754}755 756define arm_aapcs_vfpcc <16 x i8> @test_vqrshrnbq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {757; CHECK-LABEL: test_vqrshrnbq_m_n_s16:758; CHECK: @ %bb.0: @ %entry759; CHECK-NEXT: vmsr p0, r0760; CHECK-NEXT: vpst761; CHECK-NEXT: vqrshrnbt.s16 q0, q1, #2762; CHECK-NEXT: bx lr763entry:764 %0 = zext i16 %p to i32765 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)766 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 2, i32 1, i32 1, i32 0, i32 0, i32 0, <8 x i1> %1)767 ret <16 x i8> %2768}769 770define arm_aapcs_vfpcc <8 x i16> @test_vqrshrnbq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {771; CHECK-LABEL: test_vqrshrnbq_m_n_s32:772; CHECK: @ %bb.0: @ %entry773; CHECK-NEXT: vmsr p0, r0774; CHECK-NEXT: vpst775; CHECK-NEXT: vqrshrnbt.s32 q0, q1, #12776; CHECK-NEXT: bx lr777entry:778 %0 = zext i16 %p to i32779 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)780 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 12, i32 1, i32 1, i32 0, i32 0, i32 0, <4 x i1> %1)781 ret <8 x i16> %2782}783 784define arm_aapcs_vfpcc <16 x i8> @test_vqrshrnbq_m_n_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {785; CHECK-LABEL: test_vqrshrnbq_m_n_u16:786; CHECK: @ %bb.0: @ %entry787; CHECK-NEXT: vmsr p0, r0788; CHECK-NEXT: vpst789; CHECK-NEXT: vqrshrnbt.u16 q0, q1, #5790; CHECK-NEXT: bx lr791entry:792 %0 = zext i16 %p to i32793 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)794 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 5, i32 1, i32 1, i32 1, i32 1, i32 0, <8 x i1> %1)795 ret <16 x i8> %2796}797 798define arm_aapcs_vfpcc <8 x i16> @test_vqrshrnbq_m_n_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {799; CHECK-LABEL: test_vqrshrnbq_m_n_u32:800; CHECK: @ %bb.0: @ %entry801; CHECK-NEXT: vmsr p0, r0802; CHECK-NEXT: vpst803; CHECK-NEXT: vqrshrnbt.u32 q0, q1, #11804; CHECK-NEXT: bx lr805entry:806 %0 = zext i16 %p to i32807 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)808 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 11, i32 1, i32 1, i32 1, i32 1, i32 0, <4 x i1> %1)809 ret <8 x i16> %2810}811 812define arm_aapcs_vfpcc <16 x i8> @test_vqrshrntq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {813; CHECK-LABEL: test_vqrshrntq_m_n_s16:814; CHECK: @ %bb.0: @ %entry815; CHECK-NEXT: vmsr p0, r0816; CHECK-NEXT: vpst817; CHECK-NEXT: vqrshrntt.s16 q0, q1, #4818; CHECK-NEXT: bx lr819entry:820 %0 = zext i16 %p to i32821 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)822 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 4, i32 1, i32 1, i32 0, i32 0, i32 1, <8 x i1> %1)823 ret <16 x i8> %2824}825 826define arm_aapcs_vfpcc <8 x i16> @test_vqrshrntq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {827; CHECK-LABEL: test_vqrshrntq_m_n_s32:828; CHECK: @ %bb.0: @ %entry829; CHECK-NEXT: vmsr p0, r0830; CHECK-NEXT: vpst831; CHECK-NEXT: vqrshrntt.s32 q0, q1, #6832; CHECK-NEXT: bx lr833entry:834 %0 = zext i16 %p to i32835 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)836 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 6, i32 1, i32 1, i32 0, i32 0, i32 1, <4 x i1> %1)837 ret <8 x i16> %2838}839 840define arm_aapcs_vfpcc <16 x i8> @test_vqrshrntq_m_n_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {841; CHECK-LABEL: test_vqrshrntq_m_n_u16:842; CHECK: @ %bb.0: @ %entry843; CHECK-NEXT: vmsr p0, r0844; CHECK-NEXT: vpst845; CHECK-NEXT: vqrshrntt.u16 q0, q1, #7846; CHECK-NEXT: bx lr847entry:848 %0 = zext i16 %p to i32849 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)850 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 7, i32 1, i32 1, i32 1, i32 1, i32 1, <8 x i1> %1)851 ret <16 x i8> %2852}853 854define arm_aapcs_vfpcc <8 x i16> @test_vqrshrntq_m_n_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {855; CHECK-LABEL: test_vqrshrntq_m_n_u32:856; CHECK: @ %bb.0: @ %entry857; CHECK-NEXT: vmsr p0, r0858; CHECK-NEXT: vpst859; CHECK-NEXT: vqrshrntt.u32 q0, q1, #15860; CHECK-NEXT: bx lr861entry:862 %0 = zext i16 %p to i32863 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)864 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 15, i32 1, i32 1, i32 1, i32 1, i32 1, <4 x i1> %1)865 ret <8 x i16> %2866}867 868define arm_aapcs_vfpcc <16 x i8> @test_vqrshrunbq_n_s16(<16 x i8> %a, <8 x i16> %b) {869; CHECK-LABEL: test_vqrshrunbq_n_s16:870; CHECK: @ %bb.0: @ %entry871; CHECK-NEXT: vqshrunb.s16 q0, q1, #7872; CHECK-NEXT: bx lr873entry:874 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 7, i32 1, i32 0, i32 1, i32 0, i32 0)875 ret <16 x i8> %0876}877 878define arm_aapcs_vfpcc <8 x i16> @test_vqrshrunbq_n_s32(<8 x i16> %a, <4 x i32> %b) {879; CHECK-LABEL: test_vqrshrunbq_n_s32:880; CHECK: @ %bb.0: @ %entry881; CHECK-NEXT: vqshrunb.s32 q0, q1, #1882; CHECK-NEXT: bx lr883entry:884 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 1, i32 1, i32 0, i32 1, i32 0, i32 0)885 ret <8 x i16> %0886}887 888define arm_aapcs_vfpcc <16 x i8> @test_vqrshruntq_n_s16(<16 x i8> %a, <8 x i16> %b) {889; CHECK-LABEL: test_vqrshruntq_n_s16:890; CHECK: @ %bb.0: @ %entry891; CHECK-NEXT: vqshrunt.s16 q0, q1, #1892; CHECK-NEXT: bx lr893entry:894 %0 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 0, i32 1, i32 0, i32 1)895 ret <16 x i8> %0896}897 898define arm_aapcs_vfpcc <8 x i16> @test_vqrshruntq_n_s32(<8 x i16> %a, <4 x i32> %b) {899; CHECK-LABEL: test_vqrshruntq_n_s32:900; CHECK: @ %bb.0: @ %entry901; CHECK-NEXT: vqshrunt.s32 q0, q1, #3902; CHECK-NEXT: bx lr903entry:904 %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 3, i32 1, i32 0, i32 1, i32 0, i32 1)905 ret <8 x i16> %0906}907 908define arm_aapcs_vfpcc <16 x i8> @test_vqrshrunbq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {909; CHECK-LABEL: test_vqrshrunbq_m_n_s16:910; CHECK: @ %bb.0: @ %entry911; CHECK-NEXT: vmsr p0, r0912; CHECK-NEXT: vpst913; CHECK-NEXT: vqshrunbt.s16 q0, q1, #4914; CHECK-NEXT: bx lr915entry:916 %0 = zext i16 %p to i32917 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)918 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 4, i32 1, i32 0, i32 1, i32 0, i32 0, <8 x i1> %1)919 ret <16 x i8> %2920}921 922define arm_aapcs_vfpcc <8 x i16> @test_vqrshrunbq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {923; CHECK-LABEL: test_vqrshrunbq_m_n_s32:924; CHECK: @ %bb.0: @ %entry925; CHECK-NEXT: vmsr p0, r0926; CHECK-NEXT: vpst927; CHECK-NEXT: vqshrunbt.s32 q0, q1, #10928; CHECK-NEXT: bx lr929entry:930 %0 = zext i16 %p to i32931 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)932 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 10, i32 1, i32 0, i32 1, i32 0, i32 0, <4 x i1> %1)933 ret <8 x i16> %2934}935 936define arm_aapcs_vfpcc <16 x i8> @test_vqrshruntq_m_n_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {937; CHECK-LABEL: test_vqrshruntq_m_n_s16:938; CHECK: @ %bb.0: @ %entry939; CHECK-NEXT: vmsr p0, r0940; CHECK-NEXT: vpst941; CHECK-NEXT: vqshruntt.s16 q0, q1, #3942; CHECK-NEXT: bx lr943entry:944 %0 = zext i16 %p to i32945 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)946 %2 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 3, i32 1, i32 0, i32 1, i32 0, i32 1, <8 x i1> %1)947 ret <16 x i8> %2948}949 950define arm_aapcs_vfpcc <8 x i16> @test_vqrshruntq_m_n_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {951; CHECK-LABEL: test_vqrshruntq_m_n_s32:952; CHECK: @ %bb.0: @ %entry953; CHECK-NEXT: vmsr p0, r0954; CHECK-NEXT: vpst955; CHECK-NEXT: vqshruntt.s32 q0, q1, #13956; CHECK-NEXT: bx lr957entry:958 %0 = zext i16 %p to i32959 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)960 %2 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 13, i32 1, i32 0, i32 1, i32 0, i32 1, <4 x i1> %1)961 ret <8 x i16> %2962}963 964define arm_aapcs_vfpcc <16 x i8> @test_vsliq_n_s8(<16 x i8> %a, <16 x i8> %b) {965; CHECK-LABEL: test_vsliq_n_s8:966; CHECK: @ %bb.0: @ %entry967; CHECK-NEXT: vsli.8 q0, q1, #2968; CHECK-NEXT: bx lr969entry:970 %0 = call <16 x i8> @llvm.arm.mve.vsli.v16i8(<16 x i8> %a, <16 x i8> %b, i32 2)971 ret <16 x i8> %0972}973 974define arm_aapcs_vfpcc <8 x i16> @test_vsliq_n_s16(<8 x i16> %a, <8 x i16> %b) {975; CHECK-LABEL: test_vsliq_n_s16:976; CHECK: @ %bb.0: @ %entry977; CHECK-NEXT: vsli.16 q0, q1, #10978; CHECK-NEXT: bx lr979entry:980 %0 = call <8 x i16> @llvm.arm.mve.vsli.v8i16(<8 x i16> %a, <8 x i16> %b, i32 10)981 ret <8 x i16> %0982}983 984define arm_aapcs_vfpcc <4 x i32> @test_vsliq_n_s32(<4 x i32> %a, <4 x i32> %b) {985; CHECK-LABEL: test_vsliq_n_s32:986; CHECK: @ %bb.0: @ %entry987; CHECK-NEXT: vsli.32 q0, q1, #1988; CHECK-NEXT: bx lr989entry:990 %0 = call <4 x i32> @llvm.arm.mve.vsli.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1)991 ret <4 x i32> %0992}993 994define arm_aapcs_vfpcc <16 x i8> @test_vsliq_n_u8(<16 x i8> %a, <16 x i8> %b) {995; CHECK-LABEL: test_vsliq_n_u8:996; CHECK: @ %bb.0: @ %entry997; CHECK-NEXT: vsli.8 q0, q1, #1998; CHECK-NEXT: bx lr999entry:1000 %0 = call <16 x i8> @llvm.arm.mve.vsli.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1)1001 ret <16 x i8> %01002}1003 1004define arm_aapcs_vfpcc <8 x i16> @test_vsliq_n_u16(<8 x i16> %a, <8 x i16> %b) {1005; CHECK-LABEL: test_vsliq_n_u16:1006; CHECK: @ %bb.0: @ %entry1007; CHECK-NEXT: vsli.16 q0, q1, #11008; CHECK-NEXT: bx lr1009entry:1010 %0 = call <8 x i16> @llvm.arm.mve.vsli.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1)1011 ret <8 x i16> %01012}1013 1014define arm_aapcs_vfpcc <4 x i32> @test_vsliq_n_u32(<4 x i32> %a, <4 x i32> %b) {1015; CHECK-LABEL: test_vsliq_n_u32:1016; CHECK: @ %bb.0: @ %entry1017; CHECK-NEXT: vsli.32 q0, q1, #281018; CHECK-NEXT: bx lr1019entry:1020 %0 = call <4 x i32> @llvm.arm.mve.vsli.v4i32(<4 x i32> %a, <4 x i32> %b, i32 28)1021 ret <4 x i32> %01022}1023 1024define arm_aapcs_vfpcc <16 x i8> @test_vsliq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {1025; CHECK-LABEL: test_vsliq_m_n_s8:1026; CHECK: @ %bb.0: @ %entry1027; CHECK-NEXT: vmsr p0, r01028; CHECK-NEXT: vpst1029; CHECK-NEXT: vslit.8 q0, q1, #41030; CHECK-NEXT: bx lr1031entry:1032 %0 = zext i16 %p to i321033 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1034 %2 = call <16 x i8> @llvm.arm.mve.vsli.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 4, <16 x i1> %1)1035 ret <16 x i8> %21036}1037 1038define arm_aapcs_vfpcc <8 x i16> @test_vsliq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {1039; CHECK-LABEL: test_vsliq_m_n_s16:1040; CHECK: @ %bb.0: @ %entry1041; CHECK-NEXT: vmsr p0, r01042; CHECK-NEXT: vpst1043; CHECK-NEXT: vslit.16 q0, q1, #11044; CHECK-NEXT: bx lr1045entry:1046 %0 = zext i16 %p to i321047 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1048 %2 = call <8 x i16> @llvm.arm.mve.vsli.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, <8 x i1> %1)1049 ret <8 x i16> %21050}1051 1052define arm_aapcs_vfpcc <4 x i32> @test_vsliq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {1053; CHECK-LABEL: test_vsliq_m_n_s32:1054; CHECK: @ %bb.0: @ %entry1055; CHECK-NEXT: vmsr p0, r01056; CHECK-NEXT: vpst1057; CHECK-NEXT: vslit.32 q0, q1, #11058; CHECK-NEXT: bx lr1059entry:1060 %0 = zext i16 %p to i321061 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1062 %2 = call <4 x i32> @llvm.arm.mve.vsli.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, <4 x i1> %1)1063 ret <4 x i32> %21064}1065 1066define arm_aapcs_vfpcc <16 x i8> @test_vsliq_m_n_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {1067; CHECK-LABEL: test_vsliq_m_n_u8:1068; CHECK: @ %bb.0: @ %entry1069; CHECK-NEXT: vmsr p0, r01070; CHECK-NEXT: vpst1071; CHECK-NEXT: vslit.8 q0, q1, #51072; CHECK-NEXT: bx lr1073entry:1074 %0 = zext i16 %p to i321075 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1076 %2 = call <16 x i8> @llvm.arm.mve.vsli.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 5, <16 x i1> %1)1077 ret <16 x i8> %21078}1079 1080define arm_aapcs_vfpcc <8 x i16> @test_vsliq_m_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {1081; CHECK-LABEL: test_vsliq_m_n_u16:1082; CHECK: @ %bb.0: @ %entry1083; CHECK-NEXT: vmsr p0, r01084; CHECK-NEXT: vpst1085; CHECK-NEXT: vslit.16 q0, q1, #31086; CHECK-NEXT: bx lr1087entry:1088 %0 = zext i16 %p to i321089 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1090 %2 = call <8 x i16> @llvm.arm.mve.vsli.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 3, <8 x i1> %1)1091 ret <8 x i16> %21092}1093 1094define arm_aapcs_vfpcc <4 x i32> @test_vsliq_m_n_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {1095; CHECK-LABEL: test_vsliq_m_n_u32:1096; CHECK: @ %bb.0: @ %entry1097; CHECK-NEXT: vmsr p0, r01098; CHECK-NEXT: vpst1099; CHECK-NEXT: vslit.32 q0, q1, #91100; CHECK-NEXT: bx lr1101entry:1102 %0 = zext i16 %p to i321103 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1104 %2 = call <4 x i32> @llvm.arm.mve.vsli.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 9, <4 x i1> %1)1105 ret <4 x i32> %21106}1107 1108define arm_aapcs_vfpcc <16 x i8> @test_vsriq_n_s8(<16 x i8> %a, <16 x i8> %b) {1109; CHECK-LABEL: test_vsriq_n_s8:1110; CHECK: @ %bb.0: @ %entry1111; CHECK-NEXT: vsri.8 q0, q1, #31112; CHECK-NEXT: bx lr1113entry:1114 %0 = call <16 x i8> @llvm.arm.mve.vsri.v16i8(<16 x i8> %a, <16 x i8> %b, i32 3)1115 ret <16 x i8> %01116}1117 1118define arm_aapcs_vfpcc <8 x i16> @test_vsriq_n_s16(<8 x i16> %a, <8 x i16> %b) {1119; CHECK-LABEL: test_vsriq_n_s16:1120; CHECK: @ %bb.0: @ %entry1121; CHECK-NEXT: vsri.16 q0, q1, #21122; CHECK-NEXT: bx lr1123entry:1124 %0 = call <8 x i16> @llvm.arm.mve.vsri.v8i16(<8 x i16> %a, <8 x i16> %b, i32 2)1125 ret <8 x i16> %01126}1127 1128define arm_aapcs_vfpcc <4 x i32> @test_vsriq_n_s32(<4 x i32> %a, <4 x i32> %b) {1129; CHECK-LABEL: test_vsriq_n_s32:1130; CHECK: @ %bb.0: @ %entry1131; CHECK-NEXT: vsri.32 q0, q1, #281132; CHECK-NEXT: bx lr1133entry:1134 %0 = call <4 x i32> @llvm.arm.mve.vsri.v4i32(<4 x i32> %a, <4 x i32> %b, i32 28)1135 ret <4 x i32> %01136}1137 1138define arm_aapcs_vfpcc <16 x i8> @test_vsriq_n_u8(<16 x i8> %a, <16 x i8> %b) {1139; CHECK-LABEL: test_vsriq_n_u8:1140; CHECK: @ %bb.0: @ %entry1141; CHECK-NEXT: vsri.8 q0, q1, #31142; CHECK-NEXT: bx lr1143entry:1144 %0 = call <16 x i8> @llvm.arm.mve.vsri.v16i8(<16 x i8> %a, <16 x i8> %b, i32 3)1145 ret <16 x i8> %01146}1147 1148define arm_aapcs_vfpcc <8 x i16> @test_vsriq_n_u16(<8 x i16> %a, <8 x i16> %b) {1149; CHECK-LABEL: test_vsriq_n_u16:1150; CHECK: @ %bb.0: @ %entry1151; CHECK-NEXT: vsri.16 q0, q1, #31152; CHECK-NEXT: bx lr1153entry:1154 %0 = call <8 x i16> @llvm.arm.mve.vsri.v8i16(<8 x i16> %a, <8 x i16> %b, i32 3)1155 ret <8 x i16> %01156}1157 1158define arm_aapcs_vfpcc <4 x i32> @test_vsriq_n_u32(<4 x i32> %a, <4 x i32> %b) {1159; CHECK-LABEL: test_vsriq_n_u32:1160; CHECK: @ %bb.0: @ %entry1161; CHECK-NEXT: vsri.32 q0, q1, #261162; CHECK-NEXT: bx lr1163entry:1164 %0 = call <4 x i32> @llvm.arm.mve.vsri.v4i32(<4 x i32> %a, <4 x i32> %b, i32 26)1165 ret <4 x i32> %01166}1167 1168define arm_aapcs_vfpcc <16 x i8> @test_vsriq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {1169; CHECK-LABEL: test_vsriq_m_n_s8:1170; CHECK: @ %bb.0: @ %entry1171; CHECK-NEXT: vmsr p0, r01172; CHECK-NEXT: vpst1173; CHECK-NEXT: vsrit.8 q0, q1, #41174; CHECK-NEXT: bx lr1175entry:1176 %0 = zext i16 %p to i321177 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1178 %2 = call <16 x i8> @llvm.arm.mve.vsri.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 4, <16 x i1> %1)1179 ret <16 x i8> %21180}1181 1182define arm_aapcs_vfpcc <8 x i16> @test_vsriq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {1183; CHECK-LABEL: test_vsriq_m_n_s16:1184; CHECK: @ %bb.0: @ %entry1185; CHECK-NEXT: vmsr p0, r01186; CHECK-NEXT: vpst1187; CHECK-NEXT: vsrit.16 q0, q1, #11188; CHECK-NEXT: bx lr1189entry:1190 %0 = zext i16 %p to i321191 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1192 %2 = call <8 x i16> @llvm.arm.mve.vsri.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, <8 x i1> %1)1193 ret <8 x i16> %21194}1195 1196define arm_aapcs_vfpcc <4 x i32> @test_vsriq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {1197; CHECK-LABEL: test_vsriq_m_n_s32:1198; CHECK: @ %bb.0: @ %entry1199; CHECK-NEXT: vmsr p0, r01200; CHECK-NEXT: vpst1201; CHECK-NEXT: vsrit.32 q0, q1, #271202; CHECK-NEXT: bx lr1203entry:1204 %0 = zext i16 %p to i321205 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1206 %2 = call <4 x i32> @llvm.arm.mve.vsri.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 27, <4 x i1> %1)1207 ret <4 x i32> %21208}1209 1210define arm_aapcs_vfpcc <16 x i8> @test_vsriq_m_n_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {1211; CHECK-LABEL: test_vsriq_m_n_u8:1212; CHECK: @ %bb.0: @ %entry1213; CHECK-NEXT: vmsr p0, r01214; CHECK-NEXT: vpst1215; CHECK-NEXT: vsrit.8 q0, q1, #71216; CHECK-NEXT: bx lr1217entry:1218 %0 = zext i16 %p to i321219 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1220 %2 = call <16 x i8> @llvm.arm.mve.vsri.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 7, <16 x i1> %1)1221 ret <16 x i8> %21222}1223 1224define arm_aapcs_vfpcc <8 x i16> @test_vsriq_m_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {1225; CHECK-LABEL: test_vsriq_m_n_u16:1226; CHECK: @ %bb.0: @ %entry1227; CHECK-NEXT: vmsr p0, r01228; CHECK-NEXT: vpst1229; CHECK-NEXT: vsrit.16 q0, q1, #91230; CHECK-NEXT: bx lr1231entry:1232 %0 = zext i16 %p to i321233 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1234 %2 = call <8 x i16> @llvm.arm.mve.vsri.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 9, <8 x i1> %1)1235 ret <8 x i16> %21236}1237 1238define arm_aapcs_vfpcc <4 x i32> @test_vsriq_m_n_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {1239; CHECK-LABEL: test_vsriq_m_n_u32:1240; CHECK: @ %bb.0: @ %entry1241; CHECK-NEXT: vmsr p0, r01242; CHECK-NEXT: vpst1243; CHECK-NEXT: vsrit.32 q0, q1, #131244; CHECK-NEXT: bx lr1245entry:1246 %0 = zext i16 %p to i321247 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1248 %2 = call <4 x i32> @llvm.arm.mve.vsri.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 13, <4 x i1> %1)1249 ret <4 x i32> %21250}1251 1252declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32)1253declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32)1254declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)1255declare <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32, <8 x i1>)1256declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)1257declare <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32, <4 x i1>)1258declare <16 x i8> @llvm.arm.mve.vsli.v16i8(<16 x i8>, <16 x i8>, i32)1259declare <8 x i16> @llvm.arm.mve.vsli.v8i16(<8 x i16>, <8 x i16>, i32)1260declare <4 x i32> @llvm.arm.mve.vsli.v4i32(<4 x i32>, <4 x i32>, i32)1261declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)1262declare <16 x i8> @llvm.arm.mve.vsli.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)1263declare <8 x i16> @llvm.arm.mve.vsli.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)1264declare <4 x i32> @llvm.arm.mve.vsli.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)1265declare <16 x i8> @llvm.arm.mve.vsri.v16i8(<16 x i8>, <16 x i8>, i32)1266declare <8 x i16> @llvm.arm.mve.vsri.v8i16(<8 x i16>, <8 x i16>, i32)1267declare <4 x i32> @llvm.arm.mve.vsri.v4i32(<4 x i32>, <4 x i32>, i32)1268declare <16 x i8> @llvm.arm.mve.vsri.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)1269declare <8 x i16> @llvm.arm.mve.vsri.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)1270declare <4 x i32> @llvm.arm.mve.vsri.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)1271