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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8(<16 x i8> %a) {5; CHECK-LABEL: test_vshlq_n_s8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vshl.i8 q0, q0, #58; CHECK-NEXT: bx lr9entry:10 %0 = shl <16 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>11 ret <16 x i8> %012}13 14define arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16(<8 x i16> %a) {15; CHECK-LABEL: test_vshlq_n_s16:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vshl.i16 q0, q0, #518; CHECK-NEXT: bx lr19entry:20 %0 = shl <8 x i16> %a, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>21 ret <8 x i16> %022}23 24define arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32(<4 x i32> %a) {25; CHECK-LABEL: test_vshlq_n_s32:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vshl.i32 q0, q0, #1828; CHECK-NEXT: bx lr29entry:30 %0 = shl <4 x i32> %a, <i32 18, i32 18, i32 18, i32 18>31 ret <4 x i32> %032}33 34define arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8(<16 x i8> %a) {35; CHECK-LABEL: test_vshrq_n_s8:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vshr.s8 q0, q0, #438; CHECK-NEXT: bx lr39entry:40 %0 = ashr <16 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>41 ret <16 x i8> %042}43 44define arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16(<8 x i16> %a) {45; CHECK-LABEL: test_vshrq_n_s16:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vshr.s16 q0, q0, #1048; CHECK-NEXT: bx lr49entry:50 %0 = ashr <8 x i16> %a, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>51 ret <8 x i16> %052}53 54define arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32(<4 x i32> %a) {55; CHECK-LABEL: test_vshrq_n_s32:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vshr.s32 q0, q0, #1958; CHECK-NEXT: bx lr59entry:60 %0 = ashr <4 x i32> %a, <i32 19, i32 19, i32 19, i32 19>61 ret <4 x i32> %062}63 64define arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8(<16 x i8> %a) {65; CHECK-LABEL: test_vshrq_n_u8:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vshr.u8 q0, q0, #168; CHECK-NEXT: bx lr69entry:70 %0 = lshr <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>71 ret <16 x i8> %072}73 74define arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16(<8 x i16> %a) {75; CHECK-LABEL: test_vshrq_n_u16:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vshr.u16 q0, q0, #1078; CHECK-NEXT: bx lr79entry:80 %0 = lshr <8 x i16> %a, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>81 ret <8 x i16> %082}83 84define arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32(<4 x i32> %a) {85; CHECK-LABEL: test_vshrq_n_u32:86; CHECK: @ %bb.0: @ %entry87; CHECK-NEXT: vshr.u32 q0, q0, #1088; CHECK-NEXT: bx lr89entry:90 %0 = lshr <4 x i32> %a, <i32 10, i32 10, i32 10, i32 10>91 ret <4 x i32> %092}93 94define arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {95; CHECK-LABEL: test_vshlq_m_n_s8:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: vmsr p0, r098; CHECK-NEXT: vpst99; CHECK-NEXT: vshlt.i8 q0, q1, #6100; CHECK-NEXT: bx lr101entry:102 %0 = zext i16 %p to i32103 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)104 %2 = tail call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 6, <16 x i1> %1, <16 x i8> %inactive)105 ret <16 x i8> %2106}107 108define arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_n_s16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {109; CHECK-LABEL: test_vshlq_m_n_s16:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vmsr p0, r0112; CHECK-NEXT: vpst113; CHECK-NEXT: vshlt.i16 q0, q1, #13114; CHECK-NEXT: bx lr115entry:116 %0 = zext i16 %p to i32117 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)118 %2 = tail call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 13, <8 x i1> %1, <8 x i16> %inactive)119 ret <8 x i16> %2120}121 122define arm_aapcs_vfpcc <4 x i32> @test_vshlq_m_n_s32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {123; CHECK-LABEL: test_vshlq_m_n_s32:124; CHECK: @ %bb.0: @ %entry125; CHECK-NEXT: vmsr p0, r0126; CHECK-NEXT: vpst127; CHECK-NEXT: vshlt.i32 q0, q1, #0128; CHECK-NEXT: bx lr129entry:130 %0 = zext i16 %p to i32131 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)132 %2 = tail call <4 x i32> @llvm.arm.mve.shl.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 0, <4 x i1> %1, <4 x i32> %inactive)133 ret <4 x i32> %2134}135 136define arm_aapcs_vfpcc <16 x i8> @test_vshrq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {137; CHECK-LABEL: test_vshrq_m_n_s8:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: vmsr p0, r0140; CHECK-NEXT: vpst141; CHECK-NEXT: vshrt.s8 q0, q1, #2142; CHECK-NEXT: bx lr143entry:144 %0 = zext i16 %p to i32145 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)146 %2 = tail call <16 x i8> @llvm.arm.mve.shr.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 2, i32 0, <16 x i1> %1, <16 x i8> %inactive)147 ret <16 x i8> %2148}149 150define arm_aapcs_vfpcc <8 x i16> @test_vshrq_m_n_s16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {151; CHECK-LABEL: test_vshrq_m_n_s16:152; CHECK: @ %bb.0: @ %entry153; CHECK-NEXT: vmsr p0, r0154; CHECK-NEXT: vpst155; CHECK-NEXT: vshrt.s16 q0, q1, #3156; CHECK-NEXT: bx lr157entry:158 %0 = zext i16 %p to i32159 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)160 %2 = tail call <8 x i16> @llvm.arm.mve.shr.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 3, i32 0, <8 x i1> %1, <8 x i16> %inactive)161 ret <8 x i16> %2162}163 164define arm_aapcs_vfpcc <4 x i32> @test_vshrq_m_n_s32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {165; CHECK-LABEL: test_vshrq_m_n_s32:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: vmsr p0, r0168; CHECK-NEXT: vpst169; CHECK-NEXT: vshrt.s32 q0, q1, #13170; CHECK-NEXT: bx lr171entry:172 %0 = zext i16 %p to i32173 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)174 %2 = tail call <4 x i32> @llvm.arm.mve.shr.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 13, i32 0, <4 x i1> %1, <4 x i32> %inactive)175 ret <4 x i32> %2176}177 178define arm_aapcs_vfpcc <16 x i8> @test_vshrq_m_n_u8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {179; CHECK-LABEL: test_vshrq_m_n_u8:180; CHECK: @ %bb.0: @ %entry181; CHECK-NEXT: vmsr p0, r0182; CHECK-NEXT: vpst183; CHECK-NEXT: vshrt.u8 q0, q1, #4184; CHECK-NEXT: bx lr185entry:186 %0 = zext i16 %p to i32187 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)188 %2 = tail call <16 x i8> @llvm.arm.mve.shr.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 4, i32 1, <16 x i1> %1, <16 x i8> %inactive)189 ret <16 x i8> %2190}191 192define arm_aapcs_vfpcc <8 x i16> @test_vshrq_m_n_u16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {193; CHECK-LABEL: test_vshrq_m_n_u16:194; CHECK: @ %bb.0: @ %entry195; CHECK-NEXT: vmsr p0, r0196; CHECK-NEXT: vpst197; CHECK-NEXT: vshrt.u16 q0, q1, #14198; CHECK-NEXT: bx lr199entry:200 %0 = zext i16 %p to i32201 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)202 %2 = tail call <8 x i16> @llvm.arm.mve.shr.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 14, i32 1, <8 x i1> %1, <8 x i16> %inactive)203 ret <8 x i16> %2204}205 206define arm_aapcs_vfpcc <4 x i32> @test_vshrq_m_n_u32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {207; CHECK-LABEL: test_vshrq_m_n_u32:208; CHECK: @ %bb.0: @ %entry209; CHECK-NEXT: vmsr p0, r0210; CHECK-NEXT: vpst211; CHECK-NEXT: vshrt.u32 q0, q1, #21212; CHECK-NEXT: bx lr213entry:214 %0 = zext i16 %p to i32215 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)216 %2 = tail call <4 x i32> @llvm.arm.mve.shr.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 21, i32 1, <4 x i1> %1, <4 x i32> %inactive)217 ret <4 x i32> %2218}219 220define arm_aapcs_vfpcc <16 x i8> @test_vshlq_x_n_s8(<16 x i8> %a, i16 zeroext %p) {221; CHECK-LABEL: test_vshlq_x_n_s8:222; CHECK: @ %bb.0: @ %entry223; CHECK-NEXT: vmsr p0, r0224; CHECK-NEXT: vpst225; CHECK-NEXT: vshlt.i8 q0, q0, #1226; CHECK-NEXT: bx lr227entry:228 %0 = zext i16 %p to i32229 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)230 %2 = tail call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 1, <16 x i1> %1, <16 x i8> undef)231 ret <16 x i8> %2232}233 234define arm_aapcs_vfpcc <8 x i16> @test_vshlq_x_n_s16(<8 x i16> %a, i16 zeroext %p) {235; CHECK-LABEL: test_vshlq_x_n_s16:236; CHECK: @ %bb.0: @ %entry237; CHECK-NEXT: vmsr p0, r0238; CHECK-NEXT: vpst239; CHECK-NEXT: vshlt.i16 q0, q0, #15240; CHECK-NEXT: bx lr241entry:242 %0 = zext i16 %p to i32243 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)244 %2 = tail call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 15, <8 x i1> %1, <8 x i16> undef)245 ret <8 x i16> %2246}247 248define arm_aapcs_vfpcc <4 x i32> @test_vshlq_x_n_s32(<4 x i32> %a, i16 zeroext %p) {249; CHECK-LABEL: test_vshlq_x_n_s32:250; CHECK: @ %bb.0: @ %entry251; CHECK-NEXT: vmsr p0, r0252; CHECK-NEXT: vpst253; CHECK-NEXT: vshlt.i32 q0, q0, #13254; CHECK-NEXT: bx lr255entry:256 %0 = zext i16 %p to i32257 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)258 %2 = tail call <4 x i32> @llvm.arm.mve.shl.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 13, <4 x i1> %1, <4 x i32> undef)259 ret <4 x i32> %2260}261 262define arm_aapcs_vfpcc <16 x i8> @test_vshlq_x_n_u8(<16 x i8> %a, i16 zeroext %p) {263; CHECK-LABEL: test_vshlq_x_n_u8:264; CHECK: @ %bb.0: @ %entry265; CHECK-NEXT: vmsr p0, r0266; CHECK-NEXT: vpst267; CHECK-NEXT: vshlt.i8 q0, q0, #4268; CHECK-NEXT: bx lr269entry:270 %0 = zext i16 %p to i32271 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)272 %2 = tail call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 4, <16 x i1> %1, <16 x i8> undef)273 ret <16 x i8> %2274}275 276define arm_aapcs_vfpcc <8 x i16> @test_vshlq_x_n_u16(<8 x i16> %a, i16 zeroext %p) {277; CHECK-LABEL: test_vshlq_x_n_u16:278; CHECK: @ %bb.0: @ %entry279; CHECK-NEXT: vmsr p0, r0280; CHECK-NEXT: vpst281; CHECK-NEXT: vshlt.i16 q0, q0, #10282; CHECK-NEXT: bx lr283entry:284 %0 = zext i16 %p to i32285 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)286 %2 = tail call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 10, <8 x i1> %1, <8 x i16> undef)287 ret <8 x i16> %2288}289 290define arm_aapcs_vfpcc <4 x i32> @test_vshlq_x_n_u32(<4 x i32> %a, i16 zeroext %p) {291; CHECK-LABEL: test_vshlq_x_n_u32:292; CHECK: @ %bb.0: @ %entry293; CHECK-NEXT: vmsr p0, r0294; CHECK-NEXT: vpst295; CHECK-NEXT: vshlt.i32 q0, q0, #30296; CHECK-NEXT: bx lr297entry:298 %0 = zext i16 %p to i32299 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)300 %2 = tail call <4 x i32> @llvm.arm.mve.shl.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 30, <4 x i1> %1, <4 x i32> undef)301 ret <4 x i32> %2302}303 304define arm_aapcs_vfpcc <16 x i8> @test_vshrq_x_n_s8(<16 x i8> %a, i16 zeroext %p) {305; CHECK-LABEL: test_vshrq_x_n_s8:306; CHECK: @ %bb.0: @ %entry307; CHECK-NEXT: vmsr p0, r0308; CHECK-NEXT: vpst309; CHECK-NEXT: vshrt.s8 q0, q0, #4310; CHECK-NEXT: bx lr311entry:312 %0 = zext i16 %p to i32313 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)314 %2 = tail call <16 x i8> @llvm.arm.mve.shr.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 4, i32 0, <16 x i1> %1, <16 x i8> undef)315 ret <16 x i8> %2316}317 318define arm_aapcs_vfpcc <8 x i16> @test_vshrq_x_n_s16(<8 x i16> %a, i16 zeroext %p) {319; CHECK-LABEL: test_vshrq_x_n_s16:320; CHECK: @ %bb.0: @ %entry321; CHECK-NEXT: vmsr p0, r0322; CHECK-NEXT: vpst323; CHECK-NEXT: vshrt.s16 q0, q0, #10324; CHECK-NEXT: bx lr325entry:326 %0 = zext i16 %p to i32327 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)328 %2 = tail call <8 x i16> @llvm.arm.mve.shr.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 10, i32 0, <8 x i1> %1, <8 x i16> undef)329 ret <8 x i16> %2330}331 332define arm_aapcs_vfpcc <4 x i32> @test_vshrq_x_n_s32(<4 x i32> %a, i16 zeroext %p) {333; CHECK-LABEL: test_vshrq_x_n_s32:334; CHECK: @ %bb.0: @ %entry335; CHECK-NEXT: vmsr p0, r0336; CHECK-NEXT: vpst337; CHECK-NEXT: vshrt.s32 q0, q0, #7338; CHECK-NEXT: bx lr339entry:340 %0 = zext i16 %p to i32341 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)342 %2 = tail call <4 x i32> @llvm.arm.mve.shr.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 7, i32 0, <4 x i1> %1, <4 x i32> undef)343 ret <4 x i32> %2344}345 346define arm_aapcs_vfpcc <16 x i8> @test_vshrq_x_n_u8(<16 x i8> %a, i16 zeroext %p) {347; CHECK-LABEL: test_vshrq_x_n_u8:348; CHECK: @ %bb.0: @ %entry349; CHECK-NEXT: vmsr p0, r0350; CHECK-NEXT: vpst351; CHECK-NEXT: vshrt.u8 q0, q0, #7352; CHECK-NEXT: bx lr353entry:354 %0 = zext i16 %p to i32355 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)356 %2 = tail call <16 x i8> @llvm.arm.mve.shr.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 7, i32 1, <16 x i1> %1, <16 x i8> undef)357 ret <16 x i8> %2358}359 360define arm_aapcs_vfpcc <8 x i16> @test_vshrq_x_n_u16(<8 x i16> %a, i16 zeroext %p) {361; CHECK-LABEL: test_vshrq_x_n_u16:362; CHECK: @ %bb.0: @ %entry363; CHECK-NEXT: vmsr p0, r0364; CHECK-NEXT: vpst365; CHECK-NEXT: vshrt.u16 q0, q0, #7366; CHECK-NEXT: bx lr367entry:368 %0 = zext i16 %p to i32369 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)370 %2 = tail call <8 x i16> @llvm.arm.mve.shr.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 7, i32 1, <8 x i1> %1, <8 x i16> undef)371 ret <8 x i16> %2372}373 374define arm_aapcs_vfpcc <4 x i32> @test_vshrq_x_n_u32(<4 x i32> %a, i16 zeroext %p) {375; CHECK-LABEL: test_vshrq_x_n_u32:376; CHECK: @ %bb.0: @ %entry377; CHECK-NEXT: vmsr p0, r0378; CHECK-NEXT: vpst379; CHECK-NEXT: vshrt.u32 q0, q0, #6380; CHECK-NEXT: bx lr381entry:382 %0 = zext i16 %p to i32383 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)384 %2 = tail call <4 x i32> @llvm.arm.mve.shr.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 6, i32 1, <4 x i1> %1, <4 x i32> undef)385 ret <4 x i32> %2386}387 388define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_n_s8(<16 x i8> %a) {389; CHECK-LABEL: test_vqshlq_n_s8:390; CHECK: @ %bb.0: @ %entry391; CHECK-NEXT: vqshl.s8 q0, q0, #3392; CHECK-NEXT: bx lr393entry:394 %0 = tail call <16 x i8> @llvm.arm.mve.vqshl.imm.v16i8(<16 x i8> %a, i32 3, i32 0)395 ret <16 x i8> %0396}397 398define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_n_s16(<8 x i16> %a) {399; CHECK-LABEL: test_vqshlq_n_s16:400; CHECK: @ %bb.0: @ %entry401; CHECK-NEXT: vqshl.s16 q0, q0, #4402; CHECK-NEXT: bx lr403entry:404 %0 = tail call <8 x i16> @llvm.arm.mve.vqshl.imm.v8i16(<8 x i16> %a, i32 4, i32 0)405 ret <8 x i16> %0406}407 408define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_n_s32(<4 x i32> %a) {409; CHECK-LABEL: test_vqshlq_n_s32:410; CHECK: @ %bb.0: @ %entry411; CHECK-NEXT: vqshl.s32 q0, q0, #4412; CHECK-NEXT: bx lr413entry:414 %0 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32> %a, i32 4, i32 0)415 ret <4 x i32> %0416}417 418define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_n_u8(<16 x i8> %a) {419; CHECK-LABEL: test_vqshlq_n_u8:420; CHECK: @ %bb.0: @ %entry421; CHECK-NEXT: vqshl.u8 q0, q0, #0422; CHECK-NEXT: bx lr423entry:424 %0 = tail call <16 x i8> @llvm.arm.mve.vqshl.imm.v16i8(<16 x i8> %a, i32 0, i32 1)425 ret <16 x i8> %0426}427 428define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_n_u16(<8 x i16> %a) {429; CHECK-LABEL: test_vqshlq_n_u16:430; CHECK: @ %bb.0: @ %entry431; CHECK-NEXT: vqshl.u16 q0, q0, #13432; CHECK-NEXT: bx lr433entry:434 %0 = tail call <8 x i16> @llvm.arm.mve.vqshl.imm.v8i16(<8 x i16> %a, i32 13, i32 1)435 ret <8 x i16> %0436}437 438define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_n_u32(<4 x i32> %a) {439; CHECK-LABEL: test_vqshlq_n_u32:440; CHECK: @ %bb.0: @ %entry441; CHECK-NEXT: vqshl.u32 q0, q0, #6442; CHECK-NEXT: bx lr443entry:444 %0 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32> %a, i32 6, i32 1)445 ret <4 x i32> %0446}447 448define arm_aapcs_vfpcc <16 x i8> @test_vqshluq_n_s8(<16 x i8> %a) {449; CHECK-LABEL: test_vqshluq_n_s8:450; CHECK: @ %bb.0: @ %entry451; CHECK-NEXT: vqshlu.s8 q0, q0, #5452; CHECK-NEXT: bx lr453entry:454 %0 = tail call <16 x i8> @llvm.arm.mve.vqshlu.imm.v16i8(<16 x i8> %a, i32 5)455 ret <16 x i8> %0456}457 458define arm_aapcs_vfpcc <8 x i16> @test_vqshluq_n_s16(<8 x i16> %a) {459; CHECK-LABEL: test_vqshluq_n_s16:460; CHECK: @ %bb.0: @ %entry461; CHECK-NEXT: vqshlu.s16 q0, q0, #5462; CHECK-NEXT: bx lr463entry:464 %0 = tail call <8 x i16> @llvm.arm.mve.vqshlu.imm.v8i16(<8 x i16> %a, i32 5)465 ret <8 x i16> %0466}467 468define arm_aapcs_vfpcc <4 x i32> @test_vqshluq_n_s32(<4 x i32> %a) {469; CHECK-LABEL: test_vqshluq_n_s32:470; CHECK: @ %bb.0: @ %entry471; CHECK-NEXT: vqshlu.s32 q0, q0, #4472; CHECK-NEXT: bx lr473entry:474 %0 = tail call <4 x i32> @llvm.arm.mve.vqshlu.imm.v4i32(<4 x i32> %a, i32 4)475 ret <4 x i32> %0476}477 478define arm_aapcs_vfpcc <16 x i8> @test_vrshrq_n_s8(<16 x i8> %a) {479; CHECK-LABEL: test_vrshrq_n_s8:480; CHECK: @ %bb.0: @ %entry481; CHECK-NEXT: vrshr.s8 q0, q0, #4482; CHECK-NEXT: bx lr483entry:484 %0 = tail call <16 x i8> @llvm.arm.mve.vrshr.imm.v16i8(<16 x i8> %a, i32 4, i32 0)485 ret <16 x i8> %0486}487 488define arm_aapcs_vfpcc <8 x i16> @test_vrshrq_n_s16(<8 x i16> %a) {489; CHECK-LABEL: test_vrshrq_n_s16:490; CHECK: @ %bb.0: @ %entry491; CHECK-NEXT: vrshr.s16 q0, q0, #12492; CHECK-NEXT: bx lr493entry:494 %0 = tail call <8 x i16> @llvm.arm.mve.vrshr.imm.v8i16(<8 x i16> %a, i32 12, i32 0)495 ret <8 x i16> %0496}497 498define arm_aapcs_vfpcc <4 x i32> @test_vrshrq_n_s32(<4 x i32> %a) {499; CHECK-LABEL: test_vrshrq_n_s32:500; CHECK: @ %bb.0: @ %entry501; CHECK-NEXT: vrshr.s32 q0, q0, #30502; CHECK-NEXT: bx lr503entry:504 %0 = tail call <4 x i32> @llvm.arm.mve.vrshr.imm.v4i32(<4 x i32> %a, i32 30, i32 0)505 ret <4 x i32> %0506}507 508define arm_aapcs_vfpcc <16 x i8> @test_vrshrq_n_u8(<16 x i8> %a) {509; CHECK-LABEL: test_vrshrq_n_u8:510; CHECK: @ %bb.0: @ %entry511; CHECK-NEXT: vrshr.u8 q0, q0, #1512; CHECK-NEXT: bx lr513entry:514 %0 = tail call <16 x i8> @llvm.arm.mve.vrshr.imm.v16i8(<16 x i8> %a, i32 1, i32 1)515 ret <16 x i8> %0516}517 518define arm_aapcs_vfpcc <8 x i16> @test_vrshrq_n_u16(<8 x i16> %a) {519; CHECK-LABEL: test_vrshrq_n_u16:520; CHECK: @ %bb.0: @ %entry521; CHECK-NEXT: vrshr.u16 q0, q0, #15522; CHECK-NEXT: bx lr523entry:524 %0 = tail call <8 x i16> @llvm.arm.mve.vrshr.imm.v8i16(<8 x i16> %a, i32 15, i32 1)525 ret <8 x i16> %0526}527 528define arm_aapcs_vfpcc <4 x i32> @test_vrshrq_n_u32(<4 x i32> %a) {529; CHECK-LABEL: test_vrshrq_n_u32:530; CHECK: @ %bb.0: @ %entry531; CHECK-NEXT: vrshr.u32 q0, q0, #20532; CHECK-NEXT: bx lr533entry:534 %0 = tail call <4 x i32> @llvm.arm.mve.vrshr.imm.v4i32(<4 x i32> %a, i32 20, i32 1)535 ret <4 x i32> %0536}537 538define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {539; CHECK-LABEL: test_vqshlq_m_n_s8:540; CHECK: @ %bb.0: @ %entry541; CHECK-NEXT: vmsr p0, r0542; CHECK-NEXT: vpst543; CHECK-NEXT: vqshlt.s8 q0, q1, #6544; CHECK-NEXT: bx lr545entry:546 %0 = zext i16 %p to i32547 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)548 %2 = tail call <16 x i8> @llvm.arm.mve.vqshl.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 6, i32 0, <16 x i1> %1, <16 x i8> %inactive)549 ret <16 x i8> %2550}551 552define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_m_n_s16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {553; CHECK-LABEL: test_vqshlq_m_n_s16:554; CHECK: @ %bb.0: @ %entry555; CHECK-NEXT: vmsr p0, r0556; CHECK-NEXT: vpst557; CHECK-NEXT: vqshlt.s16 q0, q1, #13558; CHECK-NEXT: bx lr559entry:560 %0 = zext i16 %p to i32561 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)562 %2 = tail call <8 x i16> @llvm.arm.mve.vqshl.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 13, i32 0, <8 x i1> %1, <8 x i16> %inactive)563 ret <8 x i16> %2564}565 566define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_m_n_s32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {567; CHECK-LABEL: test_vqshlq_m_n_s32:568; CHECK: @ %bb.0: @ %entry569; CHECK-NEXT: vmsr p0, r0570; CHECK-NEXT: vpst571; CHECK-NEXT: vqshlt.s32 q0, q1, #14572; CHECK-NEXT: bx lr573entry:574 %0 = zext i16 %p to i32575 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)576 %2 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 14, i32 0, <4 x i1> %1, <4 x i32> %inactive)577 ret <4 x i32> %2578}579 580define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_m_n_u8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {581; CHECK-LABEL: test_vqshlq_m_n_u8:582; CHECK: @ %bb.0: @ %entry583; CHECK-NEXT: vmsr p0, r0584; CHECK-NEXT: vpst585; CHECK-NEXT: vqshlt.u8 q0, q1, #4586; CHECK-NEXT: bx lr587entry:588 %0 = zext i16 %p to i32589 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)590 %2 = tail call <16 x i8> @llvm.arm.mve.vqshl.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 4, i32 1, <16 x i1> %1, <16 x i8> %inactive)591 ret <16 x i8> %2592}593 594define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_m_n_u16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {595; CHECK-LABEL: test_vqshlq_m_n_u16:596; CHECK: @ %bb.0: @ %entry597; CHECK-NEXT: vmsr p0, r0598; CHECK-NEXT: vpst599; CHECK-NEXT: vqshlt.u16 q0, q1, #9600; CHECK-NEXT: bx lr601entry:602 %0 = zext i16 %p to i32603 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)604 %2 = tail call <8 x i16> @llvm.arm.mve.vqshl.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 9, i32 1, <8 x i1> %1, <8 x i16> %inactive)605 ret <8 x i16> %2606}607 608define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_m_n_u32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {609; CHECK-LABEL: test_vqshlq_m_n_u32:610; CHECK: @ %bb.0: @ %entry611; CHECK-NEXT: vmsr p0, r0612; CHECK-NEXT: vpst613; CHECK-NEXT: vqshlt.u32 q0, q1, #25614; CHECK-NEXT: bx lr615entry:616 %0 = zext i16 %p to i32617 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)618 %2 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 25, i32 1, <4 x i1> %1, <4 x i32> %inactive)619 ret <4 x i32> %2620}621 622define arm_aapcs_vfpcc <16 x i8> @test_vqshluq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {623; CHECK-LABEL: test_vqshluq_m_n_s8:624; CHECK: @ %bb.0: @ %entry625; CHECK-NEXT: vmsr p0, r0626; CHECK-NEXT: vpst627; CHECK-NEXT: vqshlut.s8 q0, q1, #2628; CHECK-NEXT: bx lr629entry:630 %0 = zext i16 %p to i32631 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)632 %2 = tail call <16 x i8> @llvm.arm.mve.vqshlu.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 2, <16 x i1> %1, <16 x i8> %inactive)633 ret <16 x i8> %2634}635 636define arm_aapcs_vfpcc <8 x i16> @test_vqshluq_m_n_s16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {637; CHECK-LABEL: test_vqshluq_m_n_s16:638; CHECK: @ %bb.0: @ %entry639; CHECK-NEXT: vmsr p0, r0640; CHECK-NEXT: vpst641; CHECK-NEXT: vqshlut.s16 q0, q1, #12642; CHECK-NEXT: bx lr643entry:644 %0 = zext i16 %p to i32645 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)646 %2 = tail call <8 x i16> @llvm.arm.mve.vqshlu.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 12, <8 x i1> %1, <8 x i16> %inactive)647 ret <8 x i16> %2648}649 650define arm_aapcs_vfpcc <4 x i32> @test_vqshluq_m_n_s32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {651; CHECK-LABEL: test_vqshluq_m_n_s32:652; CHECK: @ %bb.0: @ %entry653; CHECK-NEXT: vmsr p0, r0654; CHECK-NEXT: vpst655; CHECK-NEXT: vqshlut.s32 q0, q1, #24656; CHECK-NEXT: bx lr657entry:658 %0 = zext i16 %p to i32659 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)660 %2 = tail call <4 x i32> @llvm.arm.mve.vqshlu.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 24, <4 x i1> %1, <4 x i32> %inactive)661 ret <4 x i32> %2662}663 664define arm_aapcs_vfpcc <16 x i8> @test_vrshrq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {665; CHECK-LABEL: test_vrshrq_m_n_s8:666; CHECK: @ %bb.0: @ %entry667; CHECK-NEXT: vmsr p0, r0668; CHECK-NEXT: vpst669; CHECK-NEXT: vrshrt.s8 q0, q1, #2670; CHECK-NEXT: bx lr671entry:672 %0 = zext i16 %p to i32673 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)674 %2 = tail call <16 x i8> @llvm.arm.mve.vrshr.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 2, i32 0, <16 x i1> %1, <16 x i8> %inactive)675 ret <16 x i8> %2676}677 678define arm_aapcs_vfpcc <8 x i16> @test_vrshrq_m_n_s16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {679; CHECK-LABEL: test_vrshrq_m_n_s16:680; CHECK: @ %bb.0: @ %entry681; CHECK-NEXT: vmsr p0, r0682; CHECK-NEXT: vpst683; CHECK-NEXT: vrshrt.s16 q0, q1, #11684; CHECK-NEXT: bx lr685entry:686 %0 = zext i16 %p to i32687 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)688 %2 = tail call <8 x i16> @llvm.arm.mve.vrshr.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 11, i32 0, <8 x i1> %1, <8 x i16> %inactive)689 ret <8 x i16> %2690}691 692define arm_aapcs_vfpcc <4 x i32> @test_vrshrq_m_n_s32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {693; CHECK-LABEL: test_vrshrq_m_n_s32:694; CHECK: @ %bb.0: @ %entry695; CHECK-NEXT: vmsr p0, r0696; CHECK-NEXT: vpst697; CHECK-NEXT: vrshrt.s32 q0, q1, #24698; CHECK-NEXT: bx lr699entry:700 %0 = zext i16 %p to i32701 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)702 %2 = tail call <4 x i32> @llvm.arm.mve.vrshr.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 24, i32 0, <4 x i1> %1, <4 x i32> %inactive)703 ret <4 x i32> %2704}705 706define arm_aapcs_vfpcc <16 x i8> @test_vrshrq_m_n_u8(<16 x i8> %inactive, <16 x i8> %a, i16 zeroext %p) {707; CHECK-LABEL: test_vrshrq_m_n_u8:708; CHECK: @ %bb.0: @ %entry709; CHECK-NEXT: vmsr p0, r0710; CHECK-NEXT: vpst711; CHECK-NEXT: vrshrt.u8 q0, q1, #7712; CHECK-NEXT: bx lr713entry:714 %0 = zext i16 %p to i32715 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)716 %2 = tail call <16 x i8> @llvm.arm.mve.vrshr.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 7, i32 1, <16 x i1> %1, <16 x i8> %inactive)717 ret <16 x i8> %2718}719 720define arm_aapcs_vfpcc <8 x i16> @test_vrshrq_m_n_u16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %p) {721; CHECK-LABEL: test_vrshrq_m_n_u16:722; CHECK: @ %bb.0: @ %entry723; CHECK-NEXT: vmsr p0, r0724; CHECK-NEXT: vpst725; CHECK-NEXT: vrshrt.u16 q0, q1, #4726; CHECK-NEXT: bx lr727entry:728 %0 = zext i16 %p to i32729 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)730 %2 = tail call <8 x i16> @llvm.arm.mve.vrshr.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 4, i32 1, <8 x i1> %1, <8 x i16> %inactive)731 ret <8 x i16> %2732}733 734define arm_aapcs_vfpcc <4 x i32> @test_vrshrq_m_n_u32(<4 x i32> %inactive, <4 x i32> %a, i16 zeroext %p) {735; CHECK-LABEL: test_vrshrq_m_n_u32:736; CHECK: @ %bb.0: @ %entry737; CHECK-NEXT: vmsr p0, r0738; CHECK-NEXT: vpst739; CHECK-NEXT: vrshrt.u32 q0, q1, #27740; CHECK-NEXT: bx lr741entry:742 %0 = zext i16 %p to i32743 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)744 %2 = tail call <4 x i32> @llvm.arm.mve.vrshr.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 27, i32 1, <4 x i1> %1, <4 x i32> %inactive)745 ret <4 x i32> %2746}747 748define arm_aapcs_vfpcc <16 x i8> @test_vrshrq_x_n_s8(<16 x i8> %a, i16 zeroext %p) {749; CHECK-LABEL: test_vrshrq_x_n_s8:750; CHECK: @ %bb.0: @ %entry751; CHECK-NEXT: vmsr p0, r0752; CHECK-NEXT: vpst753; CHECK-NEXT: vrshrt.s8 q0, q0, #3754; CHECK-NEXT: bx lr755entry:756 %0 = zext i16 %p to i32757 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)758 %2 = tail call <16 x i8> @llvm.arm.mve.vrshr.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 3, i32 0, <16 x i1> %1, <16 x i8> undef)759 ret <16 x i8> %2760}761 762define arm_aapcs_vfpcc <8 x i16> @test_vrshrq_x_n_s16(<8 x i16> %a, i16 zeroext %p) {763; CHECK-LABEL: test_vrshrq_x_n_s16:764; CHECK: @ %bb.0: @ %entry765; CHECK-NEXT: vmsr p0, r0766; CHECK-NEXT: vpst767; CHECK-NEXT: vrshrt.s16 q0, q0, #12768; CHECK-NEXT: bx lr769entry:770 %0 = zext i16 %p to i32771 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)772 %2 = tail call <8 x i16> @llvm.arm.mve.vrshr.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 12, i32 0, <8 x i1> %1, <8 x i16> undef)773 ret <8 x i16> %2774}775 776define arm_aapcs_vfpcc <4 x i32> @test_vrshrq_x_n_s32(<4 x i32> %a, i16 zeroext %p) {777; CHECK-LABEL: test_vrshrq_x_n_s32:778; CHECK: @ %bb.0: @ %entry779; CHECK-NEXT: vmsr p0, r0780; CHECK-NEXT: vpst781; CHECK-NEXT: vrshrt.s32 q0, q0, #20782; CHECK-NEXT: bx lr783entry:784 %0 = zext i16 %p to i32785 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)786 %2 = tail call <4 x i32> @llvm.arm.mve.vrshr.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 20, i32 0, <4 x i1> %1, <4 x i32> undef)787 ret <4 x i32> %2788}789 790define arm_aapcs_vfpcc <16 x i8> @test_vrshrq_x_n_u8(<16 x i8> %a, i16 zeroext %p) {791; CHECK-LABEL: test_vrshrq_x_n_u8:792; CHECK: @ %bb.0: @ %entry793; CHECK-NEXT: vmsr p0, r0794; CHECK-NEXT: vpst795; CHECK-NEXT: vrshrt.u8 q0, q0, #1796; CHECK-NEXT: bx lr797entry:798 %0 = zext i16 %p to i32799 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)800 %2 = tail call <16 x i8> @llvm.arm.mve.vrshr.imm.predicated.v16i8.v16i1(<16 x i8> %a, i32 1, i32 1, <16 x i1> %1, <16 x i8> undef)801 ret <16 x i8> %2802}803 804define arm_aapcs_vfpcc <8 x i16> @test_vrshrq_x_n_u16(<8 x i16> %a, i16 zeroext %p) {805; CHECK-LABEL: test_vrshrq_x_n_u16:806; CHECK: @ %bb.0: @ %entry807; CHECK-NEXT: vmsr p0, r0808; CHECK-NEXT: vpst809; CHECK-NEXT: vrshrt.u16 q0, q0, #13810; CHECK-NEXT: bx lr811entry:812 %0 = zext i16 %p to i32813 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)814 %2 = tail call <8 x i16> @llvm.arm.mve.vrshr.imm.predicated.v8i16.v8i1(<8 x i16> %a, i32 13, i32 1, <8 x i1> %1, <8 x i16> undef)815 ret <8 x i16> %2816}817 818define arm_aapcs_vfpcc <4 x i32> @test_vrshrq_x_n_u32(<4 x i32> %a, i16 zeroext %p) {819; CHECK-LABEL: test_vrshrq_x_n_u32:820; CHECK: @ %bb.0: @ %entry821; CHECK-NEXT: vmsr p0, r0822; CHECK-NEXT: vpst823; CHECK-NEXT: vrshrt.u32 q0, q0, #6824; CHECK-NEXT: bx lr825entry:826 %0 = zext i16 %p to i32827 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)828 %2 = tail call <4 x i32> @llvm.arm.mve.vrshr.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 6, i32 1, <4 x i1> %1, <4 x i32> undef)829 ret <4 x i32> %2830}831 832define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_n_s8(<16 x i8> %a) {833; CHECK-LABEL: test_vshllbq_n_s8:834; CHECK: @ %bb.0: @ %entry835; CHECK-NEXT: vshllb.s8 q0, q0, #2836; CHECK-NEXT: bx lr837entry:838 %0 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.v8i16.v16i8(<16 x i8> %a, i32 2, i32 0, i32 0)839 ret <8 x i16> %0840}841 842define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_n_s8_lanewidth(<16 x i8> %a) {843; CHECK-LABEL: test_vshllbq_n_s8_lanewidth:844; CHECK: @ %bb.0: @ %entry845; CHECK-NEXT: vshllb.s8 q0, q0, #8846; CHECK-NEXT: bx lr847entry:848 %0 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.v8i16.v16i8(<16 x i8> %a, i32 8, i32 0, i32 0)849 ret <8 x i16> %0850}851 852define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_n_s16(<8 x i16> %a) {853; CHECK-LABEL: test_vshllbq_n_s16:854; CHECK: @ %bb.0: @ %entry855; CHECK-NEXT: vshllb.s16 q0, q0, #13856; CHECK-NEXT: bx lr857entry:858 %0 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.v4i32.v8i16(<8 x i16> %a, i32 13, i32 0, i32 0)859 ret <4 x i32> %0860}861 862define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_n_s16_lanewidth(<8 x i16> %a) {863; CHECK-LABEL: test_vshllbq_n_s16_lanewidth:864; CHECK: @ %bb.0: @ %entry865; CHECK-NEXT: vshllb.s16 q0, q0, #16866; CHECK-NEXT: bx lr867entry:868 %0 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.v4i32.v8i16(<8 x i16> %a, i32 16, i32 0, i32 0)869 ret <4 x i32> %0870}871 872define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_n_u8(<16 x i8> %a) {873; CHECK-LABEL: test_vshllbq_n_u8:874; CHECK: @ %bb.0: @ %entry875; CHECK-NEXT: vshllb.u8 q0, q0, #5876; CHECK-NEXT: bx lr877entry:878 %0 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.v8i16.v16i8(<16 x i8> %a, i32 5, i32 1, i32 0)879 ret <8 x i16> %0880}881 882define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_n_u8_lanewidth(<16 x i8> %a) {883; CHECK-LABEL: test_vshllbq_n_u8_lanewidth:884; CHECK: @ %bb.0: @ %entry885; CHECK-NEXT: vshllb.u8 q0, q0, #8886; CHECK-NEXT: bx lr887entry:888 %0 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.v8i16.v16i8(<16 x i8> %a, i32 8, i32 1, i32 0)889 ret <8 x i16> %0890}891 892define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_n_u16(<8 x i16> %a) {893; CHECK-LABEL: test_vshllbq_n_u16:894; CHECK: @ %bb.0: @ %entry895; CHECK-NEXT: vshllb.u16 q0, q0, #6896; CHECK-NEXT: bx lr897entry:898 %0 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.v4i32.v8i16(<8 x i16> %a, i32 6, i32 1, i32 0)899 ret <4 x i32> %0900}901 902define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_n_u16_lanewidth(<8 x i16> %a) {903; CHECK-LABEL: test_vshllbq_n_u16_lanewidth:904; CHECK: @ %bb.0: @ %entry905; CHECK-NEXT: vshllb.u16 q0, q0, #16906; CHECK-NEXT: bx lr907entry:908 %0 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.v4i32.v8i16(<8 x i16> %a, i32 16, i32 1, i32 0)909 ret <4 x i32> %0910}911 912define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_n_s8(<16 x i8> %a) {913; CHECK-LABEL: test_vshlltq_n_s8:914; CHECK: @ %bb.0: @ %entry915; CHECK-NEXT: vshllt.s8 q0, q0, #7916; CHECK-NEXT: bx lr917entry:918 %0 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.v8i16.v16i8(<16 x i8> %a, i32 7, i32 0, i32 1)919 ret <8 x i16> %0920}921 922define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_n_s8_lanewidth(<16 x i8> %a) {923; CHECK-LABEL: test_vshlltq_n_s8_lanewidth:924; CHECK: @ %bb.0: @ %entry925; CHECK-NEXT: vshllt.s8 q0, q0, #8926; CHECK-NEXT: bx lr927entry:928 %0 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.v8i16.v16i8(<16 x i8> %a, i32 8, i32 0, i32 1)929 ret <8 x i16> %0930}931 932define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_n_s16(<8 x i16> %a) {933; CHECK-LABEL: test_vshlltq_n_s16:934; CHECK: @ %bb.0: @ %entry935; CHECK-NEXT: vshllt.s16 q0, q0, #2936; CHECK-NEXT: bx lr937entry:938 %0 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.v4i32.v8i16(<8 x i16> %a, i32 2, i32 0, i32 1)939 ret <4 x i32> %0940}941 942define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_n_s16_lanewidth(<8 x i16> %a) {943; CHECK-LABEL: test_vshlltq_n_s16_lanewidth:944; CHECK: @ %bb.0: @ %entry945; CHECK-NEXT: vshllt.s16 q0, q0, #16946; CHECK-NEXT: bx lr947entry:948 %0 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.v4i32.v8i16(<8 x i16> %a, i32 16, i32 0, i32 1)949 ret <4 x i32> %0950}951 952define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_n_u8(<16 x i8> %a) {953; CHECK-LABEL: test_vshlltq_n_u8:954; CHECK: @ %bb.0: @ %entry955; CHECK-NEXT: vshllt.u8 q0, q0, #7956; CHECK-NEXT: bx lr957entry:958 %0 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.v8i16.v16i8(<16 x i8> %a, i32 7, i32 1, i32 1)959 ret <8 x i16> %0960}961 962define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_n_u8_lanewidth(<16 x i8> %a) {963; CHECK-LABEL: test_vshlltq_n_u8_lanewidth:964; CHECK: @ %bb.0: @ %entry965; CHECK-NEXT: vshllt.u8 q0, q0, #8966; CHECK-NEXT: bx lr967entry:968 %0 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.v8i16.v16i8(<16 x i8> %a, i32 8, i32 1, i32 1)969 ret <8 x i16> %0970}971 972define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_n_u16(<8 x i16> %a) {973; CHECK-LABEL: test_vshlltq_n_u16:974; CHECK: @ %bb.0: @ %entry975; CHECK-NEXT: vshllt.u16 q0, q0, #14976; CHECK-NEXT: bx lr977entry:978 %0 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.v4i32.v8i16(<8 x i16> %a, i32 14, i32 1, i32 1)979 ret <4 x i32> %0980}981 982define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_n_u16_lanewidth(<8 x i16> %a) {983; CHECK-LABEL: test_vshlltq_n_u16_lanewidth:984; CHECK: @ %bb.0: @ %entry985; CHECK-NEXT: vshllt.u16 q0, q0, #16986; CHECK-NEXT: bx lr987entry:988 %0 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.v4i32.v8i16(<8 x i16> %a, i32 16, i32 1, i32 1)989 ret <4 x i32> %0990}991 992define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_m_n_s8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {993; CHECK-LABEL: test_vshllbq_m_n_s8:994; CHECK: @ %bb.0: @ %entry995; CHECK-NEXT: vmsr p0, r0996; CHECK-NEXT: vpst997; CHECK-NEXT: vshllbt.s8 q0, q1, #6998; CHECK-NEXT: bx lr999entry:1000 %0 = zext i16 %p to i321001 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1002 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 6, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive)1003 ret <8 x i16> %21004}1005 1006define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_m_n_s8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {1007; CHECK-LABEL: test_vshllbq_m_n_s8_lanewidth:1008; CHECK: @ %bb.0: @ %entry1009; CHECK-NEXT: vmsr p0, r01010; CHECK-NEXT: vpst1011; CHECK-NEXT: vshllbt.s8 q0, q1, #81012; CHECK-NEXT: bx lr1013entry:1014 %0 = zext i16 %p to i321015 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1016 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive)1017 ret <8 x i16> %21018}1019 1020define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_s16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {1021; CHECK-LABEL: test_vshllbq_m_n_s16:1022; CHECK: @ %bb.0: @ %entry1023; CHECK-NEXT: vmsr p0, r01024; CHECK-NEXT: vpst1025; CHECK-NEXT: vshllbt.s16 q0, q1, #101026; CHECK-NEXT: bx lr1027entry:1028 %0 = zext i16 %p to i321029 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1030 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 10, i32 0, i32 0, <4 x i1> %1, <4 x i32> %inactive)1031 ret <4 x i32> %21032}1033 1034define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_s16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {1035; CHECK-LABEL: test_vshllbq_m_n_s16_lanewidth:1036; CHECK: @ %bb.0: @ %entry1037; CHECK-NEXT: vmsr p0, r01038; CHECK-NEXT: vpst1039; CHECK-NEXT: vshllbt.s16 q0, q1, #161040; CHECK-NEXT: bx lr1041entry:1042 %0 = zext i16 %p to i321043 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1044 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 0, i32 0, <4 x i1> %1, <4 x i32> %inactive)1045 ret <4 x i32> %21046}1047 1048define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_m_n_u8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {1049; CHECK-LABEL: test_vshllbq_m_n_u8:1050; CHECK: @ %bb.0: @ %entry1051; CHECK-NEXT: vmsr p0, r01052; CHECK-NEXT: vpst1053; CHECK-NEXT: vshllbt.u8 q0, q1, #31054; CHECK-NEXT: bx lr1055entry:1056 %0 = zext i16 %p to i321057 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1058 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 3, i32 1, i32 0, <8 x i1> %1, <8 x i16> %inactive)1059 ret <8 x i16> %21060}1061 1062define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_m_n_u8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {1063; CHECK-LABEL: test_vshllbq_m_n_u8_lanewidth:1064; CHECK: @ %bb.0: @ %entry1065; CHECK-NEXT: vmsr p0, r01066; CHECK-NEXT: vpst1067; CHECK-NEXT: vshllbt.u8 q0, q1, #81068; CHECK-NEXT: bx lr1069entry:1070 %0 = zext i16 %p to i321071 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1072 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 1, i32 0, <8 x i1> %1, <8 x i16> %inactive)1073 ret <8 x i16> %21074}1075 1076define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_u16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {1077; CHECK-LABEL: test_vshllbq_m_n_u16:1078; CHECK: @ %bb.0: @ %entry1079; CHECK-NEXT: vmsr p0, r01080; CHECK-NEXT: vpst1081; CHECK-NEXT: vshllbt.u16 q0, q1, #141082; CHECK-NEXT: bx lr1083entry:1084 %0 = zext i16 %p to i321085 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1086 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 14, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive)1087 ret <4 x i32> %21088}1089 1090define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_u16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {1091; CHECK-LABEL: test_vshllbq_m_n_u16_lanewidth:1092; CHECK: @ %bb.0: @ %entry1093; CHECK-NEXT: vmsr p0, r01094; CHECK-NEXT: vpst1095; CHECK-NEXT: vshllbt.u16 q0, q1, #161096; CHECK-NEXT: bx lr1097entry:1098 %0 = zext i16 %p to i321099 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1100 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive)1101 ret <4 x i32> %21102}1103 1104define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_s8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {1105; CHECK-LABEL: test_vshlltq_m_n_s8:1106; CHECK: @ %bb.0: @ %entry1107; CHECK-NEXT: vmsr p0, r01108; CHECK-NEXT: vpst1109; CHECK-NEXT: vshlltt.s8 q0, q1, #41110; CHECK-NEXT: bx lr1111entry:1112 %0 = zext i16 %p to i321113 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1114 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 4, i32 0, i32 1, <8 x i1> %1, <8 x i16> %inactive)1115 ret <8 x i16> %21116}1117 1118define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_s8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {1119; CHECK-LABEL: test_vshlltq_m_n_s8_lanewidth:1120; CHECK: @ %bb.0: @ %entry1121; CHECK-NEXT: vmsr p0, r01122; CHECK-NEXT: vpst1123; CHECK-NEXT: vshlltt.s8 q0, q1, #81124; CHECK-NEXT: bx lr1125entry:1126 %0 = zext i16 %p to i321127 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1128 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 0, i32 1, <8 x i1> %1, <8 x i16> %inactive)1129 ret <8 x i16> %21130}1131 1132define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_s16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {1133; CHECK-LABEL: test_vshlltq_m_n_s16:1134; CHECK: @ %bb.0: @ %entry1135; CHECK-NEXT: vmsr p0, r01136; CHECK-NEXT: vpst1137; CHECK-NEXT: vshlltt.s16 q0, q1, #121138; CHECK-NEXT: bx lr1139entry:1140 %0 = zext i16 %p to i321141 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1142 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 12, i32 0, i32 1, <4 x i1> %1, <4 x i32> %inactive)1143 ret <4 x i32> %21144}1145 1146define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_s16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {1147; CHECK-LABEL: test_vshlltq_m_n_s16_lanewidth:1148; CHECK: @ %bb.0: @ %entry1149; CHECK-NEXT: vmsr p0, r01150; CHECK-NEXT: vpst1151; CHECK-NEXT: vshlltt.s16 q0, q1, #161152; CHECK-NEXT: bx lr1153entry:1154 %0 = zext i16 %p to i321155 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1156 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 0, i32 1, <4 x i1> %1, <4 x i32> %inactive)1157 ret <4 x i32> %21158}1159 1160define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_u8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {1161; CHECK-LABEL: test_vshlltq_m_n_u8:1162; CHECK: @ %bb.0: @ %entry1163; CHECK-NEXT: vmsr p0, r01164; CHECK-NEXT: vpst1165; CHECK-NEXT: vshlltt.u8 q0, q1, #21166; CHECK-NEXT: bx lr1167entry:1168 %0 = zext i16 %p to i321169 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1170 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 2, i32 1, i32 1, <8 x i1> %1, <8 x i16> %inactive)1171 ret <8 x i16> %21172}1173 1174define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_u8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {1175; CHECK-LABEL: test_vshlltq_m_n_u8_lanewidth:1176; CHECK: @ %bb.0: @ %entry1177; CHECK-NEXT: vmsr p0, r01178; CHECK-NEXT: vpst1179; CHECK-NEXT: vshlltt.u8 q0, q1, #81180; CHECK-NEXT: bx lr1181entry:1182 %0 = zext i16 %p to i321183 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1184 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 1, i32 1, <8 x i1> %1, <8 x i16> %inactive)1185 ret <8 x i16> %21186}1187 1188define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_u16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {1189; CHECK-LABEL: test_vshlltq_m_n_u16:1190; CHECK: @ %bb.0: @ %entry1191; CHECK-NEXT: vmsr p0, r01192; CHECK-NEXT: vpst1193; CHECK-NEXT: vshlltt.u16 q0, q1, #91194; CHECK-NEXT: bx lr1195entry:1196 %0 = zext i16 %p to i321197 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1198 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 9, i32 1, i32 1, <4 x i1> %1, <4 x i32> %inactive)1199 ret <4 x i32> %21200}1201 1202define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_u16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {1203; CHECK-LABEL: test_vshlltq_m_n_u16_lanewidth:1204; CHECK: @ %bb.0: @ %entry1205; CHECK-NEXT: vmsr p0, r01206; CHECK-NEXT: vpst1207; CHECK-NEXT: vshlltt.u16 q0, q1, #161208; CHECK-NEXT: bx lr1209entry:1210 %0 = zext i16 %p to i321211 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1212 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 1, i32 1, <4 x i1> %1, <4 x i32> %inactive)1213 ret <4 x i32> %21214}1215 1216define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_s8(<16 x i8> %a, i16 zeroext %p) {1217; CHECK-LABEL: test_vshllbq_x_n_s8:1218; CHECK: @ %bb.0: @ %entry1219; CHECK-NEXT: vmsr p0, r01220; CHECK-NEXT: vpst1221; CHECK-NEXT: vshllbt.s8 q0, q0, #11222; CHECK-NEXT: bx lr1223entry:1224 %0 = zext i16 %p to i321225 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1226 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 1, i32 0, i32 0, <8 x i1> %1, <8 x i16> undef)1227 ret <8 x i16> %21228}1229 1230define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_s8_lanewidth(<16 x i8> %a, i16 zeroext %p) {1231; CHECK-LABEL: test_vshllbq_x_n_s8_lanewidth:1232; CHECK: @ %bb.0: @ %entry1233; CHECK-NEXT: vmsr p0, r01234; CHECK-NEXT: vpst1235; CHECK-NEXT: vshllbt.s8 q0, q0, #81236; CHECK-NEXT: bx lr1237entry:1238 %0 = zext i16 %p to i321239 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1240 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 0, i32 0, <8 x i1> %1, <8 x i16> undef)1241 ret <8 x i16> %21242}1243 1244define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_s16(<8 x i16> %a, i16 zeroext %p) {1245; CHECK-LABEL: test_vshllbq_x_n_s16:1246; CHECK: @ %bb.0: @ %entry1247; CHECK-NEXT: vmsr p0, r01248; CHECK-NEXT: vpst1249; CHECK-NEXT: vshllbt.s16 q0, q0, #101250; CHECK-NEXT: bx lr1251entry:1252 %0 = zext i16 %p to i321253 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1254 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 10, i32 0, i32 0, <4 x i1> %1, <4 x i32> undef)1255 ret <4 x i32> %21256}1257 1258define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_s16_lanewidth(<8 x i16> %a, i16 zeroext %p) {1259; CHECK-LABEL: test_vshllbq_x_n_s16_lanewidth:1260; CHECK: @ %bb.0: @ %entry1261; CHECK-NEXT: vmsr p0, r01262; CHECK-NEXT: vpst1263; CHECK-NEXT: vshllbt.s16 q0, q0, #161264; CHECK-NEXT: bx lr1265entry:1266 %0 = zext i16 %p to i321267 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1268 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 0, i32 0, <4 x i1> %1, <4 x i32> undef)1269 ret <4 x i32> %21270}1271 1272define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_u8(<16 x i8> %a, i16 zeroext %p) {1273; CHECK-LABEL: test_vshllbq_x_n_u8:1274; CHECK: @ %bb.0: @ %entry1275; CHECK-NEXT: vmsr p0, r01276; CHECK-NEXT: vpst1277; CHECK-NEXT: vshllbt.u8 q0, q0, #61278; CHECK-NEXT: bx lr1279entry:1280 %0 = zext i16 %p to i321281 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1282 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 6, i32 1, i32 0, <8 x i1> %1, <8 x i16> undef)1283 ret <8 x i16> %21284}1285 1286define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_u8_lanewidth(<16 x i8> %a, i16 zeroext %p) {1287; CHECK-LABEL: test_vshllbq_x_n_u8_lanewidth:1288; CHECK: @ %bb.0: @ %entry1289; CHECK-NEXT: vmsr p0, r01290; CHECK-NEXT: vpst1291; CHECK-NEXT: vshllbt.u8 q0, q0, #81292; CHECK-NEXT: bx lr1293entry:1294 %0 = zext i16 %p to i321295 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1296 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 1, i32 0, <8 x i1> %1, <8 x i16> undef)1297 ret <8 x i16> %21298}1299 1300define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_u16(<8 x i16> %a, i16 zeroext %p) {1301; CHECK-LABEL: test_vshllbq_x_n_u16:1302; CHECK: @ %bb.0: @ %entry1303; CHECK-NEXT: vmsr p0, r01304; CHECK-NEXT: vpst1305; CHECK-NEXT: vshllbt.u16 q0, q0, #101306; CHECK-NEXT: bx lr1307entry:1308 %0 = zext i16 %p to i321309 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1310 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 10, i32 1, i32 0, <4 x i1> %1, <4 x i32> undef)1311 ret <4 x i32> %21312}1313 1314define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_u16_lanewidth(<8 x i16> %a, i16 zeroext %p) {1315; CHECK-LABEL: test_vshllbq_x_n_u16_lanewidth:1316; CHECK: @ %bb.0: @ %entry1317; CHECK-NEXT: vmsr p0, r01318; CHECK-NEXT: vpst1319; CHECK-NEXT: vshllbt.u16 q0, q0, #161320; CHECK-NEXT: bx lr1321entry:1322 %0 = zext i16 %p to i321323 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1324 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 1, i32 0, <4 x i1> %1, <4 x i32> undef)1325 ret <4 x i32> %21326}1327 1328define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_s8(<16 x i8> %a, i16 zeroext %p) {1329; CHECK-LABEL: test_vshlltq_x_n_s8:1330; CHECK: @ %bb.0: @ %entry1331; CHECK-NEXT: vmsr p0, r01332; CHECK-NEXT: vpst1333; CHECK-NEXT: vshlltt.s8 q0, q0, #21334; CHECK-NEXT: bx lr1335entry:1336 %0 = zext i16 %p to i321337 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1338 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 2, i32 0, i32 1, <8 x i1> %1, <8 x i16> undef)1339 ret <8 x i16> %21340}1341 1342define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_s8_lanewidth(<16 x i8> %a, i16 zeroext %p) {1343; CHECK-LABEL: test_vshlltq_x_n_s8_lanewidth:1344; CHECK: @ %bb.0: @ %entry1345; CHECK-NEXT: vmsr p0, r01346; CHECK-NEXT: vpst1347; CHECK-NEXT: vshlltt.s8 q0, q0, #81348; CHECK-NEXT: bx lr1349entry:1350 %0 = zext i16 %p to i321351 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1352 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 0, i32 1, <8 x i1> %1, <8 x i16> undef)1353 ret <8 x i16> %21354}1355 1356define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_s16(<8 x i16> %a, i16 zeroext %p) {1357; CHECK-LABEL: test_vshlltq_x_n_s16:1358; CHECK: @ %bb.0: @ %entry1359; CHECK-NEXT: vmsr p0, r01360; CHECK-NEXT: vpst1361; CHECK-NEXT: vshlltt.s16 q0, q0, #61362; CHECK-NEXT: bx lr1363entry:1364 %0 = zext i16 %p to i321365 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1366 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 6, i32 0, i32 1, <4 x i1> %1, <4 x i32> undef)1367 ret <4 x i32> %21368}1369 1370define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_s16_lanewidth(<8 x i16> %a, i16 zeroext %p) {1371; CHECK-LABEL: test_vshlltq_x_n_s16_lanewidth:1372; CHECK: @ %bb.0: @ %entry1373; CHECK-NEXT: vmsr p0, r01374; CHECK-NEXT: vpst1375; CHECK-NEXT: vshlltt.s16 q0, q0, #161376; CHECK-NEXT: bx lr1377entry:1378 %0 = zext i16 %p to i321379 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1380 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 0, i32 1, <4 x i1> %1, <4 x i32> undef)1381 ret <4 x i32> %21382}1383 1384define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_u8(<16 x i8> %a, i16 zeroext %p) {1385; CHECK-LABEL: test_vshlltq_x_n_u8:1386; CHECK: @ %bb.0: @ %entry1387; CHECK-NEXT: vmsr p0, r01388; CHECK-NEXT: vpst1389; CHECK-NEXT: vshlltt.u8 q0, q0, #51390; CHECK-NEXT: bx lr1391entry:1392 %0 = zext i16 %p to i321393 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1394 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 5, i32 1, i32 1, <8 x i1> %1, <8 x i16> undef)1395 ret <8 x i16> %21396}1397 1398define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_u8_lanewidth(<16 x i8> %a, i16 zeroext %p) {1399; CHECK-LABEL: test_vshlltq_x_n_u8_lanewidth:1400; CHECK: @ %bb.0: @ %entry1401; CHECK-NEXT: vmsr p0, r01402; CHECK-NEXT: vpst1403; CHECK-NEXT: vshlltt.u8 q0, q0, #81404; CHECK-NEXT: bx lr1405entry:1406 %0 = zext i16 %p to i321407 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1408 %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 1, i32 1, <8 x i1> %1, <8 x i16> undef)1409 ret <8 x i16> %21410}1411 1412define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_u16(<8 x i16> %a, i16 zeroext %p) {1413; CHECK-LABEL: test_vshlltq_x_n_u16:1414; CHECK: @ %bb.0: @ %entry1415; CHECK-NEXT: vmsr p0, r01416; CHECK-NEXT: vpst1417; CHECK-NEXT: vshlltt.u16 q0, q0, #31418; CHECK-NEXT: bx lr1419entry:1420 %0 = zext i16 %p to i321421 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1422 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 3, i32 1, i32 1, <4 x i1> %1, <4 x i32> undef)1423 ret <4 x i32> %21424}1425 1426define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_u16_lanewidth(<8 x i16> %a, i16 zeroext %p) {1427; CHECK-LABEL: test_vshlltq_x_n_u16_lanewidth:1428; CHECK: @ %bb.0: @ %entry1429; CHECK-NEXT: vmsr p0, r01430; CHECK-NEXT: vpst1431; CHECK-NEXT: vshlltt.u16 q0, q0, #161432; CHECK-NEXT: bx lr1433entry:1434 %0 = zext i16 %p to i321435 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1436 %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 1, i32 1, <4 x i1> %1, <4 x i32> undef)1437 ret <4 x i32> %21438}1439 1440declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)1441declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)1442declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)1443 1444declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>)1445declare <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x i16>)1446declare <4 x i32> @llvm.arm.mve.shl.imm.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x i32>)1447 1448declare <16 x i8> @llvm.arm.mve.shr.imm.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>, <16 x i8>)1449declare <8 x i16> @llvm.arm.mve.shr.imm.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>, <8 x i16>)1450declare <4 x i32> @llvm.arm.mve.shr.imm.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>, <4 x i32>)1451 1452declare <16 x i8> @llvm.arm.mve.vqshl.imm.v16i8(<16 x i8>, i32, i32)1453declare <8 x i16> @llvm.arm.mve.vqshl.imm.v8i16(<8 x i16>, i32, i32)1454declare <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32>, i32, i32)1455declare <16 x i8> @llvm.arm.mve.vqshl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>, <16 x i8>)1456declare <8 x i16> @llvm.arm.mve.vqshl.imm.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>, <8 x i16>)1457declare <4 x i32> @llvm.arm.mve.vqshl.imm.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>, <4 x i32>)1458 1459declare <16 x i8> @llvm.arm.mve.vqshlu.imm.v16i8(<16 x i8>, i32)1460declare <8 x i16> @llvm.arm.mve.vqshlu.imm.v8i16(<8 x i16>, i32)1461declare <4 x i32> @llvm.arm.mve.vqshlu.imm.v4i32(<4 x i32>, i32)1462declare <16 x i8> @llvm.arm.mve.vqshlu.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>)1463declare <8 x i16> @llvm.arm.mve.vqshlu.imm.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x i16>)1464declare <4 x i32> @llvm.arm.mve.vqshlu.imm.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x i32>)1465 1466declare <16 x i8> @llvm.arm.mve.vrshr.imm.v16i8(<16 x i8>, i32, i32)1467declare <8 x i16> @llvm.arm.mve.vrshr.imm.v8i16(<8 x i16>, i32, i32)1468declare <4 x i32> @llvm.arm.mve.vrshr.imm.v4i32(<4 x i32>, i32, i32)1469declare <16 x i8> @llvm.arm.mve.vrshr.imm.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>, <16 x i8>)1470declare <8 x i16> @llvm.arm.mve.vrshr.imm.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>, <8 x i16>)1471declare <4 x i32> @llvm.arm.mve.vrshr.imm.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>, <4 x i32>)1472 1473declare <8 x i16> @llvm.arm.mve.vshll.imm.v8i16.v16i8(<16 x i8>, i32, i32, i32)1474declare <4 x i32> @llvm.arm.mve.vshll.imm.v4i32.v8i16(<8 x i16>, i32, i32, i32)1475declare <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, i32, <8 x i1>, <8 x i16>)1476declare <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, i32, <4 x i1>, <4 x i32>)1477