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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vshlq_s8(<16 x i8> %a, <16 x i8> %b) {5; CHECK-LABEL: test_vshlq_s8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vshl.s8 q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 0)11 ret <16 x i8> %012}13 14define arm_aapcs_vfpcc <8 x i16> @test_vshlq_s16(<8 x i16> %a, <8 x i16> %b) {15; CHECK-LABEL: test_vshlq_s16:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vshl.s16 q0, q0, q118; CHECK-NEXT: bx lr19entry:20 %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 0)21 ret <8 x i16> %022}23 24define arm_aapcs_vfpcc <4 x i32> @test_vshlq_s32(<4 x i32> %a, <4 x i32> %b) {25; CHECK-LABEL: test_vshlq_s32:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vshl.s32 q0, q0, q128; CHECK-NEXT: bx lr29entry:30 %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 0)31 ret <4 x i32> %032}33 34define arm_aapcs_vfpcc <16 x i8> @test_vshlq_u8(<16 x i8> %a, <16 x i8> %b) {35; CHECK-LABEL: test_vshlq_u8:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vshl.u8 q0, q0, q138; CHECK-NEXT: bx lr39entry:40 %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 1)41 ret <16 x i8> %042}43 44define arm_aapcs_vfpcc <8 x i16> @test_vshlq_u16(<8 x i16> %a, <8 x i16> %b) {45; CHECK-LABEL: test_vshlq_u16:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vshl.u16 q0, q0, q148; CHECK-NEXT: bx lr49entry:50 %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 1)51 ret <8 x i16> %052}53 54define arm_aapcs_vfpcc <4 x i32> @test_vshlq_u32(<4 x i32> %a, <4 x i32> %b) {55; CHECK-LABEL: test_vshlq_u32:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vshl.u32 q0, q0, q158; CHECK-NEXT: bx lr59entry:60 %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 1)61 ret <4 x i32> %062}63 64define arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_s8(<16 x i8> %a, i32 %b) {65; CHECK-LABEL: test_vshlq_r_s8:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vshl.s8 q0, r068; CHECK-NEXT: bx lr69entry:70 %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 0, i32 0, i32 0)71 ret <16 x i8> %072}73 74define arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_s16(<8 x i16> %a, i32 %b) {75; CHECK-LABEL: test_vshlq_r_s16:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vshl.s16 q0, r078; CHECK-NEXT: bx lr79entry:80 %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 0, i32 0, i32 0)81 ret <8 x i16> %082}83 84define arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_s32(<4 x i32> %a, i32 %b) {85; CHECK-LABEL: test_vshlq_r_s32:86; CHECK: @ %bb.0: @ %entry87; CHECK-NEXT: vshl.s32 q0, r088; CHECK-NEXT: bx lr89entry:90 %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 0, i32 0, i32 0)91 ret <4 x i32> %092}93 94define arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_u8(<16 x i8> %a, i32 %b) {95; CHECK-LABEL: test_vshlq_r_u8:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: vshl.u8 q0, r098; CHECK-NEXT: bx lr99entry:100 %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 0, i32 0, i32 1)101 ret <16 x i8> %0102}103 104define arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_u16(<8 x i16> %a, i32 %b) {105; CHECK-LABEL: test_vshlq_r_u16:106; CHECK: @ %bb.0: @ %entry107; CHECK-NEXT: vshl.u16 q0, r0108; CHECK-NEXT: bx lr109entry:110 %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 0, i32 0, i32 1)111 ret <8 x i16> %0112}113 114define arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_u32(<4 x i32> %a, i32 %b) {115; CHECK-LABEL: test_vshlq_r_u32:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: vshl.u32 q0, r0118; CHECK-NEXT: bx lr119entry:120 %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 0, i32 0, i32 1)121 ret <4 x i32> %0122}123 124define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_s8(<16 x i8> %a, <16 x i8> %b) {125; CHECK-LABEL: test_vqshlq_s8:126; CHECK: @ %bb.0: @ %entry127; CHECK-NEXT: vqshl.s8 q0, q0, q1128; CHECK-NEXT: bx lr129entry:130 %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 0)131 ret <16 x i8> %0132}133 134define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_s16(<8 x i16> %a, <8 x i16> %b) {135; CHECK-LABEL: test_vqshlq_s16:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vqshl.s16 q0, q0, q1138; CHECK-NEXT: bx lr139entry:140 %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 0)141 ret <8 x i16> %0142}143 144define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_s32(<4 x i32> %a, <4 x i32> %b) {145; CHECK-LABEL: test_vqshlq_s32:146; CHECK: @ %bb.0: @ %entry147; CHECK-NEXT: vqshl.s32 q0, q0, q1148; CHECK-NEXT: bx lr149entry:150 %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 0)151 ret <4 x i32> %0152}153 154define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_u8(<16 x i8> %a, <16 x i8> %b) {155; CHECK-LABEL: test_vqshlq_u8:156; CHECK: @ %bb.0: @ %entry157; CHECK-NEXT: vqshl.u8 q0, q0, q1158; CHECK-NEXT: bx lr159entry:160 %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 1)161 ret <16 x i8> %0162}163 164define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_u16(<8 x i16> %a, <8 x i16> %b) {165; CHECK-LABEL: test_vqshlq_u16:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: vqshl.u16 q0, q0, q1168; CHECK-NEXT: bx lr169entry:170 %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 1)171 ret <8 x i16> %0172}173 174define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_u32(<4 x i32> %a, <4 x i32> %b) {175; CHECK-LABEL: test_vqshlq_u32:176; CHECK: @ %bb.0: @ %entry177; CHECK-NEXT: vqshl.u32 q0, q0, q1178; CHECK-NEXT: bx lr179entry:180 %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 1)181 ret <4 x i32> %0182}183 184define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_r_s8(<16 x i8> %a, i32 %b) {185; CHECK-LABEL: test_vqshlq_r_s8:186; CHECK: @ %bb.0: @ %entry187; CHECK-NEXT: vqshl.s8 q0, r0188; CHECK-NEXT: bx lr189entry:190 %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 1, i32 0, i32 0)191 ret <16 x i8> %0192}193 194define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_r_s16(<8 x i16> %a, i32 %b) {195; CHECK-LABEL: test_vqshlq_r_s16:196; CHECK: @ %bb.0: @ %entry197; CHECK-NEXT: vqshl.s16 q0, r0198; CHECK-NEXT: bx lr199entry:200 %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 1, i32 0, i32 0)201 ret <8 x i16> %0202}203 204define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_r_s32(<4 x i32> %a, i32 %b) {205; CHECK-LABEL: test_vqshlq_r_s32:206; CHECK: @ %bb.0: @ %entry207; CHECK-NEXT: vqshl.s32 q0, r0208; CHECK-NEXT: bx lr209entry:210 %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 1, i32 0, i32 0)211 ret <4 x i32> %0212}213 214define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_r_u8(<16 x i8> %a, i32 %b) {215; CHECK-LABEL: test_vqshlq_r_u8:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vqshl.u8 q0, r0218; CHECK-NEXT: bx lr219entry:220 %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 1, i32 0, i32 1)221 ret <16 x i8> %0222}223 224define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_r_u16(<8 x i16> %a, i32 %b) {225; CHECK-LABEL: test_vqshlq_r_u16:226; CHECK: @ %bb.0: @ %entry227; CHECK-NEXT: vqshl.u16 q0, r0228; CHECK-NEXT: bx lr229entry:230 %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 1, i32 0, i32 1)231 ret <8 x i16> %0232}233 234define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_r_u32(<4 x i32> %a, i32 %b) {235; CHECK-LABEL: test_vqshlq_r_u32:236; CHECK: @ %bb.0: @ %entry237; CHECK-NEXT: vqshl.u32 q0, r0238; CHECK-NEXT: bx lr239entry:240 %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 1, i32 0, i32 1)241 ret <4 x i32> %0242}243 244define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_s8(<16 x i8> %a, <16 x i8> %b) {245; CHECK-LABEL: test_vrshlq_s8:246; CHECK: @ %bb.0: @ %entry247; CHECK-NEXT: vrshl.s8 q0, q0, q1248; CHECK-NEXT: bx lr249entry:250 %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0)251 ret <16 x i8> %0252}253 254define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_s16(<8 x i16> %a, <8 x i16> %b) {255; CHECK-LABEL: test_vrshlq_s16:256; CHECK: @ %bb.0: @ %entry257; CHECK-NEXT: vrshl.s16 q0, q0, q1258; CHECK-NEXT: bx lr259entry:260 %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 0)261 ret <8 x i16> %0262}263 264define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_s32(<4 x i32> %a, <4 x i32> %b) {265; CHECK-LABEL: test_vrshlq_s32:266; CHECK: @ %bb.0: @ %entry267; CHECK-NEXT: vrshl.s32 q0, q0, q1268; CHECK-NEXT: bx lr269entry:270 %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 0)271 ret <4 x i32> %0272}273 274define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_u8(<16 x i8> %a, <16 x i8> %b) {275; CHECK-LABEL: test_vrshlq_u8:276; CHECK: @ %bb.0: @ %entry277; CHECK-NEXT: vrshl.u8 q0, q0, q1278; CHECK-NEXT: bx lr279entry:280 %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 1)281 ret <16 x i8> %0282}283 284define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_u16(<8 x i16> %a, <8 x i16> %b) {285; CHECK-LABEL: test_vrshlq_u16:286; CHECK: @ %bb.0: @ %entry287; CHECK-NEXT: vrshl.u16 q0, q0, q1288; CHECK-NEXT: bx lr289entry:290 %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 1)291 ret <8 x i16> %0292}293 294define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_u32(<4 x i32> %a, <4 x i32> %b) {295; CHECK-LABEL: test_vrshlq_u32:296; CHECK: @ %bb.0: @ %entry297; CHECK-NEXT: vrshl.u32 q0, q0, q1298; CHECK-NEXT: bx lr299entry:300 %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 1)301 ret <4 x i32> %0302}303 304define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_n_s8(<16 x i8> %a, i32 %b) {305; CHECK-LABEL: test_vrshlq_n_s8:306; CHECK: @ %bb.0: @ %entry307; CHECK-NEXT: vrshl.s8 q0, r0308; CHECK-NEXT: bx lr309entry:310 %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 0, i32 1, i32 0)311 ret <16 x i8> %0312}313 314define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_n_s16(<8 x i16> %a, i32 %b) {315; CHECK-LABEL: test_vrshlq_n_s16:316; CHECK: @ %bb.0: @ %entry317; CHECK-NEXT: vrshl.s16 q0, r0318; CHECK-NEXT: bx lr319entry:320 %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 0, i32 1, i32 0)321 ret <8 x i16> %0322}323 324define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_n_s32(<4 x i32> %a, i32 %b) {325; CHECK-LABEL: test_vrshlq_n_s32:326; CHECK: @ %bb.0: @ %entry327; CHECK-NEXT: vrshl.s32 q0, r0328; CHECK-NEXT: bx lr329entry:330 %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 0, i32 1, i32 0)331 ret <4 x i32> %0332}333 334define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_n_u8(<16 x i8> %a, i32 %b) {335; CHECK-LABEL: test_vrshlq_n_u8:336; CHECK: @ %bb.0: @ %entry337; CHECK-NEXT: vrshl.u8 q0, r0338; CHECK-NEXT: bx lr339entry:340 %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 0, i32 1, i32 1)341 ret <16 x i8> %0342}343 344define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_n_u16(<8 x i16> %a, i32 %b) {345; CHECK-LABEL: test_vrshlq_n_u16:346; CHECK: @ %bb.0: @ %entry347; CHECK-NEXT: vrshl.u16 q0, r0348; CHECK-NEXT: bx lr349entry:350 %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 0, i32 1, i32 1)351 ret <8 x i16> %0352}353 354define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_n_u32(<4 x i32> %a, i32 %b) {355; CHECK-LABEL: test_vrshlq_n_u32:356; CHECK: @ %bb.0: @ %entry357; CHECK-NEXT: vrshl.u32 q0, r0358; CHECK-NEXT: bx lr359entry:360 %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 0, i32 1, i32 1)361 ret <4 x i32> %0362}363 364define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_s8(<16 x i8> %a, <16 x i8> %b) {365; CHECK-LABEL: test_vqrshlq_s8:366; CHECK: @ %bb.0: @ %entry367; CHECK-NEXT: vqrshl.s8 q0, q0, q1368; CHECK-NEXT: bx lr369entry:370 %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 0)371 ret <16 x i8> %0372}373 374define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_s16(<8 x i16> %a, <8 x i16> %b) {375; CHECK-LABEL: test_vqrshlq_s16:376; CHECK: @ %bb.0: @ %entry377; CHECK-NEXT: vqrshl.s16 q0, q0, q1378; CHECK-NEXT: bx lr379entry:380 %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 0)381 ret <8 x i16> %0382}383 384define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_s32(<4 x i32> %a, <4 x i32> %b) {385; CHECK-LABEL: test_vqrshlq_s32:386; CHECK: @ %bb.0: @ %entry387; CHECK-NEXT: vqrshl.s32 q0, q0, q1388; CHECK-NEXT: bx lr389entry:390 %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 0)391 ret <4 x i32> %0392}393 394define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_u8(<16 x i8> %a, <16 x i8> %b) {395; CHECK-LABEL: test_vqrshlq_u8:396; CHECK: @ %bb.0: @ %entry397; CHECK-NEXT: vqrshl.u8 q0, q0, q1398; CHECK-NEXT: bx lr399entry:400 %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 1)401 ret <16 x i8> %0402}403 404define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_u16(<8 x i16> %a, <8 x i16> %b) {405; CHECK-LABEL: test_vqrshlq_u16:406; CHECK: @ %bb.0: @ %entry407; CHECK-NEXT: vqrshl.u16 q0, q0, q1408; CHECK-NEXT: bx lr409entry:410 %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 1)411 ret <8 x i16> %0412}413 414define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_u32(<4 x i32> %a, <4 x i32> %b) {415; CHECK-LABEL: test_vqrshlq_u32:416; CHECK: @ %bb.0: @ %entry417; CHECK-NEXT: vqrshl.u32 q0, q0, q1418; CHECK-NEXT: bx lr419entry:420 %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 1)421 ret <4 x i32> %0422}423 424define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_n_s8(<16 x i8> %a, i32 %b) {425; CHECK-LABEL: test_vqrshlq_n_s8:426; CHECK: @ %bb.0: @ %entry427; CHECK-NEXT: vqrshl.s8 q0, r0428; CHECK-NEXT: bx lr429entry:430 %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 1, i32 1, i32 0)431 ret <16 x i8> %0432}433 434define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_n_s16(<8 x i16> %a, i32 %b) {435; CHECK-LABEL: test_vqrshlq_n_s16:436; CHECK: @ %bb.0: @ %entry437; CHECK-NEXT: vqrshl.s16 q0, r0438; CHECK-NEXT: bx lr439entry:440 %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 1, i32 1, i32 0)441 ret <8 x i16> %0442}443 444define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_n_s32(<4 x i32> %a, i32 %b) {445; CHECK-LABEL: test_vqrshlq_n_s32:446; CHECK: @ %bb.0: @ %entry447; CHECK-NEXT: vqrshl.s32 q0, r0448; CHECK-NEXT: bx lr449entry:450 %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 1, i32 1, i32 0)451 ret <4 x i32> %0452}453 454define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_n_u8(<16 x i8> %a, i32 %b) {455; CHECK-LABEL: test_vqrshlq_n_u8:456; CHECK: @ %bb.0: @ %entry457; CHECK-NEXT: vqrshl.u8 q0, r0458; CHECK-NEXT: bx lr459entry:460 %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 1, i32 1, i32 1)461 ret <16 x i8> %0462}463 464define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_n_u16(<8 x i16> %a, i32 %b) {465; CHECK-LABEL: test_vqrshlq_n_u16:466; CHECK: @ %bb.0: @ %entry467; CHECK-NEXT: vqrshl.u16 q0, r0468; CHECK-NEXT: bx lr469entry:470 %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 1, i32 1, i32 1)471 ret <8 x i16> %0472}473 474define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_n_u32(<4 x i32> %a, i32 %b) {475; CHECK-LABEL: test_vqrshlq_n_u32:476; CHECK: @ %bb.0: @ %entry477; CHECK-NEXT: vqrshl.u32 q0, r0478; CHECK-NEXT: bx lr479entry:480 %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 1, i32 1, i32 1)481 ret <4 x i32> %0482}483 484define arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {485; CHECK-LABEL: test_vshlq_m_s8:486; CHECK: @ %bb.0: @ %entry487; CHECK-NEXT: vmsr p0, r0488; CHECK-NEXT: vpst489; CHECK-NEXT: vshlt.s8 q0, q1, q2490; CHECK-NEXT: bx lr491entry:492 %0 = zext i16 %p to i32493 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)494 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 0, <16 x i1> %1, <16 x i8> %inactive)495 ret <16 x i8> %2496}497 498define arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {499; CHECK-LABEL: test_vshlq_m_s16:500; CHECK: @ %bb.0: @ %entry501; CHECK-NEXT: vmsr p0, r0502; CHECK-NEXT: vpst503; CHECK-NEXT: vshlt.s16 q0, q1, q2504; CHECK-NEXT: bx lr505entry:506 %0 = zext i16 %p to i32507 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)508 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive)509 ret <8 x i16> %2510}511 512define arm_aapcs_vfpcc <4 x i32> @test_vshlq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {513; CHECK-LABEL: test_vshlq_m_s32:514; CHECK: @ %bb.0: @ %entry515; CHECK-NEXT: vmsr p0, r0516; CHECK-NEXT: vpst517; CHECK-NEXT: vshlt.s32 q0, q1, q2518; CHECK-NEXT: bx lr519entry:520 %0 = zext i16 %p to i32521 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)522 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 0, <4 x i1> %1, <4 x i32> %inactive)523 ret <4 x i32> %2524}525 526define arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {527; CHECK-LABEL: test_vshlq_m_u8:528; CHECK: @ %bb.0: @ %entry529; CHECK-NEXT: vmsr p0, r0530; CHECK-NEXT: vpst531; CHECK-NEXT: vshlt.u8 q0, q1, q2532; CHECK-NEXT: bx lr533entry:534 %0 = zext i16 %p to i32535 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)536 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 1, <16 x i1> %1, <16 x i8> %inactive)537 ret <16 x i8> %2538}539 540define arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {541; CHECK-LABEL: test_vshlq_m_u16:542; CHECK: @ %bb.0: @ %entry543; CHECK-NEXT: vmsr p0, r0544; CHECK-NEXT: vpst545; CHECK-NEXT: vshlt.u16 q0, q1, q2546; CHECK-NEXT: bx lr547entry:548 %0 = zext i16 %p to i32549 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)550 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 1, <8 x i1> %1, <8 x i16> %inactive)551 ret <8 x i16> %2552}553 554define arm_aapcs_vfpcc <4 x i32> @test_vshlq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {555; CHECK-LABEL: test_vshlq_m_u32:556; CHECK: @ %bb.0: @ %entry557; CHECK-NEXT: vmsr p0, r0558; CHECK-NEXT: vpst559; CHECK-NEXT: vshlt.u32 q0, q1, q2560; CHECK-NEXT: bx lr561entry:562 %0 = zext i16 %p to i32563 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)564 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 1, <4 x i1> %1, <4 x i32> %inactive)565 ret <4 x i32> %2566}567 568define arm_aapcs_vfpcc <16 x i8> @test_vshlq_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {569; CHECK-LABEL: test_vshlq_x_s8:570; CHECK: @ %bb.0: @ %entry571; CHECK-NEXT: vmsr p0, r0572; CHECK-NEXT: vpst573; CHECK-NEXT: vshlt.s8 q0, q0, q1574; CHECK-NEXT: bx lr575entry:576 %0 = zext i16 %p to i32577 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)578 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 0, <16 x i1> %1, <16 x i8> undef)579 ret <16 x i8> %2580}581 582define arm_aapcs_vfpcc <8 x i16> @test_vshlq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {583; CHECK-LABEL: test_vshlq_x_s16:584; CHECK: @ %bb.0: @ %entry585; CHECK-NEXT: vmsr p0, r0586; CHECK-NEXT: vpst587; CHECK-NEXT: vshlt.s16 q0, q0, q1588; CHECK-NEXT: bx lr589entry:590 %0 = zext i16 %p to i32591 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)592 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 0, <8 x i1> %1, <8 x i16> undef)593 ret <8 x i16> %2594}595 596define arm_aapcs_vfpcc <4 x i32> @test_vshlq_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {597; CHECK-LABEL: test_vshlq_x_s32:598; CHECK: @ %bb.0: @ %entry599; CHECK-NEXT: vmsr p0, r0600; CHECK-NEXT: vpst601; CHECK-NEXT: vshlt.s32 q0, q0, q1602; CHECK-NEXT: bx lr603entry:604 %0 = zext i16 %p to i32605 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)606 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 0, <4 x i1> %1, <4 x i32> undef)607 ret <4 x i32> %2608}609 610define arm_aapcs_vfpcc <16 x i8> @test_vshlq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {611; CHECK-LABEL: test_vshlq_x_u8:612; CHECK: @ %bb.0: @ %entry613; CHECK-NEXT: vmsr p0, r0614; CHECK-NEXT: vpst615; CHECK-NEXT: vshlt.u8 q0, q0, q1616; CHECK-NEXT: bx lr617entry:618 %0 = zext i16 %p to i32619 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)620 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 1, <16 x i1> %1, <16 x i8> undef)621 ret <16 x i8> %2622}623 624define arm_aapcs_vfpcc <8 x i16> @test_vshlq_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {625; CHECK-LABEL: test_vshlq_x_u16:626; CHECK: @ %bb.0: @ %entry627; CHECK-NEXT: vmsr p0, r0628; CHECK-NEXT: vpst629; CHECK-NEXT: vshlt.u16 q0, q0, q1630; CHECK-NEXT: bx lr631entry:632 %0 = zext i16 %p to i32633 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)634 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 1, <8 x i1> %1, <8 x i16> undef)635 ret <8 x i16> %2636}637 638define arm_aapcs_vfpcc <4 x i32> @test_vshlq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {639; CHECK-LABEL: test_vshlq_x_u32:640; CHECK: @ %bb.0: @ %entry641; CHECK-NEXT: vmsr p0, r0642; CHECK-NEXT: vpst643; CHECK-NEXT: vshlt.u32 q0, q0, q1644; CHECK-NEXT: bx lr645entry:646 %0 = zext i16 %p to i32647 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)648 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 1, <4 x i1> %1, <4 x i32> undef)649 ret <4 x i32> %2650}651 652define arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_r_s8(<16 x i8> %a, i32 %b, i16 zeroext %p) {653; CHECK-LABEL: test_vshlq_m_r_s8:654; CHECK: @ %bb.0: @ %entry655; CHECK-NEXT: vmsr p0, r1656; CHECK-NEXT: vpst657; CHECK-NEXT: vshlt.s8 q0, r0658; CHECK-NEXT: bx lr659entry:660 %0 = zext i16 %p to i32661 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)662 %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 0, i32 0, i32 0, <16 x i1> %1)663 ret <16 x i8> %2664}665 666define arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_r_s16(<8 x i16> %a, i32 %b, i16 zeroext %p) {667; CHECK-LABEL: test_vshlq_m_r_s16:668; CHECK: @ %bb.0: @ %entry669; CHECK-NEXT: vmsr p0, r1670; CHECK-NEXT: vpst671; CHECK-NEXT: vshlt.s16 q0, r0672; CHECK-NEXT: bx lr673entry:674 %0 = zext i16 %p to i32675 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)676 %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 0, i32 0, i32 0, <8 x i1> %1)677 ret <8 x i16> %2678}679 680define arm_aapcs_vfpcc <4 x i32> @test_vshlq_m_r_s32(<4 x i32> %a, i32 %b, i16 zeroext %p) {681; CHECK-LABEL: test_vshlq_m_r_s32:682; CHECK: @ %bb.0: @ %entry683; CHECK-NEXT: vmsr p0, r1684; CHECK-NEXT: vpst685; CHECK-NEXT: vshlt.s32 q0, r0686; CHECK-NEXT: bx lr687entry:688 %0 = zext i16 %p to i32689 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)690 %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 0, i32 0, i32 0, <4 x i1> %1)691 ret <4 x i32> %2692}693 694define arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_r_u8(<16 x i8> %a, i32 %b, i16 zeroext %p) {695; CHECK-LABEL: test_vshlq_m_r_u8:696; CHECK: @ %bb.0: @ %entry697; CHECK-NEXT: vmsr p0, r1698; CHECK-NEXT: vpst699; CHECK-NEXT: vshlt.u8 q0, r0700; CHECK-NEXT: bx lr701entry:702 %0 = zext i16 %p to i32703 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)704 %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 0, i32 0, i32 1, <16 x i1> %1)705 ret <16 x i8> %2706}707 708define arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_r_u16(<8 x i16> %a, i32 %b, i16 zeroext %p) {709; CHECK-LABEL: test_vshlq_m_r_u16:710; CHECK: @ %bb.0: @ %entry711; CHECK-NEXT: vmsr p0, r1712; CHECK-NEXT: vpst713; CHECK-NEXT: vshlt.u16 q0, r0714; CHECK-NEXT: bx lr715entry:716 %0 = zext i16 %p to i32717 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)718 %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 0, i32 0, i32 1, <8 x i1> %1)719 ret <8 x i16> %2720}721 722define arm_aapcs_vfpcc <4 x i32> @test_vshlq_m_r_u32(<4 x i32> %a, i32 %b, i16 zeroext %p) {723; CHECK-LABEL: test_vshlq_m_r_u32:724; CHECK: @ %bb.0: @ %entry725; CHECK-NEXT: vmsr p0, r1726; CHECK-NEXT: vpst727; CHECK-NEXT: vshlt.u32 q0, r0728; CHECK-NEXT: bx lr729entry:730 %0 = zext i16 %p to i32731 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)732 %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 0, i32 0, i32 1, <4 x i1> %1)733 ret <4 x i32> %2734}735 736define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {737; CHECK-LABEL: test_vqshlq_m_s8:738; CHECK: @ %bb.0: @ %entry739; CHECK-NEXT: vmsr p0, r0740; CHECK-NEXT: vpst741; CHECK-NEXT: vqshlt.s8 q0, q1, q2742; CHECK-NEXT: bx lr743entry:744 %0 = zext i16 %p to i32745 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)746 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 0, <16 x i1> %1, <16 x i8> %inactive)747 ret <16 x i8> %2748}749 750define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {751; CHECK-LABEL: test_vqshlq_m_s16:752; CHECK: @ %bb.0: @ %entry753; CHECK-NEXT: vmsr p0, r0754; CHECK-NEXT: vpst755; CHECK-NEXT: vqshlt.s16 q0, q1, q2756; CHECK-NEXT: bx lr757entry:758 %0 = zext i16 %p to i32759 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)760 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive)761 ret <8 x i16> %2762}763 764define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {765; CHECK-LABEL: test_vqshlq_m_s32:766; CHECK: @ %bb.0: @ %entry767; CHECK-NEXT: vmsr p0, r0768; CHECK-NEXT: vpst769; CHECK-NEXT: vqshlt.s32 q0, q1, q2770; CHECK-NEXT: bx lr771entry:772 %0 = zext i16 %p to i32773 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)774 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 0, <4 x i1> %1, <4 x i32> %inactive)775 ret <4 x i32> %2776}777 778define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {779; CHECK-LABEL: test_vqshlq_m_u8:780; CHECK: @ %bb.0: @ %entry781; CHECK-NEXT: vmsr p0, r0782; CHECK-NEXT: vpst783; CHECK-NEXT: vqshlt.u8 q0, q1, q2784; CHECK-NEXT: bx lr785entry:786 %0 = zext i16 %p to i32787 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)788 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 1, <16 x i1> %1, <16 x i8> %inactive)789 ret <16 x i8> %2790}791 792define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {793; CHECK-LABEL: test_vqshlq_m_u16:794; CHECK: @ %bb.0: @ %entry795; CHECK-NEXT: vmsr p0, r0796; CHECK-NEXT: vpst797; CHECK-NEXT: vqshlt.u16 q0, q1, q2798; CHECK-NEXT: bx lr799entry:800 %0 = zext i16 %p to i32801 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)802 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 1, <8 x i1> %1, <8 x i16> %inactive)803 ret <8 x i16> %2804}805 806define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {807; CHECK-LABEL: test_vqshlq_m_u32:808; CHECK: @ %bb.0: @ %entry809; CHECK-NEXT: vmsr p0, r0810; CHECK-NEXT: vpst811; CHECK-NEXT: vqshlt.u32 q0, q1, q2812; CHECK-NEXT: bx lr813entry:814 %0 = zext i16 %p to i32815 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)816 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 1, <4 x i1> %1, <4 x i32> %inactive)817 ret <4 x i32> %2818}819 820define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_m_r_s8(<16 x i8> %a, i32 %b, i16 zeroext %p) {821; CHECK-LABEL: test_vqshlq_m_r_s8:822; CHECK: @ %bb.0: @ %entry823; CHECK-NEXT: vmsr p0, r1824; CHECK-NEXT: vpst825; CHECK-NEXT: vqshlt.s8 q0, r0826; CHECK-NEXT: bx lr827entry:828 %0 = zext i16 %p to i32829 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)830 %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 1, i32 0, i32 0, <16 x i1> %1)831 ret <16 x i8> %2832}833 834define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_m_r_s16(<8 x i16> %a, i32 %b, i16 zeroext %p) {835; CHECK-LABEL: test_vqshlq_m_r_s16:836; CHECK: @ %bb.0: @ %entry837; CHECK-NEXT: vmsr p0, r1838; CHECK-NEXT: vpst839; CHECK-NEXT: vqshlt.s16 q0, r0840; CHECK-NEXT: bx lr841entry:842 %0 = zext i16 %p to i32843 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)844 %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 1, i32 0, i32 0, <8 x i1> %1)845 ret <8 x i16> %2846}847 848define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_m_r_s32(<4 x i32> %a, i32 %b, i16 zeroext %p) {849; CHECK-LABEL: test_vqshlq_m_r_s32:850; CHECK: @ %bb.0: @ %entry851; CHECK-NEXT: vmsr p0, r1852; CHECK-NEXT: vpst853; CHECK-NEXT: vqshlt.s32 q0, r0854; CHECK-NEXT: bx lr855entry:856 %0 = zext i16 %p to i32857 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)858 %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 1, i32 0, i32 0, <4 x i1> %1)859 ret <4 x i32> %2860}861 862define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_m_r_u8(<16 x i8> %a, i32 %b, i16 zeroext %p) {863; CHECK-LABEL: test_vqshlq_m_r_u8:864; CHECK: @ %bb.0: @ %entry865; CHECK-NEXT: vmsr p0, r1866; CHECK-NEXT: vpst867; CHECK-NEXT: vqshlt.u8 q0, r0868; CHECK-NEXT: bx lr869entry:870 %0 = zext i16 %p to i32871 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)872 %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 1, i32 0, i32 1, <16 x i1> %1)873 ret <16 x i8> %2874}875 876define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_m_r_u16(<8 x i16> %a, i32 %b, i16 zeroext %p) {877; CHECK-LABEL: test_vqshlq_m_r_u16:878; CHECK: @ %bb.0: @ %entry879; CHECK-NEXT: vmsr p0, r1880; CHECK-NEXT: vpst881; CHECK-NEXT: vqshlt.u16 q0, r0882; CHECK-NEXT: bx lr883entry:884 %0 = zext i16 %p to i32885 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)886 %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 1, i32 0, i32 1, <8 x i1> %1)887 ret <8 x i16> %2888}889 890define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_m_r_u32(<4 x i32> %a, i32 %b, i16 zeroext %p) {891; CHECK-LABEL: test_vqshlq_m_r_u32:892; CHECK: @ %bb.0: @ %entry893; CHECK-NEXT: vmsr p0, r1894; CHECK-NEXT: vpst895; CHECK-NEXT: vqshlt.u32 q0, r0896; CHECK-NEXT: bx lr897entry:898 %0 = zext i16 %p to i32899 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)900 %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 1, i32 0, i32 1, <4 x i1> %1)901 ret <4 x i32> %2902}903 904define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {905; CHECK-LABEL: test_vrshlq_m_s8:906; CHECK: @ %bb.0: @ %entry907; CHECK-NEXT: vmsr p0, r0908; CHECK-NEXT: vpst909; CHECK-NEXT: vrshlt.s8 q0, q1, q2910; CHECK-NEXT: bx lr911entry:912 %0 = zext i16 %p to i32913 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)914 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0, <16 x i1> %1, <16 x i8> %inactive)915 ret <16 x i8> %2916}917 918define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {919; CHECK-LABEL: test_vrshlq_m_s16:920; CHECK: @ %bb.0: @ %entry921; CHECK-NEXT: vmsr p0, r0922; CHECK-NEXT: vpst923; CHECK-NEXT: vrshlt.s16 q0, q1, q2924; CHECK-NEXT: bx lr925entry:926 %0 = zext i16 %p to i32927 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)928 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 0, <8 x i1> %1, <8 x i16> %inactive)929 ret <8 x i16> %2930}931 932define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {933; CHECK-LABEL: test_vrshlq_m_s32:934; CHECK: @ %bb.0: @ %entry935; CHECK-NEXT: vmsr p0, r0936; CHECK-NEXT: vpst937; CHECK-NEXT: vrshlt.s32 q0, q1, q2938; CHECK-NEXT: bx lr939entry:940 %0 = zext i16 %p to i32941 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)942 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive)943 ret <4 x i32> %2944}945 946define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {947; CHECK-LABEL: test_vrshlq_m_u8:948; CHECK: @ %bb.0: @ %entry949; CHECK-NEXT: vmsr p0, r0950; CHECK-NEXT: vpst951; CHECK-NEXT: vrshlt.u8 q0, q1, q2952; CHECK-NEXT: bx lr953entry:954 %0 = zext i16 %p to i32955 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)956 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 1, <16 x i1> %1, <16 x i8> %inactive)957 ret <16 x i8> %2958}959 960define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {961; CHECK-LABEL: test_vrshlq_m_u16:962; CHECK: @ %bb.0: @ %entry963; CHECK-NEXT: vmsr p0, r0964; CHECK-NEXT: vpst965; CHECK-NEXT: vrshlt.u16 q0, q1, q2966; CHECK-NEXT: bx lr967entry:968 %0 = zext i16 %p to i32969 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)970 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 1, <8 x i1> %1, <8 x i16> %inactive)971 ret <8 x i16> %2972}973 974define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {975; CHECK-LABEL: test_vrshlq_m_u32:976; CHECK: @ %bb.0: @ %entry977; CHECK-NEXT: vmsr p0, r0978; CHECK-NEXT: vpst979; CHECK-NEXT: vrshlt.u32 q0, q1, q2980; CHECK-NEXT: bx lr981entry:982 %0 = zext i16 %p to i32983 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)984 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 1, <4 x i1> %1, <4 x i32> %inactive)985 ret <4 x i32> %2986}987 988define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {989; CHECK-LABEL: test_vrshlq_x_s8:990; CHECK: @ %bb.0: @ %entry991; CHECK-NEXT: vmsr p0, r0992; CHECK-NEXT: vpst993; CHECK-NEXT: vrshlt.s8 q0, q0, q1994; CHECK-NEXT: bx lr995entry:996 %0 = zext i16 %p to i32997 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)998 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0, <16 x i1> %1, <16 x i8> undef)999 ret <16 x i8> %21000}1001 1002define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {1003; CHECK-LABEL: test_vrshlq_x_s16:1004; CHECK: @ %bb.0: @ %entry1005; CHECK-NEXT: vmsr p0, r01006; CHECK-NEXT: vpst1007; CHECK-NEXT: vrshlt.s16 q0, q0, q11008; CHECK-NEXT: bx lr1009entry:1010 %0 = zext i16 %p to i321011 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1012 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 0, <8 x i1> %1, <8 x i16> undef)1013 ret <8 x i16> %21014}1015 1016define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {1017; CHECK-LABEL: test_vrshlq_x_s32:1018; CHECK: @ %bb.0: @ %entry1019; CHECK-NEXT: vmsr p0, r01020; CHECK-NEXT: vpst1021; CHECK-NEXT: vrshlt.s32 q0, q0, q11022; CHECK-NEXT: bx lr1023entry:1024 %0 = zext i16 %p to i321025 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1026 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 0, <4 x i1> %1, <4 x i32> undef)1027 ret <4 x i32> %21028}1029 1030define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {1031; CHECK-LABEL: test_vrshlq_x_u8:1032; CHECK: @ %bb.0: @ %entry1033; CHECK-NEXT: vmsr p0, r01034; CHECK-NEXT: vpst1035; CHECK-NEXT: vrshlt.u8 q0, q0, q11036; CHECK-NEXT: bx lr1037entry:1038 %0 = zext i16 %p to i321039 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1040 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 1, <16 x i1> %1, <16 x i8> undef)1041 ret <16 x i8> %21042}1043 1044define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {1045; CHECK-LABEL: test_vrshlq_x_u16:1046; CHECK: @ %bb.0: @ %entry1047; CHECK-NEXT: vmsr p0, r01048; CHECK-NEXT: vpst1049; CHECK-NEXT: vrshlt.u16 q0, q0, q11050; CHECK-NEXT: bx lr1051entry:1052 %0 = zext i16 %p to i321053 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1054 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 1, <8 x i1> %1, <8 x i16> undef)1055 ret <8 x i16> %21056}1057 1058define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {1059; CHECK-LABEL: test_vrshlq_x_u32:1060; CHECK: @ %bb.0: @ %entry1061; CHECK-NEXT: vmsr p0, r01062; CHECK-NEXT: vpst1063; CHECK-NEXT: vrshlt.u32 q0, q0, q11064; CHECK-NEXT: bx lr1065entry:1066 %0 = zext i16 %p to i321067 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1068 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 1, <4 x i1> %1, <4 x i32> undef)1069 ret <4 x i32> %21070}1071 1072define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_m_n_s8(<16 x i8> %a, i32 %b, i16 zeroext %p) {1073; CHECK-LABEL: test_vrshlq_m_n_s8:1074; CHECK: @ %bb.0: @ %entry1075; CHECK-NEXT: vmsr p0, r11076; CHECK-NEXT: vpst1077; CHECK-NEXT: vrshlt.s8 q0, r01078; CHECK-NEXT: bx lr1079entry:1080 %0 = zext i16 %p to i321081 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1082 %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 0, i32 1, i32 0, <16 x i1> %1)1083 ret <16 x i8> %21084}1085 1086define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_m_n_s16(<8 x i16> %a, i32 %b, i16 zeroext %p) {1087; CHECK-LABEL: test_vrshlq_m_n_s16:1088; CHECK: @ %bb.0: @ %entry1089; CHECK-NEXT: vmsr p0, r11090; CHECK-NEXT: vpst1091; CHECK-NEXT: vrshlt.s16 q0, r01092; CHECK-NEXT: bx lr1093entry:1094 %0 = zext i16 %p to i321095 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1096 %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 0, i32 1, i32 0, <8 x i1> %1)1097 ret <8 x i16> %21098}1099 1100define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_m_n_s32(<4 x i32> %a, i32 %b, i16 zeroext %p) {1101; CHECK-LABEL: test_vrshlq_m_n_s32:1102; CHECK: @ %bb.0: @ %entry1103; CHECK-NEXT: vmsr p0, r11104; CHECK-NEXT: vpst1105; CHECK-NEXT: vrshlt.s32 q0, r01106; CHECK-NEXT: bx lr1107entry:1108 %0 = zext i16 %p to i321109 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1110 %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 0, i32 1, i32 0, <4 x i1> %1)1111 ret <4 x i32> %21112}1113 1114define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_m_n_u8(<16 x i8> %a, i32 %b, i16 zeroext %p) {1115; CHECK-LABEL: test_vrshlq_m_n_u8:1116; CHECK: @ %bb.0: @ %entry1117; CHECK-NEXT: vmsr p0, r11118; CHECK-NEXT: vpst1119; CHECK-NEXT: vrshlt.u8 q0, r01120; CHECK-NEXT: bx lr1121entry:1122 %0 = zext i16 %p to i321123 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1124 %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 0, i32 1, i32 1, <16 x i1> %1)1125 ret <16 x i8> %21126}1127 1128define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_m_n_u16(<8 x i16> %a, i32 %b, i16 zeroext %p) {1129; CHECK-LABEL: test_vrshlq_m_n_u16:1130; CHECK: @ %bb.0: @ %entry1131; CHECK-NEXT: vmsr p0, r11132; CHECK-NEXT: vpst1133; CHECK-NEXT: vrshlt.u16 q0, r01134; CHECK-NEXT: bx lr1135entry:1136 %0 = zext i16 %p to i321137 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1138 %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 0, i32 1, i32 1, <8 x i1> %1)1139 ret <8 x i16> %21140}1141 1142define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_m_n_u32(<4 x i32> %a, i32 %b, i16 zeroext %p) {1143; CHECK-LABEL: test_vrshlq_m_n_u32:1144; CHECK: @ %bb.0: @ %entry1145; CHECK-NEXT: vmsr p0, r11146; CHECK-NEXT: vpst1147; CHECK-NEXT: vrshlt.u32 q0, r01148; CHECK-NEXT: bx lr1149entry:1150 %0 = zext i16 %p to i321151 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1152 %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 0, i32 1, i32 1, <4 x i1> %1)1153 ret <4 x i32> %21154}1155 1156define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {1157; CHECK-LABEL: test_vqrshlq_m_s8:1158; CHECK: @ %bb.0: @ %entry1159; CHECK-NEXT: vmsr p0, r01160; CHECK-NEXT: vpst1161; CHECK-NEXT: vqrshlt.s8 q0, q1, q21162; CHECK-NEXT: bx lr1163entry:1164 %0 = zext i16 %p to i321165 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1166 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 0, <16 x i1> %1, <16 x i8> %inactive)1167 ret <16 x i8> %21168}1169 1170define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {1171; CHECK-LABEL: test_vqrshlq_m_s16:1172; CHECK: @ %bb.0: @ %entry1173; CHECK-NEXT: vmsr p0, r01174; CHECK-NEXT: vpst1175; CHECK-NEXT: vqrshlt.s16 q0, q1, q21176; CHECK-NEXT: bx lr1177entry:1178 %0 = zext i16 %p to i321179 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1180 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 0, <8 x i1> %1, <8 x i16> %inactive)1181 ret <8 x i16> %21182}1183 1184define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {1185; CHECK-LABEL: test_vqrshlq_m_s32:1186; CHECK: @ %bb.0: @ %entry1187; CHECK-NEXT: vmsr p0, r01188; CHECK-NEXT: vpst1189; CHECK-NEXT: vqrshlt.s32 q0, q1, q21190; CHECK-NEXT: bx lr1191entry:1192 %0 = zext i16 %p to i321193 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1194 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive)1195 ret <4 x i32> %21196}1197 1198define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {1199; CHECK-LABEL: test_vqrshlq_m_u8:1200; CHECK: @ %bb.0: @ %entry1201; CHECK-NEXT: vmsr p0, r01202; CHECK-NEXT: vpst1203; CHECK-NEXT: vqrshlt.u8 q0, q1, q21204; CHECK-NEXT: bx lr1205entry:1206 %0 = zext i16 %p to i321207 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1208 %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 1, <16 x i1> %1, <16 x i8> %inactive)1209 ret <16 x i8> %21210}1211 1212define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {1213; CHECK-LABEL: test_vqrshlq_m_u16:1214; CHECK: @ %bb.0: @ %entry1215; CHECK-NEXT: vmsr p0, r01216; CHECK-NEXT: vpst1217; CHECK-NEXT: vqrshlt.u16 q0, q1, q21218; CHECK-NEXT: bx lr1219entry:1220 %0 = zext i16 %p to i321221 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1222 %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 1, <8 x i1> %1, <8 x i16> %inactive)1223 ret <8 x i16> %21224}1225 1226define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {1227; CHECK-LABEL: test_vqrshlq_m_u32:1228; CHECK: @ %bb.0: @ %entry1229; CHECK-NEXT: vmsr p0, r01230; CHECK-NEXT: vpst1231; CHECK-NEXT: vqrshlt.u32 q0, q1, q21232; CHECK-NEXT: bx lr1233entry:1234 %0 = zext i16 %p to i321235 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1236 %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 1, <4 x i1> %1, <4 x i32> %inactive)1237 ret <4 x i32> %21238}1239 1240define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_m_n_s8(<16 x i8> %a, i32 %b, i16 zeroext %p) {1241; CHECK-LABEL: test_vqrshlq_m_n_s8:1242; CHECK: @ %bb.0: @ %entry1243; CHECK-NEXT: vmsr p0, r11244; CHECK-NEXT: vpst1245; CHECK-NEXT: vqrshlt.s8 q0, r01246; CHECK-NEXT: bx lr1247entry:1248 %0 = zext i16 %p to i321249 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1250 %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 1, i32 1, i32 0, <16 x i1> %1)1251 ret <16 x i8> %21252}1253 1254define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_m_n_s16(<8 x i16> %a, i32 %b, i16 zeroext %p) {1255; CHECK-LABEL: test_vqrshlq_m_n_s16:1256; CHECK: @ %bb.0: @ %entry1257; CHECK-NEXT: vmsr p0, r11258; CHECK-NEXT: vpst1259; CHECK-NEXT: vqrshlt.s16 q0, r01260; CHECK-NEXT: bx lr1261entry:1262 %0 = zext i16 %p to i321263 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1264 %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 1, i32 1, i32 0, <8 x i1> %1)1265 ret <8 x i16> %21266}1267 1268define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_m_n_s32(<4 x i32> %a, i32 %b, i16 zeroext %p) {1269; CHECK-LABEL: test_vqrshlq_m_n_s32:1270; CHECK: @ %bb.0: @ %entry1271; CHECK-NEXT: vmsr p0, r11272; CHECK-NEXT: vpst1273; CHECK-NEXT: vqrshlt.s32 q0, r01274; CHECK-NEXT: bx lr1275entry:1276 %0 = zext i16 %p to i321277 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1278 %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 1, i32 1, i32 0, <4 x i1> %1)1279 ret <4 x i32> %21280}1281 1282define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_m_n_u8(<16 x i8> %a, i32 %b, i16 zeroext %p) {1283; CHECK-LABEL: test_vqrshlq_m_n_u8:1284; CHECK: @ %bb.0: @ %entry1285; CHECK-NEXT: vmsr p0, r11286; CHECK-NEXT: vpst1287; CHECK-NEXT: vqrshlt.u8 q0, r01288; CHECK-NEXT: bx lr1289entry:1290 %0 = zext i16 %p to i321291 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)1292 %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 1, i32 1, i32 1, <16 x i1> %1)1293 ret <16 x i8> %21294}1295 1296define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_m_n_u16(<8 x i16> %a, i32 %b, i16 zeroext %p) {1297; CHECK-LABEL: test_vqrshlq_m_n_u16:1298; CHECK: @ %bb.0: @ %entry1299; CHECK-NEXT: vmsr p0, r11300; CHECK-NEXT: vpst1301; CHECK-NEXT: vqrshlt.u16 q0, r01302; CHECK-NEXT: bx lr1303entry:1304 %0 = zext i16 %p to i321305 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)1306 %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 1, i32 1, i32 1, <8 x i1> %1)1307 ret <8 x i16> %21308}1309 1310define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_m_n_u32(<4 x i32> %a, i32 %b, i16 zeroext %p) {1311; CHECK-LABEL: test_vqrshlq_m_n_u32:1312; CHECK: @ %bb.0: @ %entry1313; CHECK-NEXT: vmsr p0, r11314; CHECK-NEXT: vpst1315; CHECK-NEXT: vqrshlt.u32 q0, r01316; CHECK-NEXT: bx lr1317entry:1318 %0 = zext i16 %p to i321319 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)1320 %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 1, i32 1, i32 1, <4 x i1> %1)1321 ret <4 x i32> %21322}1323 1324declare <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8>, <16 x i8>, i32, i32, i32)1325declare <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16>, <8 x i16>, i32, i32, i32)1326declare <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32)1327declare <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8>, i32, i32, i32, i32)1328declare <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16>, i32, i32, i32, i32)1329declare <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32>, i32, i32, i32, i32)1330declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)1331declare <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, i32, i32, <16 x i1>, <16 x i8>)1332declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)1333declare <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, i32, i32, <8 x i1>, <8 x i16>)1334declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)1335declare <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, i32, i32, <4 x i1>, <4 x i32>)1336declare <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8>, i32, i32, i32, i32, <16 x i1>)1337declare <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16>, i32, i32, i32, i32, <8 x i1>)1338declare <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32>, i32, i32, i32, i32, <4 x i1>)1339