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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_s8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {5; CHECK-LABEL: test_vmaxaq_s8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmaxa.s8 q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = icmp slt <16 x i8> %b, zeroinitializer11 %1 = sub <16 x i8> zeroinitializer, %b12 %2 = select <16 x i1> %0, <16 x i8> %1, <16 x i8> %b13 %3 = icmp ugt <16 x i8> %2, %a14 %4 = select <16 x i1> %3, <16 x i8> %2, <16 x i8> %a15 ret <16 x i8> %416}17 18define arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {19; CHECK-LABEL: test_vmaxaq_s16:20; CHECK: @ %bb.0: @ %entry21; CHECK-NEXT: vmaxa.s16 q0, q122; CHECK-NEXT: bx lr23entry:24 %0 = icmp slt <8 x i16> %b, zeroinitializer25 %1 = sub <8 x i16> zeroinitializer, %b26 %2 = select <8 x i1> %0, <8 x i16> %1, <8 x i16> %b27 %3 = icmp ugt <8 x i16> %2, %a28 %4 = select <8 x i1> %3, <8 x i16> %2, <8 x i16> %a29 ret <8 x i16> %430}31 32define arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_s32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {33; CHECK-LABEL: test_vmaxaq_s32:34; CHECK: @ %bb.0: @ %entry35; CHECK-NEXT: vmaxa.s32 q0, q136; CHECK-NEXT: bx lr37entry:38 %0 = icmp slt <4 x i32> %b, zeroinitializer39 %1 = sub <4 x i32> zeroinitializer, %b40 %2 = select <4 x i1> %0, <4 x i32> %1, <4 x i32> %b41 %3 = icmp ugt <4 x i32> %2, %a42 %4 = select <4 x i1> %3, <4 x i32> %2, <4 x i32> %a43 ret <4 x i32> %444}45 46define arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_m_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {47; CHECK-LABEL: test_vmaxaq_m_s8:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: vmsr p0, r050; CHECK-NEXT: vpst51; CHECK-NEXT: vmaxat.s8 q0, q152; CHECK-NEXT: bx lr53entry:54 %0 = zext i16 %p to i3255 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)56 %2 = tail call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1)57 ret <16 x i8> %258}59 60declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #261 62declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #263 64define arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_m_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {65; CHECK-LABEL: test_vmaxaq_m_s16:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vmsr p0, r068; CHECK-NEXT: vpst69; CHECK-NEXT: vmaxat.s16 q0, q170; CHECK-NEXT: bx lr71entry:72 %0 = zext i16 %p to i3273 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)74 %2 = tail call <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1)75 ret <8 x i16> %276}77 78declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #279 80declare <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #281 82define arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_m_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {83; CHECK-LABEL: test_vmaxaq_m_s32:84; CHECK: @ %bb.0: @ %entry85; CHECK-NEXT: vmsr p0, r086; CHECK-NEXT: vpst87; CHECK-NEXT: vmaxat.s32 q0, q188; CHECK-NEXT: bx lr89entry:90 %0 = zext i16 %p to i3291 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)92 %2 = tail call <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1)93 ret <4 x i32> %294}95 96declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #297 98declare <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #299