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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 {5; CHECK-LABEL: test_vmaxnmaq_f16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmaxnma.f16 q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)11 %1 = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %b)12 %2 = tail call <8 x half> @llvm.maxnum.v8f16(<8 x half> %0, <8 x half> %1)13 ret <8 x half> %214}15 16declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #117 18declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #119 20define arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {21; CHECK-LABEL: test_vmaxnmaq_f32:22; CHECK: @ %bb.0: @ %entry23; CHECK-NEXT: vmaxnma.f32 q0, q124; CHECK-NEXT: bx lr25entry:26 %0 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)27 %1 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %b)28 %2 = tail call <4 x float> @llvm.maxnum.v4f32(<4 x float> %0, <4 x float> %1)29 ret <4 x float> %230}31 32declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #133 34declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #135 36define arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_m_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 {37; CHECK-LABEL: test_vmaxnmaq_m_f16:38; CHECK: @ %bb.0: @ %entry39; CHECK-NEXT: vmsr p0, r040; CHECK-NEXT: vpst41; CHECK-NEXT: vmaxnmat.f16 q0, q142; CHECK-NEXT: bx lr43entry:44 %0 = zext i16 %p to i3245 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)46 %2 = tail call <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1)47 ret <8 x half> %248}49 50declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #251 52declare <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #253 54define arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {55; CHECK-LABEL: test_vmaxnmaq_m_f32:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vmsr p0, r058; CHECK-NEXT: vpst59; CHECK-NEXT: vmaxnmat.f32 q0, q160; CHECK-NEXT: bx lr61entry:62 %0 = zext i16 %p to i3263 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)64 %2 = tail call <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1)65 ret <4 x float> %266}67 68declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #269 70declare <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #271