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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 {5; CHECK-LABEL: test_vmaxnmq_f16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmaxnm.f16 q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = tail call <8 x half> @llvm.maxnum.v8f16(<8 x half> %a, <8 x half> %b)11 ret <8 x half> %012}13 14declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #115 16define arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {17; CHECK-LABEL: test_vmaxnmq_f32:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vmaxnm.f32 q0, q0, q120; CHECK-NEXT: bx lr21entry:22 %0 = tail call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)23 ret <4 x float> %024}25 26declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #127 28define arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 {29; CHECK-LABEL: test_vmaxnmq_m_f16:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vmsr p0, r032; CHECK-NEXT: vpst33; CHECK-NEXT: vmaxnmt.f16 q0, q1, q234; CHECK-NEXT: bx lr35entry:36 %0 = zext i16 %p to i3237 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)38 %2 = tail call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, i32 0, <8 x i1> %1, <8 x half> %inactive)39 ret <8 x half> %240}41 42declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #243 44declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #245 46define arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {47; CHECK-LABEL: test_vmaxnmq_m_f32:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: vmsr p0, r050; CHECK-NEXT: vpst51; CHECK-NEXT: vmaxnmt.f32 q0, q1, q252; CHECK-NEXT: bx lr53entry:54 %0 = zext i16 %p to i3255 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)56 %2 = tail call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, i32 0, <4 x i1> %1, <4 x float> %inactive)57 ret <4 x float> %258}59 60declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #261 62declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #263 64define arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 {65; CHECK-LABEL: test_vmaxnmq_x_f16:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vmsr p0, r068; CHECK-NEXT: vpst69; CHECK-NEXT: vmaxnmt.f16 q0, q0, q170; CHECK-NEXT: bx lr71entry:72 %0 = zext i16 %p to i3273 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)74 %2 = tail call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, i32 0, <8 x i1> %1, <8 x half> undef)75 ret <8 x half> %276}77 78define arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {79; CHECK-LABEL: test_vmaxnmq_x_f32:80; CHECK: @ %bb.0: @ %entry81; CHECK-NEXT: vmsr p0, r082; CHECK-NEXT: vpst83; CHECK-NEXT: vmaxnmt.f32 q0, q0, q184; CHECK-NEXT: bx lr85entry:86 %0 = zext i16 %p to i3287 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)88 %2 = tail call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, i32 0, <4 x i1> %1, <4 x float> undef)89 ret <4 x float> %290}91 92