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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vmaxq_s8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {5; CHECK-LABEL: test_vmaxq_s8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmax.s8 q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = icmp slt <16 x i8> %a, %b11 %1 = select <16 x i1> %0, <16 x i8> %b, <16 x i8> %a12 ret <16 x i8> %113}14 15define arm_aapcs_vfpcc <8 x i16> @test_vmaxq_u16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {16; CHECK-LABEL: test_vmaxq_u16:17; CHECK: @ %bb.0: @ %entry18; CHECK-NEXT: vmax.u16 q0, q0, q119; CHECK-NEXT: bx lr20entry:21 %0 = icmp ult <8 x i16> %a, %b22 %1 = select <8 x i1> %0, <8 x i16> %b, <8 x i16> %a23 ret <8 x i16> %124}25 26define arm_aapcs_vfpcc <4 x i32> @test_vmaxq_s32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {27; CHECK-LABEL: test_vmaxq_s32:28; CHECK: @ %bb.0: @ %entry29; CHECK-NEXT: vmax.s32 q0, q0, q130; CHECK-NEXT: bx lr31entry:32 %0 = icmp slt <4 x i32> %a, %b33 %1 = select <4 x i1> %0, <4 x i32> %b, <4 x i32> %a34 ret <4 x i32> %135}36 37define arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {38; CHECK-LABEL: test_vmaxq_m_u8:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: vmsr p0, r041; CHECK-NEXT: vpst42; CHECK-NEXT: vmaxt.u8 q0, q1, q243; CHECK-NEXT: bx lr44entry:45 %0 = zext i16 %p to i3246 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)47 %2 = tail call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <16 x i8> %inactive)48 ret <16 x i8> %249}50 51declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #252 53declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #254 55define arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {56; CHECK-LABEL: test_vmaxq_m_s16:57; CHECK: @ %bb.0: @ %entry58; CHECK-NEXT: vmsr p0, r059; CHECK-NEXT: vpst60; CHECK-NEXT: vmaxt.s16 q0, q1, q261; CHECK-NEXT: bx lr62entry:63 %0 = zext i16 %p to i3264 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)65 %2 = tail call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, <8 x i1> %1, <8 x i16> %inactive)66 ret <8 x i16> %267}68 69declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #270 71declare <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #272 73define arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {74; CHECK-LABEL: test_vmaxq_m_u32:75; CHECK: @ %bb.0: @ %entry76; CHECK-NEXT: vmsr p0, r077; CHECK-NEXT: vpst78; CHECK-NEXT: vmaxt.u32 q0, q1, q279; CHECK-NEXT: bx lr80entry:81 %0 = zext i16 %p to i3282 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)83 %2 = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, <4 x i1> %1, <4 x i32> %inactive)84 ret <4 x i32> %285}86 87declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #288 89declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #290 91define arm_aapcs_vfpcc <16 x i8> @test_vmaxq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {92; CHECK-LABEL: test_vmaxq_x_u8:93; CHECK: @ %bb.0: @ %entry94; CHECK-NEXT: vmsr p0, r095; CHECK-NEXT: vpst96; CHECK-NEXT: vmaxt.u8 q0, q0, q197; CHECK-NEXT: bx lr98entry:99 %0 = zext i16 %p to i32100 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)101 %2 = tail call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <16 x i8> undef)102 ret <16 x i8> %2103}104 105define arm_aapcs_vfpcc <8 x i16> @test_vmaxq_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {106; CHECK-LABEL: test_vmaxq_x_u16:107; CHECK: @ %bb.0: @ %entry108; CHECK-NEXT: vmsr p0, r0109; CHECK-NEXT: vpst110; CHECK-NEXT: vmaxt.s16 q0, q0, q1111; CHECK-NEXT: bx lr112entry:113 %0 = zext i16 %p to i32114 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)115 %2 = tail call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, <8 x i1> %1, <8 x i16> undef)116 ret <8 x i16> %2117}118 119define arm_aapcs_vfpcc <4 x i32> @test_vmaxq_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {120; CHECK-LABEL: test_vmaxq_x_s32:121; CHECK: @ %bb.0: @ %entry122; CHECK-NEXT: vmsr p0, r0123; CHECK-NEXT: vpst124; CHECK-NEXT: vmaxt.u32 q0, q0, q1125; CHECK-NEXT: bx lr126entry:127 %0 = zext i16 %p to i32128 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)129 %2 = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, <4 x i1> %1, <4 x i32> undef)130 ret <4 x i32> %2131}132 133