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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc signext i8 @test_vminvq_s8(i8 signext %a, <16 x i8> %b) {5; CHECK-LABEL: test_vminvq_s8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vminv.s8 r0, q08; CHECK-NEXT: sxtb r0, r09; CHECK-NEXT: bx lr10entry:11 %0 = zext i8 %a to i3212 %1 = tail call i32 @llvm.arm.mve.minv.v16i8(i32 %0, <16 x i8> %b, i32 0)13 %2 = trunc i32 %1 to i814 ret i8 %215}16 17define arm_aapcs_vfpcc signext i16 @test_vminvq_s16(i16 signext %a, <8 x i16> %b) {18; CHECK-LABEL: test_vminvq_s16:19; CHECK: @ %bb.0: @ %entry20; CHECK-NEXT: vminv.s16 r0, q021; CHECK-NEXT: sxth r0, r022; CHECK-NEXT: bx lr23entry:24 %0 = zext i16 %a to i3225 %1 = tail call i32 @llvm.arm.mve.minv.v8i16(i32 %0, <8 x i16> %b, i32 0)26 %2 = trunc i32 %1 to i1627 ret i16 %228}29 30define arm_aapcs_vfpcc i32 @test_vminvq_s32(i32 %a, <4 x i32> %b) {31; CHECK-LABEL: test_vminvq_s32:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: vminv.s32 r0, q034; CHECK-NEXT: bx lr35entry:36 %0 = tail call i32 @llvm.arm.mve.minv.v4i32(i32 %a, <4 x i32> %b, i32 0)37 ret i32 %038}39 40define arm_aapcs_vfpcc zeroext i8 @test_vminvq_u8(i8 zeroext %a, <16 x i8> %b) {41; CHECK-LABEL: test_vminvq_u8:42; CHECK: @ %bb.0: @ %entry43; CHECK-NEXT: vminv.u8 r0, q044; CHECK-NEXT: uxtb r0, r045; CHECK-NEXT: bx lr46entry:47 %0 = zext i8 %a to i3248 %1 = tail call i32 @llvm.arm.mve.minv.v16i8(i32 %0, <16 x i8> %b, i32 1)49 %2 = trunc i32 %1 to i850 ret i8 %251}52 53define arm_aapcs_vfpcc zeroext i16 @test_vminvq_u16(i16 zeroext %a, <8 x i16> %b) {54; CHECK-LABEL: test_vminvq_u16:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: vminv.u16 r0, q057; CHECK-NEXT: uxth r0, r058; CHECK-NEXT: bx lr59entry:60 %0 = zext i16 %a to i3261 %1 = tail call i32 @llvm.arm.mve.minv.v8i16(i32 %0, <8 x i16> %b, i32 1)62 %2 = trunc i32 %1 to i1663 ret i16 %264}65 66define arm_aapcs_vfpcc i32 @test_vminvq_u32(i32 %a, <4 x i32> %b) {67; CHECK-LABEL: test_vminvq_u32:68; CHECK: @ %bb.0: @ %entry69; CHECK-NEXT: vminv.u32 r0, q070; CHECK-NEXT: bx lr71entry:72 %0 = tail call i32 @llvm.arm.mve.minv.v4i32(i32 %a, <4 x i32> %b, i32 1)73 ret i32 %074}75 76define arm_aapcs_vfpcc signext i8 @test_vmaxvq_s8(i8 signext %a, <16 x i8> %b) {77; CHECK-LABEL: test_vmaxvq_s8:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vmaxv.s8 r0, q080; CHECK-NEXT: sxtb r0, r081; CHECK-NEXT: bx lr82entry:83 %0 = zext i8 %a to i3284 %1 = tail call i32 @llvm.arm.mve.maxv.v16i8(i32 %0, <16 x i8> %b, i32 0)85 %2 = trunc i32 %1 to i886 ret i8 %287}88 89define arm_aapcs_vfpcc signext i16 @test_vmaxvq_s16(i16 signext %a, <8 x i16> %b) {90; CHECK-LABEL: test_vmaxvq_s16:91; CHECK: @ %bb.0: @ %entry92; CHECK-NEXT: vmaxv.s16 r0, q093; CHECK-NEXT: sxth r0, r094; CHECK-NEXT: bx lr95entry:96 %0 = zext i16 %a to i3297 %1 = tail call i32 @llvm.arm.mve.maxv.v8i16(i32 %0, <8 x i16> %b, i32 0)98 %2 = trunc i32 %1 to i1699 ret i16 %2100}101 102define arm_aapcs_vfpcc i32 @test_vmaxvq_s32(i32 %a, <4 x i32> %b) {103; CHECK-LABEL: test_vmaxvq_s32:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vmaxv.s32 r0, q0106; CHECK-NEXT: bx lr107entry:108 %0 = tail call i32 @llvm.arm.mve.maxv.v4i32(i32 %a, <4 x i32> %b, i32 0)109 ret i32 %0110}111 112define arm_aapcs_vfpcc zeroext i8 @test_vmaxvq_u8(i8 zeroext %a, <16 x i8> %b) {113; CHECK-LABEL: test_vmaxvq_u8:114; CHECK: @ %bb.0: @ %entry115; CHECK-NEXT: vmaxv.u8 r0, q0116; CHECK-NEXT: uxtb r0, r0117; CHECK-NEXT: bx lr118entry:119 %0 = zext i8 %a to i32120 %1 = tail call i32 @llvm.arm.mve.maxv.v16i8(i32 %0, <16 x i8> %b, i32 1)121 %2 = trunc i32 %1 to i8122 ret i8 %2123}124 125define arm_aapcs_vfpcc zeroext i16 @test_vmaxvq_u16(i16 zeroext %a, <8 x i16> %b) {126; CHECK-LABEL: test_vmaxvq_u16:127; CHECK: @ %bb.0: @ %entry128; CHECK-NEXT: vmaxv.u16 r0, q0129; CHECK-NEXT: uxth r0, r0130; CHECK-NEXT: bx lr131entry:132 %0 = zext i16 %a to i32133 %1 = tail call i32 @llvm.arm.mve.maxv.v8i16(i32 %0, <8 x i16> %b, i32 1)134 %2 = trunc i32 %1 to i16135 ret i16 %2136}137 138define arm_aapcs_vfpcc i32 @test_vmaxvq_u32(i32 %a, <4 x i32> %b) {139; CHECK-LABEL: test_vmaxvq_u32:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: vmaxv.u32 r0, q0142; CHECK-NEXT: bx lr143entry:144 %0 = tail call i32 @llvm.arm.mve.maxv.v4i32(i32 %a, <4 x i32> %b, i32 1)145 ret i32 %0146}147 148define arm_aapcs_vfpcc zeroext i8 @test_vminavq_s8(i8 zeroext %a, <16 x i8> %b) {149; CHECK-LABEL: test_vminavq_s8:150; CHECK: @ %bb.0: @ %entry151; CHECK-NEXT: vminav.s8 r0, q0152; CHECK-NEXT: uxtb r0, r0153; CHECK-NEXT: bx lr154entry:155 %0 = zext i8 %a to i32156 %1 = tail call i32 @llvm.arm.mve.minav.v16i8(i32 %0, <16 x i8> %b)157 %2 = trunc i32 %1 to i8158 ret i8 %2159}160 161define arm_aapcs_vfpcc zeroext i16 @test_vminavq_s16(i16 zeroext %a, <8 x i16> %b) {162; CHECK-LABEL: test_vminavq_s16:163; CHECK: @ %bb.0: @ %entry164; CHECK-NEXT: vminav.s16 r0, q0165; CHECK-NEXT: uxth r0, r0166; CHECK-NEXT: bx lr167entry:168 %0 = zext i16 %a to i32169 %1 = tail call i32 @llvm.arm.mve.minav.v8i16(i32 %0, <8 x i16> %b)170 %2 = trunc i32 %1 to i16171 ret i16 %2172}173 174define arm_aapcs_vfpcc i32 @test_vminavq_s32(i32 %a, <4 x i32> %b) {175; CHECK-LABEL: test_vminavq_s32:176; CHECK: @ %bb.0: @ %entry177; CHECK-NEXT: vminav.s32 r0, q0178; CHECK-NEXT: bx lr179entry:180 %0 = tail call i32 @llvm.arm.mve.minav.v4i32(i32 %a, <4 x i32> %b)181 ret i32 %0182}183 184define arm_aapcs_vfpcc zeroext i8 @test_vmaxavq_s8(i8 zeroext %a, <16 x i8> %b) {185; CHECK-LABEL: test_vmaxavq_s8:186; CHECK: @ %bb.0: @ %entry187; CHECK-NEXT: vmaxav.s8 r0, q0188; CHECK-NEXT: uxtb r0, r0189; CHECK-NEXT: bx lr190entry:191 %0 = zext i8 %a to i32192 %1 = tail call i32 @llvm.arm.mve.maxav.v16i8(i32 %0, <16 x i8> %b)193 %2 = trunc i32 %1 to i8194 ret i8 %2195}196 197define arm_aapcs_vfpcc zeroext i16 @test_vmaxavq_s16(i16 zeroext %a, <8 x i16> %b) {198; CHECK-LABEL: test_vmaxavq_s16:199; CHECK: @ %bb.0: @ %entry200; CHECK-NEXT: vmaxav.s16 r0, q0201; CHECK-NEXT: uxth r0, r0202; CHECK-NEXT: bx lr203entry:204 %0 = zext i16 %a to i32205 %1 = tail call i32 @llvm.arm.mve.maxav.v8i16(i32 %0, <8 x i16> %b)206 %2 = trunc i32 %1 to i16207 ret i16 %2208}209 210define arm_aapcs_vfpcc i32 @test_vmaxavq_s32(i32 %a, <4 x i32> %b) {211; CHECK-LABEL: test_vmaxavq_s32:212; CHECK: @ %bb.0: @ %entry213; CHECK-NEXT: vmaxav.s32 r0, q0214; CHECK-NEXT: bx lr215entry:216 %0 = tail call i32 @llvm.arm.mve.maxav.v4i32(i32 %a, <4 x i32> %b)217 ret i32 %0218}219 220define arm_aapcs_vfpcc float @test_vminnmvq_f16(float %a.coerce, <8 x half> %b) {221; CHECK-LABEL: test_vminnmvq_f16:222; CHECK: @ %bb.0: @ %entry223; CHECK-NEXT: vmov r0, s0224; CHECK-NEXT: vminnmv.f16 r0, q1225; CHECK-NEXT: vmov s0, r0226; CHECK-NEXT: vmov.f16 r0, s0227; CHECK-NEXT: vmov s0, r0228; CHECK-NEXT: bx lr229entry:230 %0 = bitcast float %a.coerce to i32231 %tmp.0.extract.trunc = trunc i32 %0 to i16232 %1 = bitcast i16 %tmp.0.extract.trunc to half233 %2 = tail call half @llvm.arm.mve.minnmv.f16.v8f16(half %1, <8 x half> %b)234 %3 = bitcast half %2 to i16235 %tmp2.0.insert.ext = zext i16 %3 to i32236 %4 = bitcast i32 %tmp2.0.insert.ext to float237 ret float %4238}239 240define arm_aapcs_vfpcc float @test_vminnmvq_f32(float %a, <4 x float> %b) {241; CHECK-LABEL: test_vminnmvq_f32:242; CHECK: @ %bb.0: @ %entry243; CHECK-NEXT: vmov r0, s0244; CHECK-NEXT: vminnmv.f32 r0, q1245; CHECK-NEXT: vmov s0, r0246; CHECK-NEXT: bx lr247entry:248 %0 = tail call float @llvm.arm.mve.minnmv.f32.v4f32(float %a, <4 x float> %b)249 ret float %0250}251 252define arm_aapcs_vfpcc float @test_vminnmavq_f16(float %a.coerce, <8 x half> %b) {253; CHECK-LABEL: test_vminnmavq_f16:254; CHECK: @ %bb.0: @ %entry255; CHECK-NEXT: vmov r0, s0256; CHECK-NEXT: vminnmav.f16 r0, q1257; CHECK-NEXT: vmov s0, r0258; CHECK-NEXT: vmov.f16 r0, s0259; CHECK-NEXT: vmov s0, r0260; CHECK-NEXT: bx lr261entry:262 %0 = bitcast float %a.coerce to i32263 %tmp.0.extract.trunc = trunc i32 %0 to i16264 %1 = bitcast i16 %tmp.0.extract.trunc to half265 %2 = tail call half @llvm.arm.mve.minnmav.f16.v8f16(half %1, <8 x half> %b)266 %3 = bitcast half %2 to i16267 %tmp2.0.insert.ext = zext i16 %3 to i32268 %4 = bitcast i32 %tmp2.0.insert.ext to float269 ret float %4270}271 272define arm_aapcs_vfpcc float @test_vminnmavq_f32(float %a, <4 x float> %b) {273; CHECK-LABEL: test_vminnmavq_f32:274; CHECK: @ %bb.0: @ %entry275; CHECK-NEXT: vmov r0, s0276; CHECK-NEXT: vminnmav.f32 r0, q1277; CHECK-NEXT: vmov s0, r0278; CHECK-NEXT: bx lr279entry:280 %0 = tail call float @llvm.arm.mve.minnmav.f32.v4f32(float %a, <4 x float> %b)281 ret float %0282}283 284define arm_aapcs_vfpcc float @test_vmaxnmvq_f16(float %a.coerce, <8 x half> %b) {285; CHECK-LABEL: test_vmaxnmvq_f16:286; CHECK: @ %bb.0: @ %entry287; CHECK-NEXT: vmov r0, s0288; CHECK-NEXT: vmaxnmv.f16 r0, q1289; CHECK-NEXT: vmov s0, r0290; CHECK-NEXT: vmov.f16 r0, s0291; CHECK-NEXT: vmov s0, r0292; CHECK-NEXT: bx lr293entry:294 %0 = bitcast float %a.coerce to i32295 %tmp.0.extract.trunc = trunc i32 %0 to i16296 %1 = bitcast i16 %tmp.0.extract.trunc to half297 %2 = tail call half @llvm.arm.mve.maxnmv.f16.v8f16(half %1, <8 x half> %b)298 %3 = bitcast half %2 to i16299 %tmp2.0.insert.ext = zext i16 %3 to i32300 %4 = bitcast i32 %tmp2.0.insert.ext to float301 ret float %4302}303 304define arm_aapcs_vfpcc float @test_vmaxnmvq_f32(float %a, <4 x float> %b) {305; CHECK-LABEL: test_vmaxnmvq_f32:306; CHECK: @ %bb.0: @ %entry307; CHECK-NEXT: vmov r0, s0308; CHECK-NEXT: vmaxnmv.f32 r0, q1309; CHECK-NEXT: vmov s0, r0310; CHECK-NEXT: bx lr311entry:312 %0 = tail call float @llvm.arm.mve.maxnmv.f32.v4f32(float %a, <4 x float> %b)313 ret float %0314}315 316define arm_aapcs_vfpcc float @test_vmaxnmavq_f16(float %a.coerce, <8 x half> %b) {317; CHECK-LABEL: test_vmaxnmavq_f16:318; CHECK: @ %bb.0: @ %entry319; CHECK-NEXT: vmov r0, s0320; CHECK-NEXT: vmaxnmav.f16 r0, q1321; CHECK-NEXT: vmov s0, r0322; CHECK-NEXT: vmov.f16 r0, s0323; CHECK-NEXT: vmov s0, r0324; CHECK-NEXT: bx lr325entry:326 %0 = bitcast float %a.coerce to i32327 %tmp.0.extract.trunc = trunc i32 %0 to i16328 %1 = bitcast i16 %tmp.0.extract.trunc to half329 %2 = tail call half @llvm.arm.mve.maxnmav.f16.v8f16(half %1, <8 x half> %b)330 %3 = bitcast half %2 to i16331 %tmp2.0.insert.ext = zext i16 %3 to i32332 %4 = bitcast i32 %tmp2.0.insert.ext to float333 ret float %4334}335 336define arm_aapcs_vfpcc float @test_vmaxnmavq_f32(float %a, <4 x float> %b) {337; CHECK-LABEL: test_vmaxnmavq_f32:338; CHECK: @ %bb.0: @ %entry339; CHECK-NEXT: vmov r0, s0340; CHECK-NEXT: vmaxnmav.f32 r0, q1341; CHECK-NEXT: vmov s0, r0342; CHECK-NEXT: bx lr343entry:344 %0 = tail call float @llvm.arm.mve.maxnmav.f32.v4f32(float %a, <4 x float> %b)345 ret float %0346}347 348define arm_aapcs_vfpcc signext i8 @test_vminvq_p_s8(i8 signext %a, <16 x i8> %b, i16 zeroext %p) {349; CHECK-LABEL: test_vminvq_p_s8:350; CHECK: @ %bb.0: @ %entry351; CHECK-NEXT: vmsr p0, r1352; CHECK-NEXT: vpst353; CHECK-NEXT: vminvt.s8 r0, q0354; CHECK-NEXT: sxtb r0, r0355; CHECK-NEXT: bx lr356entry:357 %0 = zext i8 %a to i32358 %1 = zext i16 %p to i32359 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)360 %3 = tail call i32 @llvm.arm.mve.minv.predicated.v16i8.v16i1(i32 %0, <16 x i8> %b, i32 0, <16 x i1> %2)361 %4 = trunc i32 %3 to i8362 ret i8 %4363}364 365define arm_aapcs_vfpcc signext i16 @test_vminvq_p_s16(i16 signext %a, <8 x i16> %b, i16 zeroext %p) {366; CHECK-LABEL: test_vminvq_p_s16:367; CHECK: @ %bb.0: @ %entry368; CHECK-NEXT: vmsr p0, r1369; CHECK-NEXT: vpst370; CHECK-NEXT: vminvt.s16 r0, q0371; CHECK-NEXT: sxth r0, r0372; CHECK-NEXT: bx lr373entry:374 %0 = zext i16 %a to i32375 %1 = zext i16 %p to i32376 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)377 %3 = tail call i32 @llvm.arm.mve.minv.predicated.v8i16.v8i1(i32 %0, <8 x i16> %b, i32 0, <8 x i1> %2)378 %4 = trunc i32 %3 to i16379 ret i16 %4380}381 382define arm_aapcs_vfpcc i32 @test_vminvq_p_s32(i32 %a, <4 x i32> %b, i16 zeroext %p) {383; CHECK-LABEL: test_vminvq_p_s32:384; CHECK: @ %bb.0: @ %entry385; CHECK-NEXT: vmsr p0, r1386; CHECK-NEXT: vpst387; CHECK-NEXT: vminvt.s32 r0, q0388; CHECK-NEXT: bx lr389entry:390 %0 = zext i16 %p to i32391 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)392 %2 = tail call i32 @llvm.arm.mve.minv.predicated.v4i32.v4i1(i32 %a, <4 x i32> %b, i32 0, <4 x i1> %1)393 ret i32 %2394}395 396define arm_aapcs_vfpcc zeroext i8 @test_vminvq_p_u8(i8 zeroext %a, <16 x i8> %b, i16 zeroext %p) {397; CHECK-LABEL: test_vminvq_p_u8:398; CHECK: @ %bb.0: @ %entry399; CHECK-NEXT: vmsr p0, r1400; CHECK-NEXT: vpst401; CHECK-NEXT: vminvt.u8 r0, q0402; CHECK-NEXT: uxtb r0, r0403; CHECK-NEXT: bx lr404entry:405 %0 = zext i8 %a to i32406 %1 = zext i16 %p to i32407 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)408 %3 = tail call i32 @llvm.arm.mve.minv.predicated.v16i8.v16i1(i32 %0, <16 x i8> %b, i32 1, <16 x i1> %2)409 %4 = trunc i32 %3 to i8410 ret i8 %4411}412 413define arm_aapcs_vfpcc zeroext i16 @test_vminvq_p_u16(i16 zeroext %a, <8 x i16> %b, i16 zeroext %p) {414; CHECK-LABEL: test_vminvq_p_u16:415; CHECK: @ %bb.0: @ %entry416; CHECK-NEXT: vmsr p0, r1417; CHECK-NEXT: vpst418; CHECK-NEXT: vminvt.u16 r0, q0419; CHECK-NEXT: uxth r0, r0420; CHECK-NEXT: bx lr421entry:422 %0 = zext i16 %a to i32423 %1 = zext i16 %p to i32424 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)425 %3 = tail call i32 @llvm.arm.mve.minv.predicated.v8i16.v8i1(i32 %0, <8 x i16> %b, i32 1, <8 x i1> %2)426 %4 = trunc i32 %3 to i16427 ret i16 %4428}429 430define arm_aapcs_vfpcc i32 @test_vminvq_p_u32(i32 %a, <4 x i32> %b, i16 zeroext %p) {431; CHECK-LABEL: test_vminvq_p_u32:432; CHECK: @ %bb.0: @ %entry433; CHECK-NEXT: vmsr p0, r1434; CHECK-NEXT: vpst435; CHECK-NEXT: vminvt.u32 r0, q0436; CHECK-NEXT: bx lr437entry:438 %0 = zext i16 %p to i32439 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)440 %2 = tail call i32 @llvm.arm.mve.minv.predicated.v4i32.v4i1(i32 %a, <4 x i32> %b, i32 1, <4 x i1> %1)441 ret i32 %2442}443 444define arm_aapcs_vfpcc signext i8 @test_vmaxvq_p_s8(i8 signext %a, <16 x i8> %b, i16 zeroext %p) {445; CHECK-LABEL: test_vmaxvq_p_s8:446; CHECK: @ %bb.0: @ %entry447; CHECK-NEXT: vmsr p0, r1448; CHECK-NEXT: vpst449; CHECK-NEXT: vmaxvt.s8 r0, q0450; CHECK-NEXT: sxtb r0, r0451; CHECK-NEXT: bx lr452entry:453 %0 = zext i8 %a to i32454 %1 = zext i16 %p to i32455 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)456 %3 = tail call i32 @llvm.arm.mve.maxv.predicated.v16i8.v16i1(i32 %0, <16 x i8> %b, i32 0, <16 x i1> %2)457 %4 = trunc i32 %3 to i8458 ret i8 %4459}460 461define arm_aapcs_vfpcc signext i16 @test_vmaxvq_p_s16(i16 signext %a, <8 x i16> %b, i16 zeroext %p) {462; CHECK-LABEL: test_vmaxvq_p_s16:463; CHECK: @ %bb.0: @ %entry464; CHECK-NEXT: vmsr p0, r1465; CHECK-NEXT: vpst466; CHECK-NEXT: vmaxvt.s16 r0, q0467; CHECK-NEXT: sxth r0, r0468; CHECK-NEXT: bx lr469entry:470 %0 = zext i16 %a to i32471 %1 = zext i16 %p to i32472 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)473 %3 = tail call i32 @llvm.arm.mve.maxv.predicated.v8i16.v8i1(i32 %0, <8 x i16> %b, i32 0, <8 x i1> %2)474 %4 = trunc i32 %3 to i16475 ret i16 %4476}477 478define arm_aapcs_vfpcc i32 @test_vmaxvq_p_s32(i32 %a, <4 x i32> %b, i16 zeroext %p) {479; CHECK-LABEL: test_vmaxvq_p_s32:480; CHECK: @ %bb.0: @ %entry481; CHECK-NEXT: vmsr p0, r1482; CHECK-NEXT: vpst483; CHECK-NEXT: vmaxvt.s32 r0, q0484; CHECK-NEXT: bx lr485entry:486 %0 = zext i16 %p to i32487 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)488 %2 = tail call i32 @llvm.arm.mve.maxv.predicated.v4i32.v4i1(i32 %a, <4 x i32> %b, i32 0, <4 x i1> %1)489 ret i32 %2490}491 492define arm_aapcs_vfpcc zeroext i8 @test_vmaxvq_p_u8(i8 zeroext %a, <16 x i8> %b, i16 zeroext %p) {493; CHECK-LABEL: test_vmaxvq_p_u8:494; CHECK: @ %bb.0: @ %entry495; CHECK-NEXT: vmsr p0, r1496; CHECK-NEXT: vpst497; CHECK-NEXT: vmaxvt.u8 r0, q0498; CHECK-NEXT: uxtb r0, r0499; CHECK-NEXT: bx lr500entry:501 %0 = zext i8 %a to i32502 %1 = zext i16 %p to i32503 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)504 %3 = tail call i32 @llvm.arm.mve.maxv.predicated.v16i8.v16i1(i32 %0, <16 x i8> %b, i32 1, <16 x i1> %2)505 %4 = trunc i32 %3 to i8506 ret i8 %4507}508 509define arm_aapcs_vfpcc zeroext i16 @test_vmaxvq_p_u16(i16 zeroext %a, <8 x i16> %b, i16 zeroext %p) {510; CHECK-LABEL: test_vmaxvq_p_u16:511; CHECK: @ %bb.0: @ %entry512; CHECK-NEXT: vmsr p0, r1513; CHECK-NEXT: vpst514; CHECK-NEXT: vmaxvt.u16 r0, q0515; CHECK-NEXT: uxth r0, r0516; CHECK-NEXT: bx lr517entry:518 %0 = zext i16 %a to i32519 %1 = zext i16 %p to i32520 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)521 %3 = tail call i32 @llvm.arm.mve.maxv.predicated.v8i16.v8i1(i32 %0, <8 x i16> %b, i32 1, <8 x i1> %2)522 %4 = trunc i32 %3 to i16523 ret i16 %4524}525 526define arm_aapcs_vfpcc i32 @test_vmaxvq_p_u32(i32 %a, <4 x i32> %b, i16 zeroext %p) {527; CHECK-LABEL: test_vmaxvq_p_u32:528; CHECK: @ %bb.0: @ %entry529; CHECK-NEXT: vmsr p0, r1530; CHECK-NEXT: vpst531; CHECK-NEXT: vmaxvt.u32 r0, q0532; CHECK-NEXT: bx lr533entry:534 %0 = zext i16 %p to i32535 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)536 %2 = tail call i32 @llvm.arm.mve.maxv.predicated.v4i32.v4i1(i32 %a, <4 x i32> %b, i32 1, <4 x i1> %1)537 ret i32 %2538}539 540define arm_aapcs_vfpcc zeroext i8 @test_vminavq_p_s8(i8 zeroext %a, <16 x i8> %b, i16 zeroext %p) {541; CHECK-LABEL: test_vminavq_p_s8:542; CHECK: @ %bb.0: @ %entry543; CHECK-NEXT: vmsr p0, r1544; CHECK-NEXT: vpst545; CHECK-NEXT: vminavt.s8 r0, q0546; CHECK-NEXT: uxtb r0, r0547; CHECK-NEXT: bx lr548entry:549 %0 = zext i8 %a to i32550 %1 = zext i16 %p to i32551 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)552 %3 = tail call i32 @llvm.arm.mve.minav.predicated.v16i8.v16i1(i32 %0, <16 x i8> %b, <16 x i1> %2)553 %4 = trunc i32 %3 to i8554 ret i8 %4555}556 557define arm_aapcs_vfpcc zeroext i16 @test_vminavq_p_s16(i16 zeroext %a, <8 x i16> %b, i16 zeroext %p) {558; CHECK-LABEL: test_vminavq_p_s16:559; CHECK: @ %bb.0: @ %entry560; CHECK-NEXT: vmsr p0, r1561; CHECK-NEXT: vpst562; CHECK-NEXT: vminavt.s16 r0, q0563; CHECK-NEXT: uxth r0, r0564; CHECK-NEXT: bx lr565entry:566 %0 = zext i16 %a to i32567 %1 = zext i16 %p to i32568 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)569 %3 = tail call i32 @llvm.arm.mve.minav.predicated.v8i16.v8i1(i32 %0, <8 x i16> %b, <8 x i1> %2)570 %4 = trunc i32 %3 to i16571 ret i16 %4572}573 574define arm_aapcs_vfpcc i32 @test_vminavq_p_s32(i32 %a, <4 x i32> %b, i16 zeroext %p) {575; CHECK-LABEL: test_vminavq_p_s32:576; CHECK: @ %bb.0: @ %entry577; CHECK-NEXT: vmsr p0, r1578; CHECK-NEXT: vpst579; CHECK-NEXT: vminavt.s32 r0, q0580; CHECK-NEXT: bx lr581entry:582 %0 = zext i16 %p to i32583 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)584 %2 = tail call i32 @llvm.arm.mve.minav.predicated.v4i32.v4i1(i32 %a, <4 x i32> %b, <4 x i1> %1)585 ret i32 %2586}587 588define arm_aapcs_vfpcc zeroext i8 @test_vmaxavq_p_s8(i8 zeroext %a, <16 x i8> %b, i16 zeroext %p) {589; CHECK-LABEL: test_vmaxavq_p_s8:590; CHECK: @ %bb.0: @ %entry591; CHECK-NEXT: vmsr p0, r1592; CHECK-NEXT: vpst593; CHECK-NEXT: vmaxavt.s8 r0, q0594; CHECK-NEXT: uxtb r0, r0595; CHECK-NEXT: bx lr596entry:597 %0 = zext i8 %a to i32598 %1 = zext i16 %p to i32599 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)600 %3 = tail call i32 @llvm.arm.mve.maxav.predicated.v16i8.v16i1(i32 %0, <16 x i8> %b, <16 x i1> %2)601 %4 = trunc i32 %3 to i8602 ret i8 %4603}604 605define arm_aapcs_vfpcc zeroext i16 @test_vmaxavq_p_s16(i16 zeroext %a, <8 x i16> %b, i16 zeroext %p) {606; CHECK-LABEL: test_vmaxavq_p_s16:607; CHECK: @ %bb.0: @ %entry608; CHECK-NEXT: vmsr p0, r1609; CHECK-NEXT: vpst610; CHECK-NEXT: vmaxavt.s16 r0, q0611; CHECK-NEXT: uxth r0, r0612; CHECK-NEXT: bx lr613entry:614 %0 = zext i16 %a to i32615 %1 = zext i16 %p to i32616 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)617 %3 = tail call i32 @llvm.arm.mve.maxav.predicated.v8i16.v8i1(i32 %0, <8 x i16> %b, <8 x i1> %2)618 %4 = trunc i32 %3 to i16619 ret i16 %4620}621 622define arm_aapcs_vfpcc i32 @test_vmaxavq_p_s32(i32 %a, <4 x i32> %b, i16 zeroext %p) {623; CHECK-LABEL: test_vmaxavq_p_s32:624; CHECK: @ %bb.0: @ %entry625; CHECK-NEXT: vmsr p0, r1626; CHECK-NEXT: vpst627; CHECK-NEXT: vmaxavt.s32 r0, q0628; CHECK-NEXT: bx lr629entry:630 %0 = zext i16 %p to i32631 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)632 %2 = tail call i32 @llvm.arm.mve.maxav.predicated.v4i32.v4i1(i32 %a, <4 x i32> %b, <4 x i1> %1)633 ret i32 %2634}635 636define arm_aapcs_vfpcc float @test_vminnmvq_p_f16(float %a.coerce, <8 x half> %b, i16 zeroext %p) {637; CHECK-LABEL: test_vminnmvq_p_f16:638; CHECK: @ %bb.0: @ %entry639; CHECK-NEXT: vmov r1, s0640; CHECK-NEXT: vmsr p0, r0641; CHECK-NEXT: vpst642; CHECK-NEXT: vminnmvt.f16 r1, q1643; CHECK-NEXT: vmov s0, r1644; CHECK-NEXT: vmov.f16 r0, s0645; CHECK-NEXT: vmov s0, r0646; CHECK-NEXT: bx lr647entry:648 %0 = bitcast float %a.coerce to i32649 %tmp.0.extract.trunc = trunc i32 %0 to i16650 %1 = bitcast i16 %tmp.0.extract.trunc to half651 %2 = zext i16 %p to i32652 %3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)653 %4 = tail call half @llvm.arm.mve.minnmv.predicated.f16.v8f16.v8i1(half %1, <8 x half> %b, <8 x i1> %3)654 %5 = bitcast half %4 to i16655 %tmp2.0.insert.ext = zext i16 %5 to i32656 %6 = bitcast i32 %tmp2.0.insert.ext to float657 ret float %6658}659 660define arm_aapcs_vfpcc float @test_vminnmvq_p_f32(float %a, <4 x float> %b, i16 zeroext %p) {661; CHECK-LABEL: test_vminnmvq_p_f32:662; CHECK: @ %bb.0: @ %entry663; CHECK-NEXT: vmsr p0, r0664; CHECK-NEXT: vmov r0, s0665; CHECK-NEXT: vpst666; CHECK-NEXT: vminnmvt.f32 r0, q1667; CHECK-NEXT: vmov s0, r0668; CHECK-NEXT: bx lr669entry:670 %0 = zext i16 %p to i32671 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)672 %2 = tail call float @llvm.arm.mve.minnmv.predicated.f32.v4f32.v4i1(float %a, <4 x float> %b, <4 x i1> %1)673 ret float %2674}675 676define arm_aapcs_vfpcc float @test_vminnmavq_p_f16(float %a.coerce, <8 x half> %b, i16 zeroext %p) {677; CHECK-LABEL: test_vminnmavq_p_f16:678; CHECK: @ %bb.0: @ %entry679; CHECK-NEXT: vmov r1, s0680; CHECK-NEXT: vmsr p0, r0681; CHECK-NEXT: vpst682; CHECK-NEXT: vminnmavt.f16 r1, q1683; CHECK-NEXT: vmov s0, r1684; CHECK-NEXT: vmov.f16 r0, s0685; CHECK-NEXT: vmov s0, r0686; CHECK-NEXT: bx lr687entry:688 %0 = bitcast float %a.coerce to i32689 %tmp.0.extract.trunc = trunc i32 %0 to i16690 %1 = bitcast i16 %tmp.0.extract.trunc to half691 %2 = zext i16 %p to i32692 %3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)693 %4 = tail call half @llvm.arm.mve.minnmav.predicated.f16.v8f16.v8i1(half %1, <8 x half> %b, <8 x i1> %3)694 %5 = bitcast half %4 to i16695 %tmp2.0.insert.ext = zext i16 %5 to i32696 %6 = bitcast i32 %tmp2.0.insert.ext to float697 ret float %6698}699 700define arm_aapcs_vfpcc float @test_vminnmavq_p_f32(float %a, <4 x float> %b, i16 zeroext %p) {701; CHECK-LABEL: test_vminnmavq_p_f32:702; CHECK: @ %bb.0: @ %entry703; CHECK-NEXT: vmsr p0, r0704; CHECK-NEXT: vmov r0, s0705; CHECK-NEXT: vpst706; CHECK-NEXT: vminnmavt.f32 r0, q1707; CHECK-NEXT: vmov s0, r0708; CHECK-NEXT: bx lr709entry:710 %0 = zext i16 %p to i32711 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)712 %2 = tail call float @llvm.arm.mve.minnmav.predicated.f32.v4f32.v4i1(float %a, <4 x float> %b, <4 x i1> %1)713 ret float %2714}715 716define arm_aapcs_vfpcc float @test_vmaxnmvq_p_f16(float %a.coerce, <8 x half> %b, i16 zeroext %p) {717; CHECK-LABEL: test_vmaxnmvq_p_f16:718; CHECK: @ %bb.0: @ %entry719; CHECK-NEXT: vmov r1, s0720; CHECK-NEXT: vmsr p0, r0721; CHECK-NEXT: vpst722; CHECK-NEXT: vmaxnmvt.f16 r1, q1723; CHECK-NEXT: vmov s0, r1724; CHECK-NEXT: vmov.f16 r0, s0725; CHECK-NEXT: vmov s0, r0726; CHECK-NEXT: bx lr727entry:728 %0 = bitcast float %a.coerce to i32729 %tmp.0.extract.trunc = trunc i32 %0 to i16730 %1 = bitcast i16 %tmp.0.extract.trunc to half731 %2 = zext i16 %p to i32732 %3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)733 %4 = tail call half @llvm.arm.mve.maxnmv.predicated.f16.v8f16.v8i1(half %1, <8 x half> %b, <8 x i1> %3)734 %5 = bitcast half %4 to i16735 %tmp2.0.insert.ext = zext i16 %5 to i32736 %6 = bitcast i32 %tmp2.0.insert.ext to float737 ret float %6738}739 740define arm_aapcs_vfpcc float @test_vmaxnmvq_p_f32(float %a, <4 x float> %b, i16 zeroext %p) {741; CHECK-LABEL: test_vmaxnmvq_p_f32:742; CHECK: @ %bb.0: @ %entry743; CHECK-NEXT: vmsr p0, r0744; CHECK-NEXT: vmov r0, s0745; CHECK-NEXT: vpst746; CHECK-NEXT: vmaxnmvt.f32 r0, q1747; CHECK-NEXT: vmov s0, r0748; CHECK-NEXT: bx lr749entry:750 %0 = zext i16 %p to i32751 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)752 %2 = tail call float @llvm.arm.mve.maxnmv.predicated.f32.v4f32.v4i1(float %a, <4 x float> %b, <4 x i1> %1)753 ret float %2754}755 756define arm_aapcs_vfpcc float @test_vmaxnmavq_p_f16(float %a.coerce, <8 x half> %b, i16 zeroext %p) {757; CHECK-LABEL: test_vmaxnmavq_p_f16:758; CHECK: @ %bb.0: @ %entry759; CHECK-NEXT: vmov r1, s0760; CHECK-NEXT: vmsr p0, r0761; CHECK-NEXT: vpst762; CHECK-NEXT: vmaxnmavt.f16 r1, q1763; CHECK-NEXT: vmov s0, r1764; CHECK-NEXT: vmov.f16 r0, s0765; CHECK-NEXT: vmov s0, r0766; CHECK-NEXT: bx lr767entry:768 %0 = bitcast float %a.coerce to i32769 %tmp.0.extract.trunc = trunc i32 %0 to i16770 %1 = bitcast i16 %tmp.0.extract.trunc to half771 %2 = zext i16 %p to i32772 %3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)773 %4 = tail call half @llvm.arm.mve.maxnmav.predicated.f16.v8f16.v8i1(half %1, <8 x half> %b, <8 x i1> %3)774 %5 = bitcast half %4 to i16775 %tmp2.0.insert.ext = zext i16 %5 to i32776 %6 = bitcast i32 %tmp2.0.insert.ext to float777 ret float %6778}779 780define arm_aapcs_vfpcc float @test_vmaxnmavq_p_f32(float %a, <4 x float> %b, i16 zeroext %p) {781; CHECK-LABEL: test_vmaxnmavq_p_f32:782; CHECK: @ %bb.0: @ %entry783; CHECK-NEXT: vmsr p0, r0784; CHECK-NEXT: vmov r0, s0785; CHECK-NEXT: vpst786; CHECK-NEXT: vmaxnmavt.f32 r0, q1787; CHECK-NEXT: vmov s0, r0788; CHECK-NEXT: bx lr789entry:790 %0 = zext i16 %p to i32791 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)792 %2 = tail call float @llvm.arm.mve.maxnmav.predicated.f32.v4f32.v4i1(float %a, <4 x float> %b, <4 x i1> %1)793 ret float %2794}795 796declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)797declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)798declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)799 800declare i32 @llvm.arm.mve.minv.v16i8(i32, <16 x i8>, i32)801declare i32 @llvm.arm.mve.minv.v8i16(i32, <8 x i16>, i32)802declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32)803declare i32 @llvm.arm.mve.maxv.v16i8(i32, <16 x i8>, i32)804declare i32 @llvm.arm.mve.maxv.v8i16(i32, <8 x i16>, i32)805declare i32 @llvm.arm.mve.maxv.v4i32(i32, <4 x i32>, i32)806declare i32 @llvm.arm.mve.minav.v16i8(i32, <16 x i8>)807declare i32 @llvm.arm.mve.minav.v8i16(i32, <8 x i16>)808declare i32 @llvm.arm.mve.minav.v4i32(i32, <4 x i32>)809declare i32 @llvm.arm.mve.maxav.v16i8(i32, <16 x i8>)810declare i32 @llvm.arm.mve.maxav.v8i16(i32, <8 x i16>)811declare i32 @llvm.arm.mve.maxav.v4i32(i32, <4 x i32>)812declare i32 @llvm.arm.mve.minv.predicated.v16i8.v16i1(i32, <16 x i8>, i32, <16 x i1>)813declare i32 @llvm.arm.mve.minv.predicated.v8i16.v8i1(i32, <8 x i16>, i32, <8 x i1>)814declare i32 @llvm.arm.mve.minv.predicated.v4i32.v4i1(i32, <4 x i32>, i32, <4 x i1>)815declare i32 @llvm.arm.mve.maxv.predicated.v16i8.v16i1(i32, <16 x i8>, i32, <16 x i1>)816declare i32 @llvm.arm.mve.maxv.predicated.v8i16.v8i1(i32, <8 x i16>, i32, <8 x i1>)817declare i32 @llvm.arm.mve.maxv.predicated.v4i32.v4i1(i32, <4 x i32>, i32, <4 x i1>)818declare i32 @llvm.arm.mve.minav.predicated.v16i8.v16i1(i32, <16 x i8>, <16 x i1>)819declare i32 @llvm.arm.mve.minav.predicated.v8i16.v8i1(i32, <8 x i16>, <8 x i1>)820declare i32 @llvm.arm.mve.minav.predicated.v4i32.v4i1(i32, <4 x i32>, <4 x i1>)821declare i32 @llvm.arm.mve.maxav.predicated.v16i8.v16i1(i32, <16 x i8>, <16 x i1>)822declare i32 @llvm.arm.mve.maxav.predicated.v8i16.v8i1(i32, <8 x i16>, <8 x i1>)823declare i32 @llvm.arm.mve.maxav.predicated.v4i32.v4i1(i32, <4 x i32>, <4 x i1>)824 825declare half @llvm.arm.mve.minnmv.f16.v8f16(half, <8 x half>)826declare half @llvm.arm.mve.minnmav.f16.v8f16(half, <8 x half>)827declare half @llvm.arm.mve.maxnmv.f16.v8f16(half, <8 x half>)828declare half @llvm.arm.mve.maxnmav.f16.v8f16(half, <8 x half>)829declare half @llvm.arm.mve.minnmv.predicated.f16.v8f16.v8i1(half, <8 x half>, <8 x i1>)830declare half @llvm.arm.mve.minnmav.predicated.f16.v8f16.v8i1(half, <8 x half>, <8 x i1>)831declare half @llvm.arm.mve.maxnmv.predicated.f16.v8f16.v8i1(half, <8 x half>, <8 x i1>)832declare half @llvm.arm.mve.maxnmav.predicated.f16.v8f16.v8i1(half, <8 x half>, <8 x i1>)833 834declare float @llvm.arm.mve.minnmv.f32.v4f32(float, <4 x float>)835declare float @llvm.arm.mve.minnmav.f32.v4f32(float, <4 x float>)836declare float @llvm.arm.mve.maxnmv.f32.v4f32(float, <4 x float>)837declare float @llvm.arm.mve.maxnmav.f32.v4f32(float, <4 x float>)838declare float @llvm.arm.mve.minnmv.predicated.f32.v4f32.v4i1(float, <4 x float>, <4 x i1>)839declare float @llvm.arm.mve.minnmav.predicated.f32.v4f32.v4i1(float, <4 x float>, <4 x i1>)840declare float @llvm.arm.mve.maxnmv.predicated.f32.v4f32.v4i1(float, <4 x float>, <4 x i1>)841declare float @llvm.arm.mve.maxnmav.predicated.f32.v4f32.v4i1(float, <4 x float>, <4 x i1>)842