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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)5declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)6declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)7 8declare i32 @llvm.arm.mve.vmldava.v16i8(i32, i32, i32, i32, <16 x i8>, <16 x i8>)9declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>)10declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>)11 12declare i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32, i32, i32, i32, <16 x i8>, <16 x i8>, <16 x i1>)13declare i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32, i32, i32, i32, <8 x i16>, <8 x i16>, <8 x i1>)14declare i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32, i32, i32, i32, <4 x i32>, <4 x i32>, <4 x i1>)15 16define arm_aapcs_vfpcc i32 @test_vmladavaq_s8(i32 %a, <16 x i8> %b, <16 x i8> %c) {17; CHECK-LABEL: test_vmladavaq_s8:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vmlava.s8 r0, q0, q120; CHECK-NEXT: bx lr21entry:22 %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 %a, <16 x i8> %b, <16 x i8> %c)23 ret i32 %024}25 26define arm_aapcs_vfpcc i32 @test_vmladavaq_s16(i32 %a, <8 x i16> %b, <8 x i16> %c) {27; CHECK-LABEL: test_vmladavaq_s16:28; CHECK: @ %bb.0: @ %entry29; CHECK-NEXT: vmlava.s16 r0, q0, q130; CHECK-NEXT: bx lr31entry:32 %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 %a, <8 x i16> %b, <8 x i16> %c)33 ret i32 %034}35 36define arm_aapcs_vfpcc i32 @test_vmladavaq_s32(i32 %a, <4 x i32> %b, <4 x i32> %c) {37; CHECK-LABEL: test_vmladavaq_s32:38; CHECK: @ %bb.0: @ %entry39; CHECK-NEXT: vmlava.s32 r0, q0, q140; CHECK-NEXT: bx lr41entry:42 %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %a, <4 x i32> %b, <4 x i32> %c)43 ret i32 %044}45 46define arm_aapcs_vfpcc i32 @test_vmladavaq_u8(i32 %a, <16 x i8> %b, <16 x i8> %c) {47; CHECK-LABEL: test_vmladavaq_u8:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: vmlava.u8 r0, q0, q150; CHECK-NEXT: bx lr51entry:52 %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 %a, <16 x i8> %b, <16 x i8> %c)53 ret i32 %054}55 56define arm_aapcs_vfpcc i32 @test_vmladavaq_u16(i32 %a, <8 x i16> %b, <8 x i16> %c) {57; CHECK-LABEL: test_vmladavaq_u16:58; CHECK: @ %bb.0: @ %entry59; CHECK-NEXT: vmlava.u16 r0, q0, q160; CHECK-NEXT: bx lr61entry:62 %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 %a, <8 x i16> %b, <8 x i16> %c)63 ret i32 %064}65 66define arm_aapcs_vfpcc i32 @test_vmladavaq_u32(i32 %a, <4 x i32> %b, <4 x i32> %c) {67; CHECK-LABEL: test_vmladavaq_u32:68; CHECK: @ %bb.0: @ %entry69; CHECK-NEXT: vmlava.u32 r0, q0, q170; CHECK-NEXT: bx lr71entry:72 %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 %a, <4 x i32> %b, <4 x i32> %c)73 ret i32 %074}75 76define arm_aapcs_vfpcc i32 @test_vmladavaxq_s8(i32 %a, <16 x i8> %b, <16 x i8> %c) {77; CHECK-LABEL: test_vmladavaxq_s8:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vmladavax.s8 r0, q0, q180; CHECK-NEXT: bx lr81entry:82 %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 1, i32 %a, <16 x i8> %b, <16 x i8> %c)83 ret i32 %084}85 86define arm_aapcs_vfpcc i32 @test_vmladavaxq_s16(i32 %a, <8 x i16> %b, <8 x i16> %c) {87; CHECK-LABEL: test_vmladavaxq_s16:88; CHECK: @ %bb.0: @ %entry89; CHECK-NEXT: vmladavax.s16 r0, q0, q190; CHECK-NEXT: bx lr91entry:92 %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 1, i32 %a, <8 x i16> %b, <8 x i16> %c)93 ret i32 %094}95 96define arm_aapcs_vfpcc i32 @test_vmladavaxq_s32(i32 %a, <4 x i32> %b, <4 x i32> %c) {97; CHECK-LABEL: test_vmladavaxq_s32:98; CHECK: @ %bb.0: @ %entry99; CHECK-NEXT: vmladavax.s32 r0, q0, q1100; CHECK-NEXT: bx lr101entry:102 %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 1, i32 %a, <4 x i32> %b, <4 x i32> %c)103 ret i32 %0104}105 106define arm_aapcs_vfpcc i32 @test_vmlsdavaq_s8(i32 %a, <16 x i8> %b, <16 x i8> %c) {107; CHECK-LABEL: test_vmlsdavaq_s8:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: vmlsdava.s8 r0, q0, q1110; CHECK-NEXT: bx lr111entry:112 %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 %a, <16 x i8> %b, <16 x i8> %c)113 ret i32 %0114}115 116define arm_aapcs_vfpcc i32 @test_vmlsdavaq_s16(i32 %a, <8 x i16> %b, <8 x i16> %c) {117; CHECK-LABEL: test_vmlsdavaq_s16:118; CHECK: @ %bb.0: @ %entry119; CHECK-NEXT: vmlsdava.s16 r0, q0, q1120; CHECK-NEXT: bx lr121entry:122 %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 %a, <8 x i16> %b, <8 x i16> %c)123 ret i32 %0124}125 126define arm_aapcs_vfpcc i32 @test_vmlsdavaq_s32(i32 %a, <4 x i32> %b, <4 x i32> %c) {127; CHECK-LABEL: test_vmlsdavaq_s32:128; CHECK: @ %bb.0: @ %entry129; CHECK-NEXT: vmlsdava.s32 r0, q0, q1130; CHECK-NEXT: bx lr131entry:132 %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 %a, <4 x i32> %b, <4 x i32> %c)133 ret i32 %0134}135 136define arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s8(i32 %a, <16 x i8> %b, <16 x i8> %c) {137; CHECK-LABEL: test_vmlsdavaxq_s8:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: vmlsdavax.s8 r0, q0, q1140; CHECK-NEXT: bx lr141entry:142 %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 1, i32 %a, <16 x i8> %b, <16 x i8> %c)143 ret i32 %0144}145 146define arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s16(i32 %a, <8 x i16> %b, <8 x i16> %c) {147; CHECK-LABEL: test_vmlsdavaxq_s16:148; CHECK: @ %bb.0: @ %entry149; CHECK-NEXT: vmlsdavax.s16 r0, q0, q1150; CHECK-NEXT: bx lr151entry:152 %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 1, i32 %a, <8 x i16> %b, <8 x i16> %c)153 ret i32 %0154}155 156define arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s32(i32 %a, <4 x i32> %b, <4 x i32> %c) {157; CHECK-LABEL: test_vmlsdavaxq_s32:158; CHECK: @ %bb.0: @ %entry159; CHECK-NEXT: vmlsdavax.s32 r0, q0, q1160; CHECK-NEXT: bx lr161entry:162 %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 1, i32 %a, <4 x i32> %b, <4 x i32> %c)163 ret i32 %0164}165 166define arm_aapcs_vfpcc i32 @test_vmladavaq_p_s8(i32 %a, <16 x i8> %b, <16 x i8> %c, i16 zeroext %p) {167; CHECK-LABEL: test_vmladavaq_p_s8:168; CHECK: @ %bb.0: @ %entry169; CHECK-NEXT: vmsr p0, r1170; CHECK-NEXT: vpst171; CHECK-NEXT: vmlavat.s8 r0, q0, q1172; CHECK-NEXT: bx lr173entry:174 %0 = zext i16 %p to i32175 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)176 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 0, i32 0, i32 0, i32 %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %1)177 ret i32 %2178}179 180define arm_aapcs_vfpcc i32 @test_vmladavaq_p_s16(i32 %a, <8 x i16> %b, <8 x i16> %c, i16 zeroext %p) {181; CHECK-LABEL: test_vmladavaq_p_s16:182; CHECK: @ %bb.0: @ %entry183; CHECK-NEXT: vmsr p0, r1184; CHECK-NEXT: vpst185; CHECK-NEXT: vmlavat.s16 r0, q0, q1186; CHECK-NEXT: bx lr187entry:188 %0 = zext i16 %p to i32189 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)190 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32 0, i32 0, i32 0, i32 %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %1)191 ret i32 %2192}193 194define arm_aapcs_vfpcc i32 @test_vmladavaq_p_s32(i32 %a, <4 x i32> %b, <4 x i32> %c, i16 zeroext %p) {195; CHECK-LABEL: test_vmladavaq_p_s32:196; CHECK: @ %bb.0: @ %entry197; CHECK-NEXT: vmsr p0, r1198; CHECK-NEXT: vpst199; CHECK-NEXT: vmlavat.s32 r0, q0, q1200; CHECK-NEXT: bx lr201entry:202 %0 = zext i16 %p to i32203 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)204 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 0, i32 %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %1)205 ret i32 %2206}207 208define arm_aapcs_vfpcc i32 @test_vmladavaq_p_u8(i32 %a, <16 x i8> %b, <16 x i8> %c, i16 zeroext %p) {209; CHECK-LABEL: test_vmladavaq_p_u8:210; CHECK: @ %bb.0: @ %entry211; CHECK-NEXT: vmsr p0, r1212; CHECK-NEXT: vpst213; CHECK-NEXT: vmlavat.u8 r0, q0, q1214; CHECK-NEXT: bx lr215entry:216 %0 = zext i16 %p to i32217 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)218 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 1, i32 0, i32 0, i32 %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %1)219 ret i32 %2220}221 222define arm_aapcs_vfpcc i32 @test_vmladavaq_p_u16(i32 %a, <8 x i16> %b, <8 x i16> %c, i16 zeroext %p) {223; CHECK-LABEL: test_vmladavaq_p_u16:224; CHECK: @ %bb.0: @ %entry225; CHECK-NEXT: vmsr p0, r1226; CHECK-NEXT: vpst227; CHECK-NEXT: vmlavat.u16 r0, q0, q1228; CHECK-NEXT: bx lr229entry:230 %0 = zext i16 %p to i32231 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)232 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32 1, i32 0, i32 0, i32 %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %1)233 ret i32 %2234}235 236define arm_aapcs_vfpcc i32 @test_vmladavaq_p_u32(i32 %a, <4 x i32> %b, <4 x i32> %c, i16 zeroext %p) {237; CHECK-LABEL: test_vmladavaq_p_u32:238; CHECK: @ %bb.0: @ %entry239; CHECK-NEXT: vmsr p0, r1240; CHECK-NEXT: vpst241; CHECK-NEXT: vmlavat.u32 r0, q0, q1242; CHECK-NEXT: bx lr243entry:244 %0 = zext i16 %p to i32245 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)246 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 1, i32 0, i32 0, i32 %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %1)247 ret i32 %2248}249 250define arm_aapcs_vfpcc i32 @test_vmladavaxq_p_s8(i32 %a, <16 x i8> %b, <16 x i8> %c, i16 zeroext %p) {251; CHECK-LABEL: test_vmladavaxq_p_s8:252; CHECK: @ %bb.0: @ %entry253; CHECK-NEXT: vmsr p0, r1254; CHECK-NEXT: vpst255; CHECK-NEXT: vmladavaxt.s8 r0, q0, q1256; CHECK-NEXT: bx lr257entry:258 %0 = zext i16 %p to i32259 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)260 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 0, i32 0, i32 1, i32 %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %1)261 ret i32 %2262}263 264define arm_aapcs_vfpcc i32 @test_vmladavaxq_p_s16(i32 %a, <8 x i16> %b, <8 x i16> %c, i16 zeroext %p) {265; CHECK-LABEL: test_vmladavaxq_p_s16:266; CHECK: @ %bb.0: @ %entry267; CHECK-NEXT: vmsr p0, r1268; CHECK-NEXT: vpst269; CHECK-NEXT: vmladavaxt.s16 r0, q0, q1270; CHECK-NEXT: bx lr271entry:272 %0 = zext i16 %p to i32273 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)274 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32 0, i32 0, i32 1, i32 %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %1)275 ret i32 %2276}277 278define arm_aapcs_vfpcc i32 @test_vmladavaxq_p_s32(i32 %a, <4 x i32> %b, <4 x i32> %c, i16 zeroext %p) {279; CHECK-LABEL: test_vmladavaxq_p_s32:280; CHECK: @ %bb.0: @ %entry281; CHECK-NEXT: vmsr p0, r1282; CHECK-NEXT: vpst283; CHECK-NEXT: vmladavaxt.s32 r0, q0, q1284; CHECK-NEXT: bx lr285entry:286 %0 = zext i16 %p to i32287 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)288 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 1, i32 %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %1)289 ret i32 %2290}291 292define arm_aapcs_vfpcc i32 @test_vmlsdavaq_p_s8(i32 %a, <16 x i8> %b, <16 x i8> %c, i16 zeroext %p) {293; CHECK-LABEL: test_vmlsdavaq_p_s8:294; CHECK: @ %bb.0: @ %entry295; CHECK-NEXT: vmsr p0, r1296; CHECK-NEXT: vpst297; CHECK-NEXT: vmlsdavat.s8 r0, q0, q1298; CHECK-NEXT: bx lr299entry:300 %0 = zext i16 %p to i32301 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)302 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 0, i32 1, i32 0, i32 %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %1)303 ret i32 %2304}305 306define arm_aapcs_vfpcc i32 @test_vmlsdavaq_p_s16(i32 %a, <8 x i16> %b, <8 x i16> %c, i16 zeroext %p) {307; CHECK-LABEL: test_vmlsdavaq_p_s16:308; CHECK: @ %bb.0: @ %entry309; CHECK-NEXT: vmsr p0, r1310; CHECK-NEXT: vpst311; CHECK-NEXT: vmlsdavat.s16 r0, q0, q1312; CHECK-NEXT: bx lr313entry:314 %0 = zext i16 %p to i32315 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)316 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32 0, i32 1, i32 0, i32 %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %1)317 ret i32 %2318}319 320define arm_aapcs_vfpcc i32 @test_vmlsdavaq_p_s32(i32 %a, <4 x i32> %b, <4 x i32> %c, i16 zeroext %p) {321; CHECK-LABEL: test_vmlsdavaq_p_s32:322; CHECK: @ %bb.0: @ %entry323; CHECK-NEXT: vmsr p0, r1324; CHECK-NEXT: vpst325; CHECK-NEXT: vmlsdavat.s32 r0, q0, q1326; CHECK-NEXT: bx lr327entry:328 %0 = zext i16 %p to i32329 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)330 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 1, i32 0, i32 %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %1)331 ret i32 %2332}333 334define arm_aapcs_vfpcc i32 @test_vmlsdavaxq_p_s8(i32 %a, <16 x i8> %b, <16 x i8> %c, i16 zeroext %p) {335; CHECK-LABEL: test_vmlsdavaxq_p_s8:336; CHECK: @ %bb.0: @ %entry337; CHECK-NEXT: vmsr p0, r1338; CHECK-NEXT: vpst339; CHECK-NEXT: vmlsdavaxt.s8 r0, q0, q1340; CHECK-NEXT: bx lr341entry:342 %0 = zext i16 %p to i32343 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)344 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 0, i32 1, i32 1, i32 %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %1)345 ret i32 %2346}347 348define arm_aapcs_vfpcc i32 @test_vmlsdavaxq_p_s16(i32 %a, <8 x i16> %b, <8 x i16> %c, i16 zeroext %p) {349; CHECK-LABEL: test_vmlsdavaxq_p_s16:350; CHECK: @ %bb.0: @ %entry351; CHECK-NEXT: vmsr p0, r1352; CHECK-NEXT: vpst353; CHECK-NEXT: vmlsdavaxt.s16 r0, q0, q1354; CHECK-NEXT: bx lr355entry:356 %0 = zext i16 %p to i32357 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)358 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32 0, i32 1, i32 1, i32 %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %1)359 ret i32 %2360}361 362define arm_aapcs_vfpcc i32 @test_vmlsdavaxq_p_s32(i32 %a, <4 x i32> %b, <4 x i32> %c, i16 zeroext %p) {363; CHECK-LABEL: test_vmlsdavaxq_p_s32:364; CHECK: @ %bb.0: @ %entry365; CHECK-NEXT: vmsr p0, r1366; CHECK-NEXT: vpst367; CHECK-NEXT: vmlsdavaxt.s32 r0, q0, q1368; CHECK-NEXT: bx lr369entry:370 %0 = zext i16 %p to i32371 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)372 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 1, i32 1, i32 %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %1)373 ret i32 %2374}375 376define arm_aapcs_vfpcc i32 @test_vmladavq_s8(<16 x i8> %a, <16 x i8> %b) {377; CHECK-LABEL: test_vmladavq_s8:378; CHECK: @ %bb.0: @ %entry379; CHECK-NEXT: vmlav.s8 r0, q0, q1380; CHECK-NEXT: bx lr381entry:382 %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 0, <16 x i8> %a, <16 x i8> %b)383 ret i32 %0384}385 386define arm_aapcs_vfpcc i32 @test_vmladavq_s16(<8 x i16> %a, <8 x i16> %b) {387; CHECK-LABEL: test_vmladavq_s16:388; CHECK: @ %bb.0: @ %entry389; CHECK-NEXT: vmlav.s16 r0, q0, q1390; CHECK-NEXT: bx lr391entry:392 %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 0, <8 x i16> %a, <8 x i16> %b)393 ret i32 %0394}395 396define arm_aapcs_vfpcc i32 @test_vmladavq_s32(<4 x i32> %a, <4 x i32> %b) {397; CHECK-LABEL: test_vmladavq_s32:398; CHECK: @ %bb.0: @ %entry399; CHECK-NEXT: vmlav.s32 r0, q0, q1400; CHECK-NEXT: bx lr401entry:402 %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 0, <4 x i32> %a, <4 x i32> %b)403 ret i32 %0404}405 406define arm_aapcs_vfpcc i32 @test_vmladavq_u8(<16 x i8> %a, <16 x i8> %b) {407; CHECK-LABEL: test_vmladavq_u8:408; CHECK: @ %bb.0: @ %entry409; CHECK-NEXT: vmlav.u8 r0, q0, q1410; CHECK-NEXT: bx lr411entry:412 %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 0, <16 x i8> %a, <16 x i8> %b)413 ret i32 %0414}415 416define arm_aapcs_vfpcc i32 @test_vmladavq_u16(<8 x i16> %a, <8 x i16> %b) {417; CHECK-LABEL: test_vmladavq_u16:418; CHECK: @ %bb.0: @ %entry419; CHECK-NEXT: vmlav.u16 r0, q0, q1420; CHECK-NEXT: bx lr421entry:422 %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 0, <8 x i16> %a, <8 x i16> %b)423 ret i32 %0424}425 426define arm_aapcs_vfpcc i32 @test_vmladavq_u32(<4 x i32> %a, <4 x i32> %b) {427; CHECK-LABEL: test_vmladavq_u32:428; CHECK: @ %bb.0: @ %entry429; CHECK-NEXT: vmlav.u32 r0, q0, q1430; CHECK-NEXT: bx lr431entry:432 %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 0, <4 x i32> %a, <4 x i32> %b)433 ret i32 %0434}435 436define arm_aapcs_vfpcc i32 @test_vmladavxq_s8(<16 x i8> %a, <16 x i8> %b) {437; CHECK-LABEL: test_vmladavxq_s8:438; CHECK: @ %bb.0: @ %entry439; CHECK-NEXT: vmladavx.s8 r0, q0, q1440; CHECK-NEXT: bx lr441entry:442 %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 1, i32 0, <16 x i8> %a, <16 x i8> %b)443 ret i32 %0444}445 446define arm_aapcs_vfpcc i32 @test_vmladavxq_s16(<8 x i16> %a, <8 x i16> %b) {447; CHECK-LABEL: test_vmladavxq_s16:448; CHECK: @ %bb.0: @ %entry449; CHECK-NEXT: vmladavx.s16 r0, q0, q1450; CHECK-NEXT: bx lr451entry:452 %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 1, i32 0, <8 x i16> %a, <8 x i16> %b)453 ret i32 %0454}455 456define arm_aapcs_vfpcc i32 @test_vmladavxq_s32(<4 x i32> %a, <4 x i32> %b) {457; CHECK-LABEL: test_vmladavxq_s32:458; CHECK: @ %bb.0: @ %entry459; CHECK-NEXT: vmladavx.s32 r0, q0, q1460; CHECK-NEXT: bx lr461entry:462 %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 1, i32 0, <4 x i32> %a, <4 x i32> %b)463 ret i32 %0464}465 466define arm_aapcs_vfpcc i32 @test_vmlsdavq_s8(<16 x i8> %a, <16 x i8> %b) {467; CHECK-LABEL: test_vmlsdavq_s8:468; CHECK: @ %bb.0: @ %entry469; CHECK-NEXT: vmlsdav.s8 r0, q0, q1470; CHECK-NEXT: bx lr471entry:472 %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 0, <16 x i8> %a, <16 x i8> %b)473 ret i32 %0474}475 476define arm_aapcs_vfpcc i32 @test_vmlsdavq_s16(<8 x i16> %a, <8 x i16> %b) {477; CHECK-LABEL: test_vmlsdavq_s16:478; CHECK: @ %bb.0: @ %entry479; CHECK-NEXT: vmlsdav.s16 r0, q0, q1480; CHECK-NEXT: bx lr481entry:482 %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 0, <8 x i16> %a, <8 x i16> %b)483 ret i32 %0484}485 486define arm_aapcs_vfpcc i32 @test_vmlsdavq_s32(<4 x i32> %a, <4 x i32> %b) {487; CHECK-LABEL: test_vmlsdavq_s32:488; CHECK: @ %bb.0: @ %entry489; CHECK-NEXT: vmlsdav.s32 r0, q0, q1490; CHECK-NEXT: bx lr491entry:492 %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 0, <4 x i32> %a, <4 x i32> %b)493 ret i32 %0494}495 496define arm_aapcs_vfpcc i32 @test_vmlsdavxq_s8(<16 x i8> %a, <16 x i8> %b) {497; CHECK-LABEL: test_vmlsdavxq_s8:498; CHECK: @ %bb.0: @ %entry499; CHECK-NEXT: vmlsdavx.s8 r0, q0, q1500; CHECK-NEXT: bx lr501entry:502 %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 1, i32 0, <16 x i8> %a, <16 x i8> %b)503 ret i32 %0504}505 506define arm_aapcs_vfpcc i32 @test_vmlsdavxq_s16(<8 x i16> %a, <8 x i16> %b) {507; CHECK-LABEL: test_vmlsdavxq_s16:508; CHECK: @ %bb.0: @ %entry509; CHECK-NEXT: vmlsdavx.s16 r0, q0, q1510; CHECK-NEXT: bx lr511entry:512 %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 1, i32 0, <8 x i16> %a, <8 x i16> %b)513 ret i32 %0514}515 516define arm_aapcs_vfpcc i32 @test_vmlsdavxq_s32(<4 x i32> %a, <4 x i32> %b) {517; CHECK-LABEL: test_vmlsdavxq_s32:518; CHECK: @ %bb.0: @ %entry519; CHECK-NEXT: vmlsdavx.s32 r0, q0, q1520; CHECK-NEXT: bx lr521entry:522 %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 1, i32 0, <4 x i32> %a, <4 x i32> %b)523 ret i32 %0524}525 526define arm_aapcs_vfpcc i32 @test_vmladavq_p_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {527; CHECK-LABEL: test_vmladavq_p_s8:528; CHECK: @ %bb.0: @ %entry529; CHECK-NEXT: vmsr p0, r0530; CHECK-NEXT: vpst531; CHECK-NEXT: vmlavt.s8 r0, q0, q1532; CHECK-NEXT: bx lr533entry:534 %0 = zext i16 %p to i32535 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)536 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 0, i32 0, i32 0, i32 0, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)537 ret i32 %2538}539 540define arm_aapcs_vfpcc i32 @test_vmladavq_p_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {541; CHECK-LABEL: test_vmladavq_p_s16:542; CHECK: @ %bb.0: @ %entry543; CHECK-NEXT: vmsr p0, r0544; CHECK-NEXT: vpst545; CHECK-NEXT: vmlavt.s16 r0, q0, q1546; CHECK-NEXT: bx lr547entry:548 %0 = zext i16 %p to i32549 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)550 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32 0, i32 0, i32 0, i32 0, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)551 ret i32 %2552}553 554define arm_aapcs_vfpcc i32 @test_vmladavq_p_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {555; CHECK-LABEL: test_vmladavq_p_s32:556; CHECK: @ %bb.0: @ %entry557; CHECK-NEXT: vmsr p0, r0558; CHECK-NEXT: vpst559; CHECK-NEXT: vmlavt.s32 r0, q0, q1560; CHECK-NEXT: bx lr561entry:562 %0 = zext i16 %p to i32563 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)564 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 0, i32 0, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)565 ret i32 %2566}567 568define arm_aapcs_vfpcc i32 @test_vmladavq_p_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {569; CHECK-LABEL: test_vmladavq_p_u8:570; CHECK: @ %bb.0: @ %entry571; CHECK-NEXT: vmsr p0, r0572; CHECK-NEXT: vpst573; CHECK-NEXT: vmlavt.u8 r0, q0, q1574; CHECK-NEXT: bx lr575entry:576 %0 = zext i16 %p to i32577 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)578 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 1, i32 0, i32 0, i32 0, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)579 ret i32 %2580}581 582define arm_aapcs_vfpcc i32 @test_vmladavq_p_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {583; CHECK-LABEL: test_vmladavq_p_u16:584; CHECK: @ %bb.0: @ %entry585; CHECK-NEXT: vmsr p0, r0586; CHECK-NEXT: vpst587; CHECK-NEXT: vmlavt.u16 r0, q0, q1588; CHECK-NEXT: bx lr589entry:590 %0 = zext i16 %p to i32591 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)592 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32 1, i32 0, i32 0, i32 0, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)593 ret i32 %2594}595 596define arm_aapcs_vfpcc i32 @test_vmladavq_p_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {597; CHECK-LABEL: test_vmladavq_p_u32:598; CHECK: @ %bb.0: @ %entry599; CHECK-NEXT: vmsr p0, r0600; CHECK-NEXT: vpst601; CHECK-NEXT: vmlavt.u32 r0, q0, q1602; CHECK-NEXT: bx lr603entry:604 %0 = zext i16 %p to i32605 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)606 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 1, i32 0, i32 0, i32 0, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)607 ret i32 %2608}609 610define arm_aapcs_vfpcc i32 @test_vmladavxq_p_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {611; CHECK-LABEL: test_vmladavxq_p_s8:612; CHECK: @ %bb.0: @ %entry613; CHECK-NEXT: vmsr p0, r0614; CHECK-NEXT: vpst615; CHECK-NEXT: vmladavxt.s8 r0, q0, q1616; CHECK-NEXT: bx lr617entry:618 %0 = zext i16 %p to i32619 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)620 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 0, i32 0, i32 1, i32 0, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)621 ret i32 %2622}623 624define arm_aapcs_vfpcc i32 @test_vmladavxq_p_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {625; CHECK-LABEL: test_vmladavxq_p_s16:626; CHECK: @ %bb.0: @ %entry627; CHECK-NEXT: vmsr p0, r0628; CHECK-NEXT: vpst629; CHECK-NEXT: vmladavxt.s16 r0, q0, q1630; CHECK-NEXT: bx lr631entry:632 %0 = zext i16 %p to i32633 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)634 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32 0, i32 0, i32 1, i32 0, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)635 ret i32 %2636}637 638define arm_aapcs_vfpcc i32 @test_vmladavxq_p_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {639; CHECK-LABEL: test_vmladavxq_p_s32:640; CHECK: @ %bb.0: @ %entry641; CHECK-NEXT: vmsr p0, r0642; CHECK-NEXT: vpst643; CHECK-NEXT: vmladavxt.s32 r0, q0, q1644; CHECK-NEXT: bx lr645entry:646 %0 = zext i16 %p to i32647 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)648 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 1, i32 0, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)649 ret i32 %2650}651 652define arm_aapcs_vfpcc i32 @test_vmlsdavq_p_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {653; CHECK-LABEL: test_vmlsdavq_p_s8:654; CHECK: @ %bb.0: @ %entry655; CHECK-NEXT: vmsr p0, r0656; CHECK-NEXT: vpst657; CHECK-NEXT: vmlsdavt.s8 r0, q0, q1658; CHECK-NEXT: bx lr659entry:660 %0 = zext i16 %p to i32661 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)662 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 0, i32 1, i32 0, i32 0, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)663 ret i32 %2664}665 666define arm_aapcs_vfpcc i32 @test_vmlsdavq_p_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {667; CHECK-LABEL: test_vmlsdavq_p_s16:668; CHECK: @ %bb.0: @ %entry669; CHECK-NEXT: vmsr p0, r0670; CHECK-NEXT: vpst671; CHECK-NEXT: vmlsdavt.s16 r0, q0, q1672; CHECK-NEXT: bx lr673entry:674 %0 = zext i16 %p to i32675 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)676 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32 0, i32 1, i32 0, i32 0, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)677 ret i32 %2678}679 680define arm_aapcs_vfpcc i32 @test_vmlsdavq_p_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {681; CHECK-LABEL: test_vmlsdavq_p_s32:682; CHECK: @ %bb.0: @ %entry683; CHECK-NEXT: vmsr p0, r0684; CHECK-NEXT: vpst685; CHECK-NEXT: vmlsdavt.s32 r0, q0, q1686; CHECK-NEXT: bx lr687entry:688 %0 = zext i16 %p to i32689 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)690 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 1, i32 0, i32 0, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)691 ret i32 %2692}693 694define arm_aapcs_vfpcc i32 @test_vmlsdavxq_p_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {695; CHECK-LABEL: test_vmlsdavxq_p_s8:696; CHECK: @ %bb.0: @ %entry697; CHECK-NEXT: vmsr p0, r0698; CHECK-NEXT: vpst699; CHECK-NEXT: vmlsdavxt.s8 r0, q0, q1700; CHECK-NEXT: bx lr701entry:702 %0 = zext i16 %p to i32703 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)704 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 0, i32 1, i32 1, i32 0, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)705 ret i32 %2706}707 708define arm_aapcs_vfpcc i32 @test_vmlsdavxq_p_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {709; CHECK-LABEL: test_vmlsdavxq_p_s16:710; CHECK: @ %bb.0: @ %entry711; CHECK-NEXT: vmsr p0, r0712; CHECK-NEXT: vpst713; CHECK-NEXT: vmlsdavxt.s16 r0, q0, q1714; CHECK-NEXT: bx lr715entry:716 %0 = zext i16 %p to i32717 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)718 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32 0, i32 1, i32 1, i32 0, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)719 ret i32 %2720}721 722define arm_aapcs_vfpcc i32 @test_vmlsdavxq_p_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {723; CHECK-LABEL: test_vmlsdavxq_p_s32:724; CHECK: @ %bb.0: @ %entry725; CHECK-NEXT: vmsr p0, r0726; CHECK-NEXT: vpst727; CHECK-NEXT: vmlsdavxt.s32 r0, q0, q1728; CHECK-NEXT: bx lr729entry:730 %0 = zext i16 %p to i32731 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)732 %2 = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 1, i32 1, i32 0, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)733 ret i32 %2734}735