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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck --check-prefix=LE %s3; RUN: llc -mtriple=thumbebv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck --check-prefix=BE %s4 5define arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> %a) {6; LE-LABEL: test_vmovlbq_s8:7; LE: @ %bb.0: @ %entry8; LE-NEXT: vmovlb.s8 q0, q09; LE-NEXT: bx lr10;11; BE-LABEL: test_vmovlbq_s8:12; BE: @ %bb.0: @ %entry13; BE-NEXT: vrev64.8 q1, q014; BE-NEXT: vmovlb.s8 q1, q115; BE-NEXT: vrev64.16 q0, q116; BE-NEXT: bx lr17entry:18 %0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>19 %1 = sext <8 x i8> %0 to <8 x i16>20 ret <8 x i16> %121}22 23define arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> %a) {24; LE-LABEL: test_vmovlbq_s16:25; LE: @ %bb.0: @ %entry26; LE-NEXT: vmovlb.s16 q0, q027; LE-NEXT: bx lr28;29; BE-LABEL: test_vmovlbq_s16:30; BE: @ %bb.0: @ %entry31; BE-NEXT: vrev64.16 q1, q032; BE-NEXT: vmovlb.s16 q1, q133; BE-NEXT: vrev64.32 q0, q134; BE-NEXT: bx lr35entry:36 %0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>37 %1 = sext <4 x i16> %0 to <4 x i32>38 ret <4 x i32> %139}40 41define arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> %a) {42; LE-LABEL: test_vmovlbq_u8:43; LE: @ %bb.0: @ %entry44; LE-NEXT: vmovlb.u8 q0, q045; LE-NEXT: bx lr46;47; BE-LABEL: test_vmovlbq_u8:48; BE: @ %bb.0: @ %entry49; BE-NEXT: vrev64.8 q1, q050; BE-NEXT: vmovlb.u8 q1, q151; BE-NEXT: vrev64.16 q0, q152; BE-NEXT: bx lr53entry:54 %0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>55 %1 = zext <8 x i8> %0 to <8 x i16>56 ret <8 x i16> %157}58 59define arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> %a) {60; LE-LABEL: test_vmovlbq_u16:61; LE: @ %bb.0: @ %entry62; LE-NEXT: vmovlb.u16 q0, q063; LE-NEXT: bx lr64;65; BE-LABEL: test_vmovlbq_u16:66; BE: @ %bb.0: @ %entry67; BE-NEXT: vrev64.16 q1, q068; BE-NEXT: vmovlb.u16 q1, q169; BE-NEXT: vrev64.32 q0, q170; BE-NEXT: bx lr71entry:72 %0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>73 %1 = zext <4 x i16> %0 to <4 x i32>74 ret <4 x i32> %175}76 77define arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> %a) {78; LE-LABEL: test_vmovltq_s8:79; LE: @ %bb.0: @ %entry80; LE-NEXT: vmovlt.s8 q0, q081; LE-NEXT: bx lr82;83; BE-LABEL: test_vmovltq_s8:84; BE: @ %bb.0: @ %entry85; BE-NEXT: vrev64.8 q1, q086; BE-NEXT: vmovlt.s8 q1, q187; BE-NEXT: vrev64.16 q0, q188; BE-NEXT: bx lr89entry:90 %0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>91 %1 = sext <8 x i8> %0 to <8 x i16>92 ret <8 x i16> %193}94 95define arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> %a) {96; LE-LABEL: test_vmovltq_s16:97; LE: @ %bb.0: @ %entry98; LE-NEXT: vmovlt.s16 q0, q099; LE-NEXT: bx lr100;101; BE-LABEL: test_vmovltq_s16:102; BE: @ %bb.0: @ %entry103; BE-NEXT: vrev64.16 q1, q0104; BE-NEXT: vmovlt.s16 q1, q1105; BE-NEXT: vrev64.32 q0, q1106; BE-NEXT: bx lr107entry:108 %0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>109 %1 = sext <4 x i16> %0 to <4 x i32>110 ret <4 x i32> %1111}112 113define arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> %a) {114; LE-LABEL: test_vmovltq_u8:115; LE: @ %bb.0: @ %entry116; LE-NEXT: vmovlt.u8 q0, q0117; LE-NEXT: bx lr118;119; BE-LABEL: test_vmovltq_u8:120; BE: @ %bb.0: @ %entry121; BE-NEXT: vrev64.8 q1, q0122; BE-NEXT: vmovlt.u8 q1, q1123; BE-NEXT: vrev64.16 q0, q1124; BE-NEXT: bx lr125entry:126 %0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>127 %1 = zext <8 x i8> %0 to <8 x i16>128 ret <8 x i16> %1129}130 131define arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> %a) {132; LE-LABEL: test_vmovltq_u16:133; LE: @ %bb.0: @ %entry134; LE-NEXT: vmovlt.u16 q0, q0135; LE-NEXT: bx lr136;137; BE-LABEL: test_vmovltq_u16:138; BE: @ %bb.0: @ %entry139; BE-NEXT: vrev64.16 q1, q0140; BE-NEXT: vmovlt.u16 q1, q1141; BE-NEXT: vrev64.32 q0, q1142; BE-NEXT: bx lr143entry:144 %0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>145 %1 = zext <4 x i16> %0 to <4 x i32>146 ret <4 x i32> %1147}148 149define arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_s8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {150; LE-LABEL: test_vmovlbq_m_s8:151; LE: @ %bb.0: @ %entry152; LE-NEXT: vmsr p0, r0153; LE-NEXT: vpst154; LE-NEXT: vmovlbt.s8 q0, q1155; LE-NEXT: bx lr156;157; BE-LABEL: test_vmovlbq_m_s8:158; BE: @ %bb.0: @ %entry159; BE-NEXT: vrev64.16 q2, q0160; BE-NEXT: vrev64.8 q0, q1161; BE-NEXT: vmsr p0, r0162; BE-NEXT: vpst163; BE-NEXT: vmovlbt.s8 q2, q0164; BE-NEXT: vrev64.16 q0, q2165; BE-NEXT: bx lr166entry:167 %0 = zext i16 %p to i32168 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)169 %2 = tail call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive)170 ret <8 x i16> %2171}172 173define arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_s16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {174; LE-LABEL: test_vmovlbq_m_s16:175; LE: @ %bb.0: @ %entry176; LE-NEXT: vmsr p0, r0177; LE-NEXT: vpst178; LE-NEXT: vmovlbt.s16 q0, q1179; LE-NEXT: bx lr180;181; BE-LABEL: test_vmovlbq_m_s16:182; BE: @ %bb.0: @ %entry183; BE-NEXT: vrev64.32 q2, q0184; BE-NEXT: vrev64.16 q0, q1185; BE-NEXT: vmsr p0, r0186; BE-NEXT: vpst187; BE-NEXT: vmovlbt.s16 q2, q0188; BE-NEXT: vrev64.32 q0, q2189; BE-NEXT: bx lr190entry:191 %0 = zext i16 %p to i32192 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)193 %2 = tail call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 0, i32 0, <4 x i1> %1, <4 x i32> %inactive)194 ret <4 x i32> %2195}196 197define arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_u8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {198; LE-LABEL: test_vmovlbq_m_u8:199; LE: @ %bb.0: @ %entry200; LE-NEXT: vmsr p0, r0201; LE-NEXT: vpst202; LE-NEXT: vmovlbt.u8 q0, q1203; LE-NEXT: bx lr204;205; BE-LABEL: test_vmovlbq_m_u8:206; BE: @ %bb.0: @ %entry207; BE-NEXT: vrev64.16 q2, q0208; BE-NEXT: vrev64.8 q0, q1209; BE-NEXT: vmsr p0, r0210; BE-NEXT: vpst211; BE-NEXT: vmovlbt.u8 q2, q0212; BE-NEXT: vrev64.16 q0, q2213; BE-NEXT: bx lr214entry:215 %0 = zext i16 %p to i32216 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)217 %2 = tail call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 1, i32 0, <8 x i1> %1, <8 x i16> %inactive)218 ret <8 x i16> %2219}220 221define arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_u16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {222; LE-LABEL: test_vmovlbq_m_u16:223; LE: @ %bb.0: @ %entry224; LE-NEXT: vmsr p0, r0225; LE-NEXT: vpst226; LE-NEXT: vmovlbt.u16 q0, q1227; LE-NEXT: bx lr228;229; BE-LABEL: test_vmovlbq_m_u16:230; BE: @ %bb.0: @ %entry231; BE-NEXT: vrev64.32 q2, q0232; BE-NEXT: vrev64.16 q0, q1233; BE-NEXT: vmsr p0, r0234; BE-NEXT: vpst235; BE-NEXT: vmovlbt.u16 q2, q0236; BE-NEXT: vrev64.32 q0, q2237; BE-NEXT: bx lr238entry:239 %0 = zext i16 %p to i32240 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)241 %2 = tail call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive)242 ret <4 x i32> %2243}244 245define arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_s8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {246; LE-LABEL: test_vmovltq_m_s8:247; LE: @ %bb.0: @ %entry248; LE-NEXT: vmsr p0, r0249; LE-NEXT: vpst250; LE-NEXT: vmovltt.s8 q0, q1251; LE-NEXT: bx lr252;253; BE-LABEL: test_vmovltq_m_s8:254; BE: @ %bb.0: @ %entry255; BE-NEXT: vrev64.16 q2, q0256; BE-NEXT: vrev64.8 q0, q1257; BE-NEXT: vmsr p0, r0258; BE-NEXT: vpst259; BE-NEXT: vmovltt.s8 q2, q0260; BE-NEXT: vrev64.16 q0, q2261; BE-NEXT: bx lr262entry:263 %0 = zext i16 %p to i32264 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)265 %2 = tail call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 0, i32 1, <8 x i1> %1, <8 x i16> %inactive)266 ret <8 x i16> %2267}268 269define arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_s16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {270; LE-LABEL: test_vmovltq_m_s16:271; LE: @ %bb.0: @ %entry272; LE-NEXT: vmsr p0, r0273; LE-NEXT: vpst274; LE-NEXT: vmovltt.s16 q0, q1275; LE-NEXT: bx lr276;277; BE-LABEL: test_vmovltq_m_s16:278; BE: @ %bb.0: @ %entry279; BE-NEXT: vrev64.32 q2, q0280; BE-NEXT: vrev64.16 q0, q1281; BE-NEXT: vmsr p0, r0282; BE-NEXT: vpst283; BE-NEXT: vmovltt.s16 q2, q0284; BE-NEXT: vrev64.32 q0, q2285; BE-NEXT: bx lr286entry:287 %0 = zext i16 %p to i32288 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)289 %2 = tail call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 0, i32 1, <4 x i1> %1, <4 x i32> %inactive)290 ret <4 x i32> %2291}292 293define arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_u8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {294; LE-LABEL: test_vmovltq_m_u8:295; LE: @ %bb.0: @ %entry296; LE-NEXT: vmsr p0, r0297; LE-NEXT: vpst298; LE-NEXT: vmovltt.u8 q0, q1299; LE-NEXT: bx lr300;301; BE-LABEL: test_vmovltq_m_u8:302; BE: @ %bb.0: @ %entry303; BE-NEXT: vrev64.16 q2, q0304; BE-NEXT: vrev64.8 q0, q1305; BE-NEXT: vmsr p0, r0306; BE-NEXT: vpst307; BE-NEXT: vmovltt.u8 q2, q0308; BE-NEXT: vrev64.16 q0, q2309; BE-NEXT: bx lr310entry:311 %0 = zext i16 %p to i32312 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)313 %2 = tail call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 1, i32 1, <8 x i1> %1, <8 x i16> %inactive)314 ret <8 x i16> %2315}316 317define arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_u16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {318; LE-LABEL: test_vmovltq_m_u16:319; LE: @ %bb.0: @ %entry320; LE-NEXT: vmsr p0, r0321; LE-NEXT: vpst322; LE-NEXT: vmovltt.u16 q0, q1323; LE-NEXT: bx lr324;325; BE-LABEL: test_vmovltq_m_u16:326; BE: @ %bb.0: @ %entry327; BE-NEXT: vrev64.32 q2, q0328; BE-NEXT: vrev64.16 q0, q1329; BE-NEXT: vmsr p0, r0330; BE-NEXT: vpst331; BE-NEXT: vmovltt.u16 q2, q0332; BE-NEXT: vrev64.32 q0, q2333; BE-NEXT: bx lr334entry:335 %0 = zext i16 %p to i32336 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)337 %2 = tail call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 1, i32 1, <4 x i1> %1, <4 x i32> %inactive)338 ret <4 x i32> %2339}340 341declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)342declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)343declare <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, <8 x i1>, <8 x i16>)344declare <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, <4 x i1>, <4 x i32>)345