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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck --check-prefix=LE %s3; RUN: llc -mtriple=thumbebv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck --check-prefix=BE %s4 5define arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_s16(<16 x i8> %a, <8 x i16> %b) {6; LE-LABEL: test_vmovnbq_s16:7; LE: @ %bb.0: @ %entry8; LE-NEXT: vmovnb.i16 q0, q19; LE-NEXT: bx lr10;11; BE-LABEL: test_vmovnbq_s16:12; BE: @ %bb.0: @ %entry13; BE-NEXT: vrev64.16 q2, q114; BE-NEXT: vrev64.8 q1, q015; BE-NEXT: vmovnb.i16 q1, q216; BE-NEXT: vrev64.8 q0, q117; BE-NEXT: bx lr18entry:19 %0 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>20 %1 = tail call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %0)21 %2 = shufflevector <8 x i16> %b, <8 x i16> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>22 %3 = trunc <16 x i16> %2 to <16 x i8>23 ret <16 x i8> %324}25 26define arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_s32(<8 x i16> %a, <4 x i32> %b) {27; LE-LABEL: test_vmovnbq_s32:28; LE: @ %bb.0: @ %entry29; LE-NEXT: vmovnb.i32 q0, q130; LE-NEXT: bx lr31;32; BE-LABEL: test_vmovnbq_s32:33; BE: @ %bb.0: @ %entry34; BE-NEXT: vrev64.32 q2, q135; BE-NEXT: vrev64.16 q1, q036; BE-NEXT: vmovnb.i32 q1, q237; BE-NEXT: vrev64.16 q0, q138; BE-NEXT: bx lr39entry:40 %0 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>41 %1 = tail call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> %0)42 %2 = shufflevector <4 x i32> %b, <4 x i32> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>43 %3 = trunc <8 x i32> %2 to <8 x i16>44 ret <8 x i16> %345}46 47define arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_u16(<16 x i8> %a, <8 x i16> %b) {48; LE-LABEL: test_vmovnbq_u16:49; LE: @ %bb.0: @ %entry50; LE-NEXT: vmovnb.i16 q0, q151; LE-NEXT: bx lr52;53; BE-LABEL: test_vmovnbq_u16:54; BE: @ %bb.0: @ %entry55; BE-NEXT: vrev64.16 q2, q156; BE-NEXT: vrev64.8 q1, q057; BE-NEXT: vmovnb.i16 q1, q258; BE-NEXT: vrev64.8 q0, q159; BE-NEXT: bx lr60entry:61 %0 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>62 %1 = tail call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %0)63 %2 = shufflevector <8 x i16> %b, <8 x i16> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>64 %3 = trunc <16 x i16> %2 to <16 x i8>65 ret <16 x i8> %366}67 68define arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_u32(<8 x i16> %a, <4 x i32> %b) {69; LE-LABEL: test_vmovnbq_u32:70; LE: @ %bb.0: @ %entry71; LE-NEXT: vmovnb.i32 q0, q172; LE-NEXT: bx lr73;74; BE-LABEL: test_vmovnbq_u32:75; BE: @ %bb.0: @ %entry76; BE-NEXT: vrev64.32 q2, q177; BE-NEXT: vrev64.16 q1, q078; BE-NEXT: vmovnb.i32 q1, q279; BE-NEXT: vrev64.16 q0, q180; BE-NEXT: bx lr81entry:82 %0 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>83 %1 = tail call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> %0)84 %2 = shufflevector <4 x i32> %b, <4 x i32> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>85 %3 = trunc <8 x i32> %2 to <8 x i16>86 ret <8 x i16> %387}88 89define arm_aapcs_vfpcc <16 x i8> @test_vmovntq_s16(<16 x i8> %a, <8 x i16> %b) {90; LE-LABEL: test_vmovntq_s16:91; LE: @ %bb.0: @ %entry92; LE-NEXT: vmovnt.i16 q0, q193; LE-NEXT: bx lr94;95; BE-LABEL: test_vmovntq_s16:96; BE: @ %bb.0: @ %entry97; BE-NEXT: vrev64.16 q2, q198; BE-NEXT: vrev64.8 q1, q099; BE-NEXT: vmovnt.i16 q1, q2100; BE-NEXT: vrev64.8 q0, q1101; BE-NEXT: bx lr102entry:103 %0 = tail call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %a)104 %1 = shufflevector <8 x i16> %0, <8 x i16> %b, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>105 %2 = trunc <16 x i16> %1 to <16 x i8>106 ret <16 x i8> %2107}108 109define arm_aapcs_vfpcc <8 x i16> @test_vmovntq_s32(<8 x i16> %a, <4 x i32> %b) {110; LE-LABEL: test_vmovntq_s32:111; LE: @ %bb.0: @ %entry112; LE-NEXT: vmovnt.i32 q0, q1113; LE-NEXT: bx lr114;115; BE-LABEL: test_vmovntq_s32:116; BE: @ %bb.0: @ %entry117; BE-NEXT: vrev64.32 q2, q1118; BE-NEXT: vrev64.16 q1, q0119; BE-NEXT: vmovnt.i32 q1, q2120; BE-NEXT: vrev64.16 q0, q1121; BE-NEXT: bx lr122entry:123 %0 = tail call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> %a)124 %1 = shufflevector <4 x i32> %0, <4 x i32> %b, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>125 %2 = trunc <8 x i32> %1 to <8 x i16>126 ret <8 x i16> %2127}128 129define arm_aapcs_vfpcc <16 x i8> @test_vmovntq_u16(<16 x i8> %a, <8 x i16> %b) {130; LE-LABEL: test_vmovntq_u16:131; LE: @ %bb.0: @ %entry132; LE-NEXT: vmovnt.i16 q0, q1133; LE-NEXT: bx lr134;135; BE-LABEL: test_vmovntq_u16:136; BE: @ %bb.0: @ %entry137; BE-NEXT: vrev64.16 q2, q1138; BE-NEXT: vrev64.8 q1, q0139; BE-NEXT: vmovnt.i16 q1, q2140; BE-NEXT: vrev64.8 q0, q1141; BE-NEXT: bx lr142entry:143 %0 = tail call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> %a)144 %1 = shufflevector <8 x i16> %0, <8 x i16> %b, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>145 %2 = trunc <16 x i16> %1 to <16 x i8>146 ret <16 x i8> %2147}148 149define arm_aapcs_vfpcc <8 x i16> @test_vmovntq_u32(<8 x i16> %a, <4 x i32> %b) {150; LE-LABEL: test_vmovntq_u32:151; LE: @ %bb.0: @ %entry152; LE-NEXT: vmovnt.i32 q0, q1153; LE-NEXT: bx lr154;155; BE-LABEL: test_vmovntq_u32:156; BE: @ %bb.0: @ %entry157; BE-NEXT: vrev64.32 q2, q1158; BE-NEXT: vrev64.16 q1, q0159; BE-NEXT: vmovnt.i32 q1, q2160; BE-NEXT: vrev64.16 q0, q1161; BE-NEXT: bx lr162entry:163 %0 = tail call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16> %a)164 %1 = shufflevector <4 x i32> %0, <4 x i32> %b, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>165 %2 = trunc <8 x i32> %1 to <8 x i16>166 ret <8 x i16> %2167}168 169define arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {170; LE-LABEL: test_vmovnbq_m_s16:171; LE: @ %bb.0: @ %entry172; LE-NEXT: vmsr p0, r0173; LE-NEXT: vpst174; LE-NEXT: vmovnbt.i16 q0, q1175; LE-NEXT: bx lr176;177; BE-LABEL: test_vmovnbq_m_s16:178; BE: @ %bb.0: @ %entry179; BE-NEXT: vrev64.16 q2, q1180; BE-NEXT: vrev64.8 q1, q0181; BE-NEXT: vmsr p0, r0182; BE-NEXT: vpst183; BE-NEXT: vmovnbt.i16 q1, q2184; BE-NEXT: vrev64.8 q0, q1185; BE-NEXT: bx lr186entry:187 %0 = zext i16 %p to i32188 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)189 %2 = tail call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 0, <8 x i1> %1)190 ret <16 x i8> %2191}192 193define arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {194; LE-LABEL: test_vmovnbq_m_s32:195; LE: @ %bb.0: @ %entry196; LE-NEXT: vmsr p0, r0197; LE-NEXT: vpst198; LE-NEXT: vmovnbt.i32 q0, q1199; LE-NEXT: bx lr200;201; BE-LABEL: test_vmovnbq_m_s32:202; BE: @ %bb.0: @ %entry203; BE-NEXT: vrev64.32 q2, q1204; BE-NEXT: vrev64.16 q1, q0205; BE-NEXT: vmsr p0, r0206; BE-NEXT: vpst207; BE-NEXT: vmovnbt.i32 q1, q2208; BE-NEXT: vrev64.16 q0, q1209; BE-NEXT: bx lr210entry:211 %0 = zext i16 %p to i32212 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)213 %2 = tail call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 0, <4 x i1> %1)214 ret <8 x i16> %2215}216 217define arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {218; LE-LABEL: test_vmovnbq_m_u16:219; LE: @ %bb.0: @ %entry220; LE-NEXT: vmsr p0, r0221; LE-NEXT: vpst222; LE-NEXT: vmovnbt.i16 q0, q1223; LE-NEXT: bx lr224;225; BE-LABEL: test_vmovnbq_m_u16:226; BE: @ %bb.0: @ %entry227; BE-NEXT: vrev64.16 q2, q1228; BE-NEXT: vrev64.8 q1, q0229; BE-NEXT: vmsr p0, r0230; BE-NEXT: vpst231; BE-NEXT: vmovnbt.i16 q1, q2232; BE-NEXT: vrev64.8 q0, q1233; BE-NEXT: bx lr234entry:235 %0 = zext i16 %p to i32236 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)237 %2 = tail call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 0, <8 x i1> %1)238 ret <16 x i8> %2239}240 241define arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {242; LE-LABEL: test_vmovnbq_m_u32:243; LE: @ %bb.0: @ %entry244; LE-NEXT: vmsr p0, r0245; LE-NEXT: vpst246; LE-NEXT: vmovnbt.i32 q0, q1247; LE-NEXT: bx lr248;249; BE-LABEL: test_vmovnbq_m_u32:250; BE: @ %bb.0: @ %entry251; BE-NEXT: vrev64.32 q2, q1252; BE-NEXT: vrev64.16 q1, q0253; BE-NEXT: vmsr p0, r0254; BE-NEXT: vpst255; BE-NEXT: vmovnbt.i32 q1, q2256; BE-NEXT: vrev64.16 q0, q1257; BE-NEXT: bx lr258entry:259 %0 = zext i16 %p to i32260 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)261 %2 = tail call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 0, <4 x i1> %1)262 ret <8 x i16> %2263}264 265define arm_aapcs_vfpcc <16 x i8> @test_vmovntq_m_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {266; LE-LABEL: test_vmovntq_m_s16:267; LE: @ %bb.0: @ %entry268; LE-NEXT: vmsr p0, r0269; LE-NEXT: vpst270; LE-NEXT: vmovntt.i16 q0, q1271; LE-NEXT: bx lr272;273; BE-LABEL: test_vmovntq_m_s16:274; BE: @ %bb.0: @ %entry275; BE-NEXT: vrev64.16 q2, q1276; BE-NEXT: vrev64.8 q1, q0277; BE-NEXT: vmsr p0, r0278; BE-NEXT: vpst279; BE-NEXT: vmovntt.i16 q1, q2280; BE-NEXT: vrev64.8 q0, q1281; BE-NEXT: bx lr282entry:283 %0 = zext i16 %p to i32284 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)285 %2 = tail call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, <8 x i1> %1)286 ret <16 x i8> %2287}288 289define arm_aapcs_vfpcc <8 x i16> @test_vmovntq_m_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {290; LE-LABEL: test_vmovntq_m_s32:291; LE: @ %bb.0: @ %entry292; LE-NEXT: vmsr p0, r0293; LE-NEXT: vpst294; LE-NEXT: vmovntt.i32 q0, q1295; LE-NEXT: bx lr296;297; BE-LABEL: test_vmovntq_m_s32:298; BE: @ %bb.0: @ %entry299; BE-NEXT: vrev64.32 q2, q1300; BE-NEXT: vrev64.16 q1, q0301; BE-NEXT: vmsr p0, r0302; BE-NEXT: vpst303; BE-NEXT: vmovntt.i32 q1, q2304; BE-NEXT: vrev64.16 q0, q1305; BE-NEXT: bx lr306entry:307 %0 = zext i16 %p to i32308 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)309 %2 = tail call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, <4 x i1> %1)310 ret <8 x i16> %2311}312 313define arm_aapcs_vfpcc <16 x i8> @test_vmovntq_m_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {314; LE-LABEL: test_vmovntq_m_u16:315; LE: @ %bb.0: @ %entry316; LE-NEXT: vmsr p0, r0317; LE-NEXT: vpst318; LE-NEXT: vmovntt.i16 q0, q1319; LE-NEXT: bx lr320;321; BE-LABEL: test_vmovntq_m_u16:322; BE: @ %bb.0: @ %entry323; BE-NEXT: vrev64.16 q2, q1324; BE-NEXT: vrev64.8 q1, q0325; BE-NEXT: vmsr p0, r0326; BE-NEXT: vpst327; BE-NEXT: vmovntt.i16 q1, q2328; BE-NEXT: vrev64.8 q0, q1329; BE-NEXT: bx lr330entry:331 %0 = zext i16 %p to i32332 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)333 %2 = tail call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, <8 x i1> %1)334 ret <16 x i8> %2335}336 337define arm_aapcs_vfpcc <8 x i16> @test_vmovntq_m_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {338; LE-LABEL: test_vmovntq_m_u32:339; LE: @ %bb.0: @ %entry340; LE-NEXT: vmsr p0, r0341; LE-NEXT: vpst342; LE-NEXT: vmovntt.i32 q0, q1343; LE-NEXT: bx lr344;345; BE-LABEL: test_vmovntq_m_u32:346; BE: @ %bb.0: @ %entry347; BE-NEXT: vrev64.32 q2, q1348; BE-NEXT: vrev64.16 q1, q0349; BE-NEXT: vmsr p0, r0350; BE-NEXT: vpst351; BE-NEXT: vmovntt.i32 q1, q2352; BE-NEXT: vrev64.16 q0, q1353; BE-NEXT: bx lr354entry:355 %0 = zext i16 %p to i32356 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)357 %2 = tail call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, <4 x i1> %1)358 ret <8 x i16> %2359}360 361declare <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8>)362declare <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v8i16(<8 x i16>)363declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)364declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)365declare <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, <8 x i1>)366declare <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, <4 x i1>)367