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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vmulhq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {5; CHECK-LABEL: test_vmulhq_u8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmulh.u8 q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = tail call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1)11 ret <16 x i8> %012}13 14declare <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8>, <16 x i8>, i32) #115 16define arm_aapcs_vfpcc <8 x i16> @test_vmulhq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {17; CHECK-LABEL: test_vmulhq_s16:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vmulh.s16 q0, q0, q120; CHECK-NEXT: bx lr21entry:22 %0 = tail call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0)23 ret <8 x i16> %024}25 26declare <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16>, <8 x i16>, i32) #127 28define arm_aapcs_vfpcc <4 x i32> @test_vmulhq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {29; CHECK-LABEL: test_vmulhq_u32:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vmulh.u32 q0, q0, q132; CHECK-NEXT: bx lr33entry:34 %0 = tail call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1)35 ret <4 x i32> %036}37 38declare <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32>, <4 x i32>, i32) #139 40define arm_aapcs_vfpcc <16 x i8> @test_vmulhq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {41; CHECK-LABEL: test_vmulhq_m_s8:42; CHECK: @ %bb.0: @ %entry43; CHECK-NEXT: vmsr p0, r044; CHECK-NEXT: vpst45; CHECK-NEXT: vmulht.s8 q0, q1, q246; CHECK-NEXT: bx lr47entry:48 %0 = zext i16 %p to i3249 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)50 %2 = tail call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <16 x i8> %inactive)51 ret <16 x i8> %252}53 54declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #155 56declare <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #157 58define arm_aapcs_vfpcc <8 x i16> @test_vmulhq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {59; CHECK-LABEL: test_vmulhq_m_u16:60; CHECK: @ %bb.0: @ %entry61; CHECK-NEXT: vmsr p0, r062; CHECK-NEXT: vpst63; CHECK-NEXT: vmulht.u16 q0, q1, q264; CHECK-NEXT: bx lr65entry:66 %0 = zext i16 %p to i3267 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)68 %2 = tail call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, <8 x i1> %1, <8 x i16> %inactive)69 ret <8 x i16> %270}71 72declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #173 74declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #175 76define arm_aapcs_vfpcc <4 x i32> @test_vmulhq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {77; CHECK-LABEL: test_vmulhq_m_s32:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vmsr p0, r080; CHECK-NEXT: vpst81; CHECK-NEXT: vmulht.s32 q0, q1, q282; CHECK-NEXT: bx lr83entry:84 %0 = zext i16 %p to i3285 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)86 %2 = tail call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1, <4 x i32> %inactive)87 ret <4 x i32> %288}89 90declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #191 92declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #193 94define arm_aapcs_vfpcc <16 x i8> @test_vmulhq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {95; CHECK-LABEL: test_vmulhq_x_u8:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: vmsr p0, r098; CHECK-NEXT: vpst99; CHECK-NEXT: vmulht.u8 q0, q0, q1100; CHECK-NEXT: bx lr101entry:102 %0 = zext i16 %p to i32103 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)104 %2 = tail call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <16 x i8> undef)105 ret <16 x i8> %2106}107 108define arm_aapcs_vfpcc <8 x i16> @test_vmulhq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {109; CHECK-LABEL: test_vmulhq_x_s16:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vmsr p0, r0112; CHECK-NEXT: vpst113; CHECK-NEXT: vmulht.s16 q0, q0, q1114; CHECK-NEXT: bx lr115entry:116 %0 = zext i16 %p to i32117 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)118 %2 = tail call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, <8 x i1> %1, <8 x i16> undef)119 ret <8 x i16> %2120}121 122define arm_aapcs_vfpcc <4 x i32> @test_vmulhq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {123; CHECK-LABEL: test_vmulhq_x_u32:124; CHECK: @ %bb.0: @ %entry125; CHECK-NEXT: vmsr p0, r0126; CHECK-NEXT: vpst127; CHECK-NEXT: vmulht.u32 q0, q0, q1128; CHECK-NEXT: bx lr129entry:130 %0 = zext i16 %p to i32131 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)132 %2 = tail call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, <4 x i1> %1, <4 x i32> undef)133 ret <4 x i32> %2134}135 136