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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {5; CHECK-LABEL: test_vmullbq_int_u8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmullb.u8 q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = tail call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0)11 ret <8 x i16> %012}13 14declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #115 16define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {17; CHECK-LABEL: test_vmullbq_int_s16:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vmullb.s16 q0, q0, q120; CHECK-NEXT: bx lr21entry:22 %0 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0)23 ret <4 x i32> %024}25 26declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #127 28define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {29; CHECK-LABEL: test_vmullbq_int_u32:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vmullb.u32 q2, q0, q132; CHECK-NEXT: vmov q0, q233; CHECK-NEXT: bx lr34entry:35 %0 = tail call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0)36 ret <2 x i64> %037}38 39declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #140 41define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {42; CHECK-LABEL: test_vmullbq_poly_p16:43; CHECK: @ %bb.0: @ %entry44; CHECK-NEXT: vmullb.p16 q0, q0, q145; CHECK-NEXT: bx lr46entry:47 %0 = tail call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0)48 ret <4 x i32> %049}50 51declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #152 53define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {54; CHECK-LABEL: test_vmullbq_int_m_s8:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: vmsr p0, r057; CHECK-NEXT: vpst58; CHECK-NEXT: vmullbt.s8 q0, q1, q259; CHECK-NEXT: bx lr60entry:61 %0 = zext i16 %p to i3262 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)63 %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive)64 ret <8 x i16> %265}66 67declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #168 69declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #170 71define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) #0 {72; CHECK-LABEL: test_vmullbq_int_m_u16:73; CHECK: @ %bb.0: @ %entry74; CHECK-NEXT: vmsr p0, r075; CHECK-NEXT: vpst76; CHECK-NEXT: vmullbt.u16 q0, q1, q277; CHECK-NEXT: bx lr78entry:79 %0 = zext i16 %p to i3280 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)81 %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive)82 ret <4 x i32> %283}84 85declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #186 87declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #188 89define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {90; CHECK-LABEL: test_vmullbq_int_m_s32:91; CHECK: @ %bb.0: @ %entry92; CHECK-NEXT: vmsr p0, r093; CHECK-NEXT: vpst94; CHECK-NEXT: vmullbt.s32 q0, q1, q295; CHECK-NEXT: bx lr96entry:97 %0 = zext i16 %p to i3298 %1 = tail call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)99 %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, <2 x i1> %1, <2 x i64> %inactive)100 ret <2 x i64> %2101}102 103declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32)104declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1105 106define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {107; CHECK-LABEL: test_vmullbq_poly_m_p8:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: vmsr p0, r0110; CHECK-NEXT: vpst111; CHECK-NEXT: vmullbt.p8 q0, q1, q2112; CHECK-NEXT: bx lr113entry:114 %0 = zext i16 %p to i32115 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)116 %2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 0, <8 x i1> %1, <8 x i16> %inactive)117 ret <8 x i16> %2118}119 120declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1121 122define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {123; CHECK-LABEL: test_vmullbq_int_x_u8:124; CHECK: @ %bb.0: @ %entry125; CHECK-NEXT: vmsr p0, r0126; CHECK-NEXT: vpst127; CHECK-NEXT: vmullbt.u8 q0, q0, q1128; CHECK-NEXT: bx lr129entry:130 %0 = zext i16 %p to i32131 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)132 %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, <8 x i1> %1, <8 x i16> undef)133 ret <8 x i16> %2134}135 136define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {137; CHECK-LABEL: test_vmullbq_int_x_s16:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: vmsr p0, r0140; CHECK-NEXT: vpst141; CHECK-NEXT: vmullbt.s16 q0, q0, q1142; CHECK-NEXT: bx lr143entry:144 %0 = zext i16 %p to i32145 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)146 %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, <4 x i1> %1, <4 x i32> undef)147 ret <4 x i32> %2148}149 150define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {151; CHECK-LABEL: test_vmullbq_int_x_u32:152; CHECK: @ %bb.0: @ %entry153; CHECK-NEXT: vmsr p0, r0154; CHECK-NEXT: vpst155; CHECK-NEXT: vmullbt.u32 q2, q0, q1156; CHECK-NEXT: vmov q0, q2157; CHECK-NEXT: bx lr158entry:159 %0 = zext i16 %p to i32160 %1 = tail call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)161 %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0, <2 x i1> %1, <2 x i64> undef)162 ret <2 x i64> %2163}164 165define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_x_p16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {166; CHECK-LABEL: test_vmullbq_poly_x_p16:167; CHECK: @ %bb.0: @ %entry168; CHECK-NEXT: vmsr p0, r0169; CHECK-NEXT: vpst170; CHECK-NEXT: vmullbt.p16 q0, q0, q1171; CHECK-NEXT: bx lr172entry:173 %0 = zext i16 %p to i32174 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)175 %2 = tail call <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 0, <4 x i1> %1, <4 x i32> undef)176 ret <4 x i32> %2177}178 179declare <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1180