353 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vmulq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {5; CHECK-LABEL: test_vmulq_u8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmul.i8 q0, q1, q08; CHECK-NEXT: bx lr9entry:10 %0 = mul <16 x i8> %b, %a11 ret <16 x i8> %012}13 14define arm_aapcs_vfpcc <8 x i16> @test_vmulq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {15; CHECK-LABEL: test_vmulq_s16:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vmul.i16 q0, q1, q018; CHECK-NEXT: bx lr19entry:20 %0 = mul <8 x i16> %b, %a21 ret <8 x i16> %022}23 24define arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {25; CHECK-LABEL: test_vmulq_u32:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vmul.i32 q0, q1, q028; CHECK-NEXT: bx lr29entry:30 %0 = mul <4 x i32> %b, %a31 ret <4 x i32> %032}33 34define arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {35; CHECK-LABEL: test_vmulq_f32:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vmul.f32 q0, q0, q138; CHECK-NEXT: bx lr39entry:40 %0 = fmul <4 x float> %a, %b41 ret <4 x float> %042}43 44define arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {45; CHECK-LABEL: test_vmulq_m_s8:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vmsr p0, r048; CHECK-NEXT: vpst49; CHECK-NEXT: vmult.i8 q0, q1, q250; CHECK-NEXT: bx lr51entry:52 %0 = zext i16 %p to i3253 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)54 %2 = tail call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)55 ret <16 x i8> %256}57 58declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #259 60declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #261 62define arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {63; CHECK-LABEL: test_vmulq_m_u16:64; CHECK: @ %bb.0: @ %entry65; CHECK-NEXT: vmsr p0, r066; CHECK-NEXT: vpst67; CHECK-NEXT: vmult.i16 q0, q1, q268; CHECK-NEXT: bx lr69entry:70 %0 = zext i16 %p to i3271 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)72 %2 = tail call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)73 ret <8 x i16> %274}75 76declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #277 78declare <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #279 80define arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {81; CHECK-LABEL: test_vmulq_m_s32:82; CHECK: @ %bb.0: @ %entry83; CHECK-NEXT: vmsr p0, r084; CHECK-NEXT: vpst85; CHECK-NEXT: vmult.i32 q0, q1, q286; CHECK-NEXT: bx lr87entry:88 %0 = zext i16 %p to i3289 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)90 %2 = tail call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)91 ret <4 x i32> %292}93 94declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #295 96declare <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #297 98define arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {99; CHECK-LABEL: test_vmulq_m_f16:100; CHECK: @ %bb.0: @ %entry101; CHECK-NEXT: vmsr p0, r0102; CHECK-NEXT: vpst103; CHECK-NEXT: vmult.f16 q0, q1, q2104; CHECK-NEXT: bx lr105entry:106 %0 = zext i16 %p to i32107 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)108 %2 = tail call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> %inactive)109 ret <8 x half> %2110}111 112declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #2113 114define arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {115; CHECK-LABEL: test_vmulq_x_u8:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: vmsr p0, r0118; CHECK-NEXT: vpst119; CHECK-NEXT: vmult.i8 q0, q0, q1120; CHECK-NEXT: bx lr121entry:122 %0 = zext i16 %p to i32123 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)124 %2 = tail call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)125 ret <16 x i8> %2126}127 128define arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {129; CHECK-LABEL: test_vmulq_x_s16:130; CHECK: @ %bb.0: @ %entry131; CHECK-NEXT: vmsr p0, r0132; CHECK-NEXT: vpst133; CHECK-NEXT: vmult.i16 q0, q0, q1134; CHECK-NEXT: bx lr135entry:136 %0 = zext i16 %p to i32137 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)138 %2 = tail call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)139 ret <8 x i16> %2140}141 142define arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {143; CHECK-LABEL: test_vmulq_x_u32:144; CHECK: @ %bb.0: @ %entry145; CHECK-NEXT: vmsr p0, r0146; CHECK-NEXT: vpst147; CHECK-NEXT: vmult.i32 q0, q0, q1148; CHECK-NEXT: bx lr149entry:150 %0 = zext i16 %p to i32151 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)152 %2 = tail call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)153 ret <4 x i32> %2154}155 156define arm_aapcs_vfpcc <4 x float> @test_vmulq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {157; CHECK-LABEL: test_vmulq_m_f32:158; CHECK: @ %bb.0: @ %entry159; CHECK-NEXT: vmsr p0, r0160; CHECK-NEXT: vpst161; CHECK-NEXT: vmult.f32 q0, q0, q1162; CHECK-NEXT: bx lr163entry:164 %0 = zext i16 %p to i32165 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)166 %2 = tail call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> undef)167 ret <4 x float> %2168}169 170declare <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #2171 172define arm_aapcs_vfpcc <16 x i8> @test_vmulq_n_u8(<16 x i8> %a, i8 zeroext %b) {173; CHECK-LABEL: test_vmulq_n_u8:174; CHECK: @ %bb.0: @ %entry175; CHECK-NEXT: vmul.i8 q0, q0, r0176; CHECK-NEXT: bx lr177entry:178 %.splatinsert = insertelement <16 x i8> undef, i8 %b, i32 0179 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer180 %0 = mul <16 x i8> %.splat, %a181 ret <16 x i8> %0182}183 184define arm_aapcs_vfpcc <8 x i16> @test_vmulq_n_s16(<8 x i16> %a, i16 signext %b) {185; CHECK-LABEL: test_vmulq_n_s16:186; CHECK: @ %bb.0: @ %entry187; CHECK-NEXT: vmul.i16 q0, q0, r0188; CHECK-NEXT: bx lr189entry:190 %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0191 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer192 %0 = mul <8 x i16> %.splat, %a193 ret <8 x i16> %0194}195 196define arm_aapcs_vfpcc <4 x i32> @test_vmulq_n_u32(<4 x i32> %a, i32 %b) {197; CHECK-LABEL: test_vmulq_n_u32:198; CHECK: @ %bb.0: @ %entry199; CHECK-NEXT: vmul.i32 q0, q0, r0200; CHECK-NEXT: bx lr201entry:202 %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0203 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer204 %0 = mul <4 x i32> %.splat, %a205 ret <4 x i32> %0206}207 208define arm_aapcs_vfpcc <4 x float> @test_vmulq_n_f32(<4 x float> %a, float %b) {209; CHECK-LABEL: test_vmulq_n_f32:210; CHECK: @ %bb.0: @ %entry211; CHECK-NEXT: vmov r0, s4212; CHECK-NEXT: vmul.f32 q0, q0, r0213; CHECK-NEXT: bx lr214entry:215 %.splatinsert = insertelement <4 x float> undef, float %b, i32 0216 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer217 %0 = fmul <4 x float> %.splat, %a218 ret <4 x float> %0219}220 221define arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i8 signext %b, i16 zeroext %p) {222; CHECK-LABEL: test_vmulq_m_n_s8:223; CHECK: @ %bb.0: @ %entry224; CHECK-NEXT: vmsr p0, r1225; CHECK-NEXT: vpst226; CHECK-NEXT: vmult.i8 q0, q1, r0227; CHECK-NEXT: bx lr228entry:229 %.splatinsert = insertelement <16 x i8> undef, i8 %b, i32 0230 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer231 %0 = zext i16 %p to i32232 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)233 %2 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %.splat, <16 x i1> %1, <16 x i8> %inactive)234 ret <16 x i8> %2235}236 237define arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_n_u16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %b, i16 zeroext %p) {238; CHECK-LABEL: test_vmulq_m_n_u16:239; CHECK: @ %bb.0: @ %entry240; CHECK-NEXT: vmsr p0, r1241; CHECK-NEXT: vpst242; CHECK-NEXT: vmult.i16 q0, q1, r0243; CHECK-NEXT: bx lr244entry:245 %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0246 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer247 %0 = zext i16 %p to i32248 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)249 %2 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %.splat, <8 x i1> %1, <8 x i16> %inactive)250 ret <8 x i16> %2251}252 253define arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_n_s32(<4 x i32> %inactive, <4 x i32> %a, i32 %b, i16 zeroext %p) {254; CHECK-LABEL: test_vmulq_m_n_s32:255; CHECK: @ %bb.0: @ %entry256; CHECK-NEXT: vmsr p0, r1257; CHECK-NEXT: vpst258; CHECK-NEXT: vmult.i32 q0, q1, r0259; CHECK-NEXT: bx lr260entry:261 %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0262 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer263 %0 = zext i16 %p to i32264 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)265 %2 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %.splat, <4 x i1> %1, <4 x i32> %inactive)266 ret <4 x i32> %2267}268 269define arm_aapcs_vfpcc <8 x half> @test_vmulq_m_n_f16(<8 x half> %inactive, <8 x half> %a, float %b.coerce, i16 zeroext %p) {270; CHECK-LABEL: test_vmulq_m_n_f16:271; CHECK: @ %bb.0: @ %entry272; CHECK-NEXT: vmov r1, s8273; CHECK-NEXT: vmsr p0, r0274; CHECK-NEXT: vpst275; CHECK-NEXT: vmult.f16 q0, q1, r1276; CHECK-NEXT: bx lr277entry:278 %0 = bitcast float %b.coerce to i32279 %tmp.0.extract.trunc = trunc i32 %0 to i16280 %1 = bitcast i16 %tmp.0.extract.trunc to half281 %.splatinsert = insertelement <8 x half> undef, half %1, i32 0282 %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> undef, <8 x i32> zeroinitializer283 %2 = zext i16 %p to i32284 %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)285 %4 = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %.splat, <8 x i1> %3, <8 x half> %inactive)286 ret <8 x half> %4287}288 289define arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_n_u8(<16 x i8> %a, i8 zeroext %b, i16 zeroext %p) {290; CHECK-LABEL: test_vmulq_x_n_u8:291; CHECK: @ %bb.0: @ %entry292; CHECK-NEXT: vmsr p0, r1293; CHECK-NEXT: vpst294; CHECK-NEXT: vmult.i8 q0, q0, r0295; CHECK-NEXT: bx lr296entry:297 %.splatinsert = insertelement <16 x i8> undef, i8 %b, i32 0298 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer299 %0 = zext i16 %p to i32300 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)301 %2 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %.splat, <16 x i1> %1, <16 x i8> undef)302 ret <16 x i8> %2303}304 305define arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_n_s16(<8 x i16> %a, i16 signext %b, i16 zeroext %p) {306; CHECK-LABEL: test_vmulq_x_n_s16:307; CHECK: @ %bb.0: @ %entry308; CHECK-NEXT: vmsr p0, r1309; CHECK-NEXT: vpst310; CHECK-NEXT: vmult.i16 q0, q0, r0311; CHECK-NEXT: bx lr312entry:313 %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0314 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer315 %0 = zext i16 %p to i32316 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)317 %2 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %.splat, <8 x i1> %1, <8 x i16> undef)318 ret <8 x i16> %2319}320 321define arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_n_u32(<4 x i32> %a, i32 %b, i16 zeroext %p) {322; CHECK-LABEL: test_vmulq_x_n_u32:323; CHECK: @ %bb.0: @ %entry324; CHECK-NEXT: vmsr p0, r1325; CHECK-NEXT: vpst326; CHECK-NEXT: vmult.i32 q0, q0, r0327; CHECK-NEXT: bx lr328entry:329 %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0330 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer331 %0 = zext i16 %p to i32332 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)333 %2 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %.splat, <4 x i1> %1, <4 x i32> undef)334 ret <4 x i32> %2335}336 337define arm_aapcs_vfpcc <4 x float> @test_vmulq_x_n_f32(<4 x float> %a, float %b, i16 zeroext %p) {338; CHECK-LABEL: test_vmulq_x_n_f32:339; CHECK: @ %bb.0: @ %entry340; CHECK-NEXT: vmov r1, s4341; CHECK-NEXT: vmsr p0, r0342; CHECK-NEXT: vpst343; CHECK-NEXT: vmult.f32 q0, q0, r1344; CHECK-NEXT: bx lr345entry:346 %.splatinsert = insertelement <4 x float> undef, float %b, i32 0347 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer348 %0 = zext i16 %p to i32349 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)350 %2 = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %.splat, <4 x i1> %1, <4 x float> undef)351 ret <4 x float> %2352}353