590 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {5; CHECK-LABEL: test_vqdmladhq_s8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vqdmladh.s8 q0, q1, q28; CHECK-NEXT: bx lr9entry:10 %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 0)11 ret <16 x i8> %012}13 14define arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {15; CHECK-LABEL: test_vqdmladhq_s16:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vqdmladh.s16 q0, q1, q218; CHECK-NEXT: bx lr19entry:20 %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 0)21 ret <8 x i16> %022}23 24define arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {25; CHECK-LABEL: test_vqdmladhq_s32:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vqdmladh.s32 q0, q1, q228; CHECK-NEXT: bx lr29entry:30 %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 0)31 ret <4 x i32> %032}33 34define arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {35; CHECK-LABEL: test_vqdmladhxq_s8:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vqdmladhx.s8 q0, q1, q238; CHECK-NEXT: bx lr39entry:40 %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 0)41 ret <16 x i8> %042}43 44define arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {45; CHECK-LABEL: test_vqdmladhxq_s16:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vqdmladhx.s16 q0, q1, q248; CHECK-NEXT: bx lr49entry:50 %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 0)51 ret <8 x i16> %052}53 54define arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {55; CHECK-LABEL: test_vqdmladhxq_s32:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vqdmladhx.s32 q0, q1, q258; CHECK-NEXT: bx lr59entry:60 %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 0)61 ret <4 x i32> %062}63 64define arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {65; CHECK-LABEL: test_vqdmlsdhq_s8:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vqdmlsdh.s8 q0, q1, q268; CHECK-NEXT: bx lr69entry:70 %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 1)71 ret <16 x i8> %072}73 74define arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {75; CHECK-LABEL: test_vqdmlsdhq_s16:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vqdmlsdh.s16 q0, q1, q278; CHECK-NEXT: bx lr79entry:80 %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 1)81 ret <8 x i16> %082}83 84define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {85; CHECK-LABEL: test_vqdmlsdhq_s32:86; CHECK: @ %bb.0: @ %entry87; CHECK-NEXT: vqdmlsdh.s32 q0, q1, q288; CHECK-NEXT: bx lr89entry:90 %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 1)91 ret <4 x i32> %092}93 94define arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {95; CHECK-LABEL: test_vqdmlsdhxq_s8:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: vqdmlsdhx.s8 q0, q1, q298; CHECK-NEXT: bx lr99entry:100 %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 1)101 ret <16 x i8> %0102}103 104define arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {105; CHECK-LABEL: test_vqdmlsdhxq_s16:106; CHECK: @ %bb.0: @ %entry107; CHECK-NEXT: vqdmlsdhx.s16 q0, q1, q2108; CHECK-NEXT: bx lr109entry:110 %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 1)111 ret <8 x i16> %0112}113 114define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {115; CHECK-LABEL: test_vqdmlsdhxq_s32:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: vqdmlsdhx.s32 q0, q1, q2118; CHECK-NEXT: bx lr119entry:120 %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 1)121 ret <4 x i32> %0122}123 124define arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {125; CHECK-LABEL: test_vqrdmladhq_s8:126; CHECK: @ %bb.0: @ %entry127; CHECK-NEXT: vqrdmladh.s8 q0, q1, q2128; CHECK-NEXT: bx lr129entry:130 %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0)131 ret <16 x i8> %0132}133 134define arm_aapcs_vfpcc <8 x i16> @test_vqrdmladhq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {135; CHECK-LABEL: test_vqrdmladhq_s16:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: vqrdmladh.s16 q0, q1, q2138; CHECK-NEXT: bx lr139entry:140 %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 0)141 ret <8 x i16> %0142}143 144define arm_aapcs_vfpcc <4 x i32> @test_vqrdmladhq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {145; CHECK-LABEL: test_vqrdmladhq_s32:146; CHECK: @ %bb.0: @ %entry147; CHECK-NEXT: vqrdmladh.s32 q0, q1, q2148; CHECK-NEXT: bx lr149entry:150 %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 0)151 ret <4 x i32> %0152}153 154define arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhxq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {155; CHECK-LABEL: test_vqrdmladhxq_s8:156; CHECK: @ %bb.0: @ %entry157; CHECK-NEXT: vqrdmladhx.s8 q0, q1, q2158; CHECK-NEXT: bx lr159entry:160 %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 0)161 ret <16 x i8> %0162}163 164define arm_aapcs_vfpcc <8 x i16> @test_vqrdmladhxq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {165; CHECK-LABEL: test_vqrdmladhxq_s16:166; CHECK: @ %bb.0: @ %entry167; CHECK-NEXT: vqrdmladhx.s16 q0, q1, q2168; CHECK-NEXT: bx lr169entry:170 %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 0)171 ret <8 x i16> %0172}173 174define arm_aapcs_vfpcc <4 x i32> @test_vqrdmladhxq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {175; CHECK-LABEL: test_vqrdmladhxq_s32:176; CHECK: @ %bb.0: @ %entry177; CHECK-NEXT: vqrdmladhx.s32 q0, q1, q2178; CHECK-NEXT: bx lr179entry:180 %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 0)181 ret <4 x i32> %0182}183 184define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlsdhq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {185; CHECK-LABEL: test_vqrdmlsdhq_s8:186; CHECK: @ %bb.0: @ %entry187; CHECK-NEXT: vqrdmlsdh.s8 q0, q1, q2188; CHECK-NEXT: bx lr189entry:190 %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 1)191 ret <16 x i8> %0192}193 194define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlsdhq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {195; CHECK-LABEL: test_vqrdmlsdhq_s16:196; CHECK: @ %bb.0: @ %entry197; CHECK-NEXT: vqrdmlsdh.s16 q0, q1, q2198; CHECK-NEXT: bx lr199entry:200 %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 1)201 ret <8 x i16> %0202}203 204define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlsdhq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {205; CHECK-LABEL: test_vqrdmlsdhq_s32:206; CHECK: @ %bb.0: @ %entry207; CHECK-NEXT: vqrdmlsdh.s32 q0, q1, q2208; CHECK-NEXT: bx lr209entry:210 %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 1)211 ret <4 x i32> %0212}213 214define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlsdhxq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {215; CHECK-LABEL: test_vqrdmlsdhxq_s8:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vqrdmlsdhx.s8 q0, q1, q2218; CHECK-NEXT: bx lr219entry:220 %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 1)221 ret <16 x i8> %0222}223 224define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlsdhxq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {225; CHECK-LABEL: test_vqrdmlsdhxq_s16:226; CHECK: @ %bb.0: @ %entry227; CHECK-NEXT: vqrdmlsdhx.s16 q0, q1, q2228; CHECK-NEXT: bx lr229entry:230 %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 1)231 ret <8 x i16> %0232}233 234define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlsdhxq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {235; CHECK-LABEL: test_vqrdmlsdhxq_s32:236; CHECK: @ %bb.0: @ %entry237; CHECK-NEXT: vqrdmlsdhx.s32 q0, q1, q2238; CHECK-NEXT: bx lr239entry:240 %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 1)241 ret <4 x i32> %0242}243 244define arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {245; CHECK-LABEL: test_vqdmladhq_m_s8:246; CHECK: @ %bb.0: @ %entry247; CHECK-NEXT: vmsr p0, r0248; CHECK-NEXT: vpst249; CHECK-NEXT: vqdmladht.s8 q0, q1, q2250; CHECK-NEXT: bx lr251entry:252 %0 = zext i16 %p to i32253 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)254 %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 0, <16 x i1> %1)255 ret <16 x i8> %2256}257 258define arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {259; CHECK-LABEL: test_vqdmladhq_m_s16:260; CHECK: @ %bb.0: @ %entry261; CHECK-NEXT: vmsr p0, r0262; CHECK-NEXT: vpst263; CHECK-NEXT: vqdmladht.s16 q0, q1, q2264; CHECK-NEXT: bx lr265entry:266 %0 = zext i16 %p to i32267 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)268 %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 0, <8 x i1> %1)269 ret <8 x i16> %2270}271 272define arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {273; CHECK-LABEL: test_vqdmladhq_m_s32:274; CHECK: @ %bb.0: @ %entry275; CHECK-NEXT: vmsr p0, r0276; CHECK-NEXT: vpst277; CHECK-NEXT: vqdmladht.s32 q0, q1, q2278; CHECK-NEXT: bx lr279entry:280 %0 = zext i16 %p to i32281 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)282 %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 0, <4 x i1> %1)283 ret <4 x i32> %2284}285 286define arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {287; CHECK-LABEL: test_vqdmladhxq_m_s8:288; CHECK: @ %bb.0: @ %entry289; CHECK-NEXT: vmsr p0, r0290; CHECK-NEXT: vpst291; CHECK-NEXT: vqdmladhxt.s8 q0, q1, q2292; CHECK-NEXT: bx lr293entry:294 %0 = zext i16 %p to i32295 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)296 %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 0, <16 x i1> %1)297 ret <16 x i8> %2298}299 300define arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {301; CHECK-LABEL: test_vqdmladhxq_m_s16:302; CHECK: @ %bb.0: @ %entry303; CHECK-NEXT: vmsr p0, r0304; CHECK-NEXT: vpst305; CHECK-NEXT: vqdmladhxt.s16 q0, q1, q2306; CHECK-NEXT: bx lr307entry:308 %0 = zext i16 %p to i32309 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)310 %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 0, <8 x i1> %1)311 ret <8 x i16> %2312}313 314define arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {315; CHECK-LABEL: test_vqdmladhxq_m_s32:316; CHECK: @ %bb.0: @ %entry317; CHECK-NEXT: vmsr p0, r0318; CHECK-NEXT: vpst319; CHECK-NEXT: vqdmladhxt.s32 q0, q1, q2320; CHECK-NEXT: bx lr321entry:322 %0 = zext i16 %p to i32323 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)324 %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 0, <4 x i1> %1)325 ret <4 x i32> %2326}327 328define arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {329; CHECK-LABEL: test_vqdmlsdhq_m_s8:330; CHECK: @ %bb.0: @ %entry331; CHECK-NEXT: vmsr p0, r0332; CHECK-NEXT: vpst333; CHECK-NEXT: vqdmlsdht.s8 q0, q1, q2334; CHECK-NEXT: bx lr335entry:336 %0 = zext i16 %p to i32337 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)338 %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 1, <16 x i1> %1)339 ret <16 x i8> %2340}341 342define arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {343; CHECK-LABEL: test_vqdmlsdhq_m_s16:344; CHECK: @ %bb.0: @ %entry345; CHECK-NEXT: vmsr p0, r0346; CHECK-NEXT: vpst347; CHECK-NEXT: vqdmlsdht.s16 q0, q1, q2348; CHECK-NEXT: bx lr349entry:350 %0 = zext i16 %p to i32351 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)352 %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 1, <8 x i1> %1)353 ret <8 x i16> %2354}355 356define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {357; CHECK-LABEL: test_vqdmlsdhq_m_s32:358; CHECK: @ %bb.0: @ %entry359; CHECK-NEXT: vmsr p0, r0360; CHECK-NEXT: vpst361; CHECK-NEXT: vqdmlsdht.s32 q0, q1, q2362; CHECK-NEXT: bx lr363entry:364 %0 = zext i16 %p to i32365 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)366 %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 1, <4 x i1> %1)367 ret <4 x i32> %2368}369 370define arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {371; CHECK-LABEL: test_vqdmlsdhxq_m_s8:372; CHECK: @ %bb.0: @ %entry373; CHECK-NEXT: vmsr p0, r0374; CHECK-NEXT: vpst375; CHECK-NEXT: vqdmlsdhxt.s8 q0, q1, q2376; CHECK-NEXT: bx lr377entry:378 %0 = zext i16 %p to i32379 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)380 %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 1, <16 x i1> %1)381 ret <16 x i8> %2382}383 384define arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {385; CHECK-LABEL: test_vqdmlsdhxq_m_s16:386; CHECK: @ %bb.0: @ %entry387; CHECK-NEXT: vmsr p0, r0388; CHECK-NEXT: vpst389; CHECK-NEXT: vqdmlsdhxt.s16 q0, q1, q2390; CHECK-NEXT: bx lr391entry:392 %0 = zext i16 %p to i32393 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)394 %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 1, <8 x i1> %1)395 ret <8 x i16> %2396}397 398define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {399; CHECK-LABEL: test_vqdmlsdhxq_m_s32:400; CHECK: @ %bb.0: @ %entry401; CHECK-NEXT: vmsr p0, r0402; CHECK-NEXT: vpst403; CHECK-NEXT: vqdmlsdhxt.s32 q0, q1, q2404; CHECK-NEXT: bx lr405entry:406 %0 = zext i16 %p to i32407 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)408 %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 1, <4 x i1> %1)409 ret <4 x i32> %2410}411 412define arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {413; CHECK-LABEL: test_vqrdmladhq_m_s8:414; CHECK: @ %bb.0: @ %entry415; CHECK-NEXT: vmsr p0, r0416; CHECK-NEXT: vpst417; CHECK-NEXT: vqrdmladht.s8 q0, q1, q2418; CHECK-NEXT: bx lr419entry:420 %0 = zext i16 %p to i32421 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)422 %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0, <16 x i1> %1)423 ret <16 x i8> %2424}425 426define arm_aapcs_vfpcc <8 x i16> @test_vqrdmladhq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {427; CHECK-LABEL: test_vqrdmladhq_m_s16:428; CHECK: @ %bb.0: @ %entry429; CHECK-NEXT: vmsr p0, r0430; CHECK-NEXT: vpst431; CHECK-NEXT: vqrdmladht.s16 q0, q1, q2432; CHECK-NEXT: bx lr433entry:434 %0 = zext i16 %p to i32435 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)436 %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 0, <8 x i1> %1)437 ret <8 x i16> %2438}439 440define arm_aapcs_vfpcc <4 x i32> @test_vqrdmladhq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {441; CHECK-LABEL: test_vqrdmladhq_m_s32:442; CHECK: @ %bb.0: @ %entry443; CHECK-NEXT: vmsr p0, r0444; CHECK-NEXT: vpst445; CHECK-NEXT: vqrdmladht.s32 q0, q1, q2446; CHECK-NEXT: bx lr447entry:448 %0 = zext i16 %p to i32449 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)450 %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 0, <4 x i1> %1)451 ret <4 x i32> %2452}453 454define arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhxq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {455; CHECK-LABEL: test_vqrdmladhxq_m_s8:456; CHECK: @ %bb.0: @ %entry457; CHECK-NEXT: vmsr p0, r0458; CHECK-NEXT: vpst459; CHECK-NEXT: vqrdmladhxt.s8 q0, q1, q2460; CHECK-NEXT: bx lr461entry:462 %0 = zext i16 %p to i32463 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)464 %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 0, <16 x i1> %1)465 ret <16 x i8> %2466}467 468define arm_aapcs_vfpcc <8 x i16> @test_vqrdmladhxq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {469; CHECK-LABEL: test_vqrdmladhxq_m_s16:470; CHECK: @ %bb.0: @ %entry471; CHECK-NEXT: vmsr p0, r0472; CHECK-NEXT: vpst473; CHECK-NEXT: vqrdmladhxt.s16 q0, q1, q2474; CHECK-NEXT: bx lr475entry:476 %0 = zext i16 %p to i32477 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)478 %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 0, <8 x i1> %1)479 ret <8 x i16> %2480}481 482define arm_aapcs_vfpcc <4 x i32> @test_vqrdmladhxq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {483; CHECK-LABEL: test_vqrdmladhxq_m_s32:484; CHECK: @ %bb.0: @ %entry485; CHECK-NEXT: vmsr p0, r0486; CHECK-NEXT: vpst487; CHECK-NEXT: vqrdmladhxt.s32 q0, q1, q2488; CHECK-NEXT: bx lr489entry:490 %0 = zext i16 %p to i32491 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)492 %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 0, <4 x i1> %1)493 ret <4 x i32> %2494}495 496define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlsdhq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {497; CHECK-LABEL: test_vqrdmlsdhq_m_s8:498; CHECK: @ %bb.0: @ %entry499; CHECK-NEXT: vmsr p0, r0500; CHECK-NEXT: vpst501; CHECK-NEXT: vqrdmlsdht.s8 q0, q1, q2502; CHECK-NEXT: bx lr503entry:504 %0 = zext i16 %p to i32505 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)506 %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 1, <16 x i1> %1)507 ret <16 x i8> %2508}509 510define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlsdhq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {511; CHECK-LABEL: test_vqrdmlsdhq_m_s16:512; CHECK: @ %bb.0: @ %entry513; CHECK-NEXT: vmsr p0, r0514; CHECK-NEXT: vpst515; CHECK-NEXT: vqrdmlsdht.s16 q0, q1, q2516; CHECK-NEXT: bx lr517entry:518 %0 = zext i16 %p to i32519 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)520 %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 1, <8 x i1> %1)521 ret <8 x i16> %2522}523 524define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlsdhq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {525; CHECK-LABEL: test_vqrdmlsdhq_m_s32:526; CHECK: @ %bb.0: @ %entry527; CHECK-NEXT: vmsr p0, r0528; CHECK-NEXT: vpst529; CHECK-NEXT: vqrdmlsdht.s32 q0, q1, q2530; CHECK-NEXT: bx lr531entry:532 %0 = zext i16 %p to i32533 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)534 %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 1, <4 x i1> %1)535 ret <4 x i32> %2536}537 538define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlsdhxq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {539; CHECK-LABEL: test_vqrdmlsdhxq_m_s8:540; CHECK: @ %bb.0: @ %entry541; CHECK-NEXT: vmsr p0, r0542; CHECK-NEXT: vpst543; CHECK-NEXT: vqrdmlsdhxt.s8 q0, q1, q2544; CHECK-NEXT: bx lr545entry:546 %0 = zext i16 %p to i32547 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)548 %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 1, <16 x i1> %1)549 ret <16 x i8> %2550}551 552define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlsdhxq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {553; CHECK-LABEL: test_vqrdmlsdhxq_m_s16:554; CHECK: @ %bb.0: @ %entry555; CHECK-NEXT: vmsr p0, r0556; CHECK-NEXT: vpst557; CHECK-NEXT: vqrdmlsdhxt.s16 q0, q1, q2558; CHECK-NEXT: bx lr559entry:560 %0 = zext i16 %p to i32561 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)562 %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 1, <8 x i1> %1)563 ret <8 x i16> %2564}565 566define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlsdhxq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {567; CHECK-LABEL: test_vqrdmlsdhxq_m_s32:568; CHECK: @ %bb.0: @ %entry569; CHECK-NEXT: vmsr p0, r0570; CHECK-NEXT: vpst571; CHECK-NEXT: vqrdmlsdhxt.s32 q0, q1, q2572; CHECK-NEXT: bx lr573entry:574 %0 = zext i16 %p to i32575 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)576 %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 1, <4 x i1> %1)577 ret <4 x i32> %2578}579 580declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)581declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)582declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)583 584declare <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32)585declare <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32)586declare <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32)587declare <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32, <16 x i1>)588declare <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32, <8 x i1>)589declare <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32, <4 x i1>)590