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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s3 4declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)5declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32)6 7declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32)8declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32)9declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>)10declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>)11 12define arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_s16(<8 x i16> %a, <8 x i16> %b) {13; CHECK-LABEL: test_vqdmullbq_s16:14; CHECK: @ %bb.0: @ %entry15; CHECK-NEXT: vqdmullb.s16 q0, q0, q116; CHECK-NEXT: bx lr17entry:18 %0 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0)19 ret <4 x i32> %020}21 22define arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_s32(<4 x i32> %a, <4 x i32> %b) {23; CHECK-LABEL: test_vqdmullbq_s32:24; CHECK: @ %bb.0: @ %entry25; CHECK-NEXT: vqdmullb.s32 q2, q0, q126; CHECK-NEXT: vmov q0, q227; CHECK-NEXT: bx lr28entry:29 %0 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0)30 ret <2 x i64> %031}32 33define arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_s16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {34; CHECK-LABEL: test_vqdmullbq_m_s16:35; CHECK: @ %bb.0: @ %entry36; CHECK-NEXT: vmsr p0, r037; CHECK-NEXT: vpst38; CHECK-NEXT: vqdmullbt.s16 q0, q1, q239; CHECK-NEXT: bx lr40entry:41 %0 = zext i16 %p to i3242 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)43 %2 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 0, <4 x i1> %1, <4 x i32> %inactive)44 ret <4 x i32> %245}46 47define arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {48; CHECK-LABEL: test_vqdmullbq_m_s32:49; CHECK: @ %bb.0: @ %entry50; CHECK-NEXT: vmsr p0, r051; CHECK-NEXT: vpst52; CHECK-NEXT: vqdmullbt.s32 q0, q1, q253; CHECK-NEXT: bx lr54entry:55 %0 = zext i16 %p to i3256 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)57 %2 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %a, <4 x i32> %b, i32 0, <2 x i1> %1, <2 x i64> %inactive)58 ret <2 x i64> %259}60 61define arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_n_s16(<8 x i16> %a, i16 signext %b) {62; CHECK-LABEL: test_vqdmullbq_n_s16:63; CHECK: @ %bb.0: @ %entry64; CHECK-NEXT: vqdmullb.s16 q0, q0, r065; CHECK-NEXT: bx lr66entry:67 %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 068 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer69 %0 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %.splat, i32 0)70 ret <4 x i32> %071}72 73define arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_n_s32(<4 x i32> %a, i32 %b) #0 {74; CHECK-LABEL: test_vqdmullbq_n_s32:75; CHECK: @ %bb.0: @ %entry76; CHECK-NEXT: vqdmullb.s32 q1, q0, r077; CHECK-NEXT: vmov q0, q178; CHECK-NEXT: bx lr79entry:80 %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 081 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer82 %0 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %.splat, i32 0)83 ret <2 x i64> %084}85 86define arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_n_s16(<4 x i32> %inactive, <8 x i16> %a, i16 signext %b, i16 zeroext %p) {87; CHECK-LABEL: test_vqdmullbq_m_n_s16:88; CHECK: @ %bb.0: @ %entry89; CHECK-NEXT: vmsr p0, r190; CHECK-NEXT: vpst91; CHECK-NEXT: vqdmullbt.s16 q0, q1, r092; CHECK-NEXT: bx lr93entry:94 %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 095 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer96 %0 = zext i16 %p to i3297 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)98 %2 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %.splat, i32 0, <4 x i1> %1, <4 x i32> %inactive)99 ret <4 x i32> %2100}101 102define arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_n_s32(<2 x i64> %inactive, <4 x i32> %a, i32 %b, i16 zeroext %p) {103; CHECK-LABEL: test_vqdmullbq_m_n_s32:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vmsr p0, r1106; CHECK-NEXT: vpst107; CHECK-NEXT: vqdmullbt.s32 q0, q1, r0108; CHECK-NEXT: bx lr109entry:110 %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0111 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer112 %0 = zext i16 %p to i32113 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)114 %2 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %a, <4 x i32> %.splat, i32 0, <2 x i1> %1, <2 x i64> %inactive)115 ret <2 x i64> %2116}117 118define arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_s16(<8 x i16> %a, <8 x i16> %b) {119; CHECK-LABEL: test_vqdmulltq_s16:120; CHECK: @ %bb.0: @ %entry121; CHECK-NEXT: vqdmullt.s16 q0, q0, q1122; CHECK-NEXT: bx lr123entry:124 %0 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1)125 ret <4 x i32> %0126}127 128define arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_s32(<4 x i32> %a, <4 x i32> %b) {129; CHECK-LABEL: test_vqdmulltq_s32:130; CHECK: @ %bb.0: @ %entry131; CHECK-NEXT: vqdmullt.s32 q2, q0, q1132; CHECK-NEXT: vmov q0, q2133; CHECK-NEXT: bx lr134entry:135 %0 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1)136 ret <2 x i64> %0137}138 139define arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_s16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {140; CHECK-LABEL: test_vqdmulltq_m_s16:141; CHECK: @ %bb.0: @ %entry142; CHECK-NEXT: vmsr p0, r0143; CHECK-NEXT: vpst144; CHECK-NEXT: vqdmulltt.s16 q0, q1, q2145; CHECK-NEXT: bx lr146entry:147 %0 = zext i16 %p to i32148 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)149 %2 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 1, <4 x i1> %1, <4 x i32> %inactive)150 ret <4 x i32> %2151}152 153define arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {154; CHECK-LABEL: test_vqdmulltq_m_s32:155; CHECK: @ %bb.0: @ %entry156; CHECK-NEXT: vmsr p0, r0157; CHECK-NEXT: vpst158; CHECK-NEXT: vqdmulltt.s32 q0, q1, q2159; CHECK-NEXT: bx lr160entry:161 %0 = zext i16 %p to i32162 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)163 %2 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %a, <4 x i32> %b, i32 1, <2 x i1> %1, <2 x i64> %inactive)164 ret <2 x i64> %2165}166 167define arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_n_s16(<8 x i16> %a, i16 signext %b) {168; CHECK-LABEL: test_vqdmulltq_n_s16:169; CHECK: @ %bb.0: @ %entry170; CHECK-NEXT: vqdmullt.s16 q0, q0, r0171; CHECK-NEXT: bx lr172entry:173 %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0174 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer175 %0 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %.splat, i32 1)176 ret <4 x i32> %0177}178 179define arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_n_s32(<4 x i32> %a, i32 %b) {180; CHECK-LABEL: test_vqdmulltq_n_s32:181; CHECK: @ %bb.0: @ %entry182; CHECK-NEXT: vqdmullt.s32 q1, q0, r0183; CHECK-NEXT: vmov q0, q1184; CHECK-NEXT: bx lr185entry:186 %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0187 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer188 %0 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %.splat, i32 1)189 ret <2 x i64> %0190}191 192define arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_n_s16(<4 x i32> %inactive, <8 x i16> %a, i16 signext %b, i16 zeroext %p) {193; CHECK-LABEL: test_vqdmulltq_m_n_s16:194; CHECK: @ %bb.0: @ %entry195; CHECK-NEXT: vmsr p0, r1196; CHECK-NEXT: vpst197; CHECK-NEXT: vqdmulltt.s16 q0, q1, r0198; CHECK-NEXT: bx lr199entry:200 %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0201 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer202 %0 = zext i16 %p to i32203 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)204 %2 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %.splat, i32 1, <4 x i1> %1, <4 x i32> %inactive)205 ret <4 x i32> %2206}207 208define arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_n_s32(<2 x i64> %inactive, <4 x i32> %a, i32 %b, i16 zeroext %p) {209; CHECK-LABEL: test_vqdmulltq_m_n_s32:210; CHECK: @ %bb.0: @ %entry211; CHECK-NEXT: vmsr p0, r1212; CHECK-NEXT: vpst213; CHECK-NEXT: vqdmulltt.s32 q0, q1, r0214; CHECK-NEXT: bx lr215entry:216 %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0217 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer218 %0 = zext i16 %p to i32219 %1 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)220 %2 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %a, <4 x i32> %.splat, i32 1, <2 x i1> %1, <2 x i64> %inactive)221 ret <2 x i64> %2222}223