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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_s16(<16 x i8> %a, <8 x i16> %b) {5; CHECK-LABEL: test_vqmovnbq_s16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vqmovnb.s16 q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 0, i32 0, i32 0)11 ret <16 x i8> %012}13 14define arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_s32(<8 x i16> %a, <4 x i32> %b) {15; CHECK-LABEL: test_vqmovnbq_s32:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vqmovnb.s32 q0, q118; CHECK-NEXT: bx lr19entry:20 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 0, i32 0, i32 0)21 ret <8 x i16> %022}23 24define arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_u16(<16 x i8> %a, <8 x i16> %b) {25; CHECK-LABEL: test_vqmovnbq_u16:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vqmovnb.u16 q0, q128; CHECK-NEXT: bx lr29entry:30 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 0)31 ret <16 x i8> %032}33 34define arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_u32(<8 x i16> %a, <4 x i32> %b) {35; CHECK-LABEL: test_vqmovnbq_u32:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vqmovnb.u32 q0, q138; CHECK-NEXT: bx lr39entry:40 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 1, i32 1, i32 0)41 ret <8 x i16> %042}43 44define arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_s16(<16 x i8> %a, <8 x i16> %b) {45; CHECK-LABEL: test_vqmovntq_s16:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: vqmovnt.s16 q0, q148; CHECK-NEXT: bx lr49entry:50 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 0, i32 0, i32 1)51 ret <16 x i8> %052}53 54define arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_s32(<8 x i16> %a, <4 x i32> %b) {55; CHECK-LABEL: test_vqmovntq_s32:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vqmovnt.s32 q0, q158; CHECK-NEXT: bx lr59entry:60 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 0, i32 0, i32 1)61 ret <8 x i16> %062}63 64define arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_u16(<16 x i8> %a, <8 x i16> %b) {65; CHECK-LABEL: test_vqmovntq_u16:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vqmovnt.u16 q0, q168; CHECK-NEXT: bx lr69entry:70 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 1)71 ret <16 x i8> %072}73 74define arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_u32(<8 x i16> %a, <4 x i32> %b) {75; CHECK-LABEL: test_vqmovntq_u32:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vqmovnt.u32 q0, q178; CHECK-NEXT: bx lr79entry:80 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 1, i32 1, i32 1)81 ret <8 x i16> %082}83 84define arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_s16(<16 x i8> %a, <8 x i16> %b) {85; CHECK-LABEL: test_vqmovunbq_s16:86; CHECK: @ %bb.0: @ %entry87; CHECK-NEXT: vqmovunb.s16 q0, q188; CHECK-NEXT: bx lr89entry:90 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 0)91 ret <16 x i8> %092}93 94define arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_s32(<8 x i16> %a, <4 x i32> %b) {95; CHECK-LABEL: test_vqmovunbq_s32:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: vqmovunb.s32 q0, q198; CHECK-NEXT: bx lr99entry:100 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 1, i32 0, i32 0)101 ret <8 x i16> %0102}103 104define arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_s16(<16 x i8> %a, <8 x i16> %b) {105; CHECK-LABEL: test_vqmovuntq_s16:106; CHECK: @ %bb.0: @ %entry107; CHECK-NEXT: vqmovunt.s16 q0, q1108; CHECK-NEXT: bx lr109entry:110 %0 = tail call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 1)111 ret <16 x i8> %0112}113 114define arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_s32(<8 x i16> %a, <4 x i32> %b) {115; CHECK-LABEL: test_vqmovuntq_s32:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: vqmovunt.s32 q0, q1118; CHECK-NEXT: bx lr119entry:120 %0 = tail call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %a, <4 x i32> %b, i32 1, i32 0, i32 1)121 ret <8 x i16> %0122}123 124define arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {125; CHECK-LABEL: test_vqmovnbq_m_s16:126; CHECK: @ %bb.0: @ %entry127; CHECK-NEXT: vmsr p0, r0128; CHECK-NEXT: vpst129; CHECK-NEXT: vqmovnbt.s16 q0, q1130; CHECK-NEXT: bx lr131entry:132 %0 = zext i16 %p to i32133 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)134 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 0, i32 0, i32 0, <8 x i1> %1)135 ret <16 x i8> %2136}137 138define arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {139; CHECK-LABEL: test_vqmovnbq_m_s32:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: vmsr p0, r0142; CHECK-NEXT: vpst143; CHECK-NEXT: vqmovnbt.s32 q0, q1144; CHECK-NEXT: bx lr145entry:146 %0 = zext i16 %p to i32147 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)148 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 0, i32 0, i32 0, <4 x i1> %1)149 ret <8 x i16> %2150}151 152define arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {153; CHECK-LABEL: test_vqmovnbq_m_u16:154; CHECK: @ %bb.0: @ %entry155; CHECK-NEXT: vmsr p0, r0156; CHECK-NEXT: vpst157; CHECK-NEXT: vqmovnbt.u16 q0, q1158; CHECK-NEXT: bx lr159entry:160 %0 = zext i16 %p to i32161 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)162 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 0, <8 x i1> %1)163 ret <16 x i8> %2164}165 166define arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {167; CHECK-LABEL: test_vqmovnbq_m_u32:168; CHECK: @ %bb.0: @ %entry169; CHECK-NEXT: vmsr p0, r0170; CHECK-NEXT: vpst171; CHECK-NEXT: vqmovnbt.u32 q0, q1172; CHECK-NEXT: bx lr173entry:174 %0 = zext i16 %p to i32175 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)176 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, i32 1, i32 0, <4 x i1> %1)177 ret <8 x i16> %2178}179 180define arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_m_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {181; CHECK-LABEL: test_vqmovntq_m_s16:182; CHECK: @ %bb.0: @ %entry183; CHECK-NEXT: vmsr p0, r0184; CHECK-NEXT: vpst185; CHECK-NEXT: vqmovntt.s16 q0, q1186; CHECK-NEXT: bx lr187entry:188 %0 = zext i16 %p to i32189 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)190 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 0, i32 0, i32 1, <8 x i1> %1)191 ret <16 x i8> %2192}193 194define arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_m_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {195; CHECK-LABEL: test_vqmovntq_m_s32:196; CHECK: @ %bb.0: @ %entry197; CHECK-NEXT: vmsr p0, r0198; CHECK-NEXT: vpst199; CHECK-NEXT: vqmovntt.s32 q0, q1200; CHECK-NEXT: bx lr201entry:202 %0 = zext i16 %p to i32203 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)204 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 0, i32 0, i32 1, <4 x i1> %1)205 ret <8 x i16> %2206}207 208define arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_m_u16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {209; CHECK-LABEL: test_vqmovntq_m_u16:210; CHECK: @ %bb.0: @ %entry211; CHECK-NEXT: vmsr p0, r0212; CHECK-NEXT: vpst213; CHECK-NEXT: vqmovntt.u16 q0, q1214; CHECK-NEXT: bx lr215entry:216 %0 = zext i16 %p to i32217 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)218 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 1, i32 1, <8 x i1> %1)219 ret <16 x i8> %2220}221 222define arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_m_u32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {223; CHECK-LABEL: test_vqmovntq_m_u32:224; CHECK: @ %bb.0: @ %entry225; CHECK-NEXT: vmsr p0, r0226; CHECK-NEXT: vpst227; CHECK-NEXT: vqmovntt.u32 q0, q1228; CHECK-NEXT: bx lr229entry:230 %0 = zext i16 %p to i32231 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)232 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, i32 1, i32 1, <4 x i1> %1)233 ret <8 x i16> %2234}235 236define arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_m_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {237; CHECK-LABEL: test_vqmovunbq_m_s16:238; CHECK: @ %bb.0: @ %entry239; CHECK-NEXT: vmsr p0, r0240; CHECK-NEXT: vpst241; CHECK-NEXT: vqmovunbt.s16 q0, q1242; CHECK-NEXT: bx lr243entry:244 %0 = zext i16 %p to i32245 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)246 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 0, <8 x i1> %1)247 ret <16 x i8> %2248}249 250define arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_m_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {251; CHECK-LABEL: test_vqmovunbq_m_s32:252; CHECK: @ %bb.0: @ %entry253; CHECK-NEXT: vmsr p0, r0254; CHECK-NEXT: vpst255; CHECK-NEXT: vqmovunbt.s32 q0, q1256; CHECK-NEXT: bx lr257entry:258 %0 = zext i16 %p to i32259 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)260 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, i32 0, i32 0, <4 x i1> %1)261 ret <8 x i16> %2262}263 264define arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_m_s16(<16 x i8> %a, <8 x i16> %b, i16 zeroext %p) {265; CHECK-LABEL: test_vqmovuntq_m_s16:266; CHECK: @ %bb.0: @ %entry267; CHECK-NEXT: vmsr p0, r0268; CHECK-NEXT: vpst269; CHECK-NEXT: vqmovuntt.s16 q0, q1270; CHECK-NEXT: bx lr271entry:272 %0 = zext i16 %p to i32273 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)274 %2 = tail call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %b, i32 1, i32 0, i32 1, <8 x i1> %1)275 ret <16 x i8> %2276}277 278define arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_m_s32(<8 x i16> %a, <4 x i32> %b, i16 zeroext %p) {279; CHECK-LABEL: test_vqmovuntq_m_s32:280; CHECK: @ %bb.0: @ %entry281; CHECK-NEXT: vmsr p0, r0282; CHECK-NEXT: vpst283; CHECK-NEXT: vqmovuntt.s32 q0, q1284; CHECK-NEXT: bx lr285entry:286 %0 = zext i16 %p to i32287 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)288 %2 = tail call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %b, i32 1, i32 0, i32 1, <4 x i1> %1)289 ret <8 x i16> %2290}291 292declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)293declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)294 295declare <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32)296declare <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32)297 298declare <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, <8 x i1>)299declare <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, <4 x i1>)300