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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vqsubq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {5; CHECK-LABEL: test_vqsubq_u8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vqsub.u8 q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = tail call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %a, <16 x i8> %b)11 ret <16 x i8> %012}13 14declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) #115 16define arm_aapcs_vfpcc <8 x i16> @test_vqsubq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {17; CHECK-LABEL: test_vqsubq_s16:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vqsub.s16 q0, q0, q120; CHECK-NEXT: bx lr21entry:22 %0 = tail call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a, <8 x i16> %b)23 ret <8 x i16> %024}25 26declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #127 28define arm_aapcs_vfpcc <4 x i32> @test_vqsubq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {29; CHECK-LABEL: test_vqsubq_u32:30; CHECK: @ %bb.0: @ %entry31; CHECK-NEXT: vqsub.u32 q0, q0, q132; CHECK-NEXT: bx lr33entry:34 %0 = tail call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %a, <4 x i32> %b)35 ret <4 x i32> %036}37 38declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #139 40define arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {41; CHECK-LABEL: test_vqsubq_m_s8:42; CHECK: @ %bb.0: @ %entry43; CHECK-NEXT: vmsr p0, r044; CHECK-NEXT: vpst45; CHECK-NEXT: vqsubt.s8 q0, q1, q246; CHECK-NEXT: bx lr47entry:48 %0 = zext i16 %p to i3249 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)50 %2 = tail call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <16 x i8> %inactive)51 ret <16 x i8> %252}53 54declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #255 56declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #257 58define arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {59; CHECK-LABEL: test_vqsubq_m_u16:60; CHECK: @ %bb.0: @ %entry61; CHECK-NEXT: vmsr p0, r062; CHECK-NEXT: vpst63; CHECK-NEXT: vqsubt.u16 q0, q1, q264; CHECK-NEXT: bx lr65entry:66 %0 = zext i16 %p to i3267 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)68 %2 = tail call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, <8 x i1> %1, <8 x i16> %inactive)69 ret <8 x i16> %270}71 72declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #273 74declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #275 76define arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {77; CHECK-LABEL: test_vqsubq_m_s32:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vmsr p0, r080; CHECK-NEXT: vpst81; CHECK-NEXT: vqsubt.s32 q0, q1, q282; CHECK-NEXT: bx lr83entry:84 %0 = zext i16 %p to i3285 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)86 %2 = tail call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1, <4 x i32> %inactive)87 ret <4 x i32> %288}89 90declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #291 92declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #293 94define arm_aapcs_vfpcc <16 x i8> @test_vqsubq_n_u8(<16 x i8> %a, i8 zeroext %b) {95; CHECK-LABEL: test_vqsubq_n_u8:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: vqsub.u8 q0, q0, r098; CHECK-NEXT: bx lr99entry:100 %.splatinsert = insertelement <16 x i8> undef, i8 %b, i32 0101 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer102 %0 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %a, <16 x i8> %.splat)103 ret <16 x i8> %0104}105 106define arm_aapcs_vfpcc <8 x i16> @test_vqsubq_n_s16(<8 x i16> %a, i16 signext %b) {107; CHECK-LABEL: test_vqsubq_n_s16:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: vqsub.s16 q0, q0, r0110; CHECK-NEXT: bx lr111entry:112 %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0113 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer114 %0 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a, <8 x i16> %.splat)115 ret <8 x i16> %0116}117 118define arm_aapcs_vfpcc <4 x i32> @test_vqsubq_n_u32(<4 x i32> %a, i32 %b) {119; CHECK-LABEL: test_vqsubq_n_u32:120; CHECK: @ %bb.0: @ %entry121; CHECK-NEXT: vqsub.u32 q0, q0, r0122; CHECK-NEXT: bx lr123entry:124 %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0125 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer126 %0 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %a, <4 x i32> %.splat)127 ret <4 x i32> %0128}129 130define arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i8 signext %b, i16 zeroext %p) {131; CHECK-LABEL: test_vqsubq_m_n_s8:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: vmsr p0, r1134; CHECK-NEXT: vpst135; CHECK-NEXT: vqsubt.s8 q0, q1, r0136; CHECK-NEXT: bx lr137entry:138 %.splatinsert = insertelement <16 x i8> undef, i8 %b, i32 0139 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer140 %0 = zext i16 %p to i32141 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)142 %2 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %.splat, i32 0, <16 x i1> %1, <16 x i8> %inactive)143 ret <16 x i8> %2144}145 146define arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_n_u16(<8 x i16> %inactive, <8 x i16> %a, i16 zeroext %b, i16 zeroext %p) {147; CHECK-LABEL: test_vqsubq_m_n_u16:148; CHECK: @ %bb.0: @ %entry149; CHECK-NEXT: vmsr p0, r1150; CHECK-NEXT: vpst151; CHECK-NEXT: vqsubt.u16 q0, q1, r0152; CHECK-NEXT: bx lr153entry:154 %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0155 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer156 %0 = zext i16 %p to i32157 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)158 %2 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %.splat, i32 1, <8 x i1> %1, <8 x i16> %inactive)159 ret <8 x i16> %2160}161 162define arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_n_s32(<4 x i32> %inactive, <4 x i32> %a, i32 %b, i16 zeroext %p) {163; CHECK-LABEL: test_vqsubq_m_n_s32:164; CHECK: @ %bb.0: @ %entry165; CHECK-NEXT: vmsr p0, r1166; CHECK-NEXT: vpst167; CHECK-NEXT: vqsubt.s32 q0, q1, r0168; CHECK-NEXT: bx lr169entry:170 %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0171 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer172 %0 = zext i16 %p to i32173 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)174 %2 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %.splat, i32 0, <4 x i1> %1, <4 x i32> %inactive)175 ret <4 x i32> %2176}177