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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <8 x half> @test_vrndaq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) {5; CHECK-LABEL: test_vrndaq_m_f16:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vmsr p0, r08; CHECK-NEXT: vpst9; CHECK-NEXT: vrintat.f16 q0, q110; CHECK-NEXT: bx lr11entry:12 %0 = zext i16 %p to i3213 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)14 %2 = tail call <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive)15 ret <8 x half> %216}17 18define arm_aapcs_vfpcc <4 x float> @test_vrndaq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) {19; CHECK-LABEL: test_vrndaq_m_f32:20; CHECK: @ %bb.0: @ %entry21; CHECK-NEXT: vmsr p0, r022; CHECK-NEXT: vpst23; CHECK-NEXT: vrintat.f32 q0, q124; CHECK-NEXT: bx lr25entry:26 %0 = zext i16 %p to i3227 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)28 %2 = tail call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive)29 ret <4 x float> %230}31 32define arm_aapcs_vfpcc <8 x half> @test_vrndmq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) {33; CHECK-LABEL: test_vrndmq_m_f16:34; CHECK: @ %bb.0: @ %entry35; CHECK-NEXT: vmsr p0, r036; CHECK-NEXT: vpst37; CHECK-NEXT: vrintmt.f16 q0, q138; CHECK-NEXT: bx lr39entry:40 %0 = zext i16 %p to i3241 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)42 %2 = tail call <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive)43 ret <8 x half> %244}45 46define arm_aapcs_vfpcc <4 x float> @test_vrndmq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) {47; CHECK-LABEL: test_vrndmq_m_f32:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: vmsr p0, r050; CHECK-NEXT: vpst51; CHECK-NEXT: vrintmt.f32 q0, q152; CHECK-NEXT: bx lr53entry:54 %0 = zext i16 %p to i3255 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)56 %2 = tail call <4 x float> @llvm.arm.mve.vrintm.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive)57 ret <4 x float> %258}59 60define arm_aapcs_vfpcc <8 x half> @test_vrndnq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) {61; CHECK-LABEL: test_vrndnq_m_f16:62; CHECK: @ %bb.0: @ %entry63; CHECK-NEXT: vmsr p0, r064; CHECK-NEXT: vpst65; CHECK-NEXT: vrintnt.f16 q0, q166; CHECK-NEXT: bx lr67entry:68 %0 = zext i16 %p to i3269 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)70 %2 = tail call <8 x half> @llvm.arm.mve.vrintn.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive)71 ret <8 x half> %272}73 74define arm_aapcs_vfpcc <4 x float> @test_vrndnq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) {75; CHECK-LABEL: test_vrndnq_m_f32:76; CHECK: @ %bb.0: @ %entry77; CHECK-NEXT: vmsr p0, r078; CHECK-NEXT: vpst79; CHECK-NEXT: vrintnt.f32 q0, q180; CHECK-NEXT: bx lr81entry:82 %0 = zext i16 %p to i3283 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)84 %2 = tail call <4 x float> @llvm.arm.mve.vrintn.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive)85 ret <4 x float> %286}87 88define arm_aapcs_vfpcc <8 x half> @test_vrndpq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) {89; CHECK-LABEL: test_vrndpq_m_f16:90; CHECK: @ %bb.0: @ %entry91; CHECK-NEXT: vmsr p0, r092; CHECK-NEXT: vpst93; CHECK-NEXT: vrintpt.f16 q0, q194; CHECK-NEXT: bx lr95entry:96 %0 = zext i16 %p to i3297 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)98 %2 = tail call <8 x half> @llvm.arm.mve.vrintp.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive)99 ret <8 x half> %2100}101 102define arm_aapcs_vfpcc <4 x float> @test_vrndpq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) {103; CHECK-LABEL: test_vrndpq_m_f32:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vmsr p0, r0106; CHECK-NEXT: vpst107; CHECK-NEXT: vrintpt.f32 q0, q1108; CHECK-NEXT: bx lr109entry:110 %0 = zext i16 %p to i32111 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)112 %2 = tail call <4 x float> @llvm.arm.mve.vrintp.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive)113 ret <4 x float> %2114}115 116define arm_aapcs_vfpcc <8 x half> @test_vrndq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) {117; CHECK-LABEL: test_vrndq_m_f16:118; CHECK: @ %bb.0: @ %entry119; CHECK-NEXT: vmsr p0, r0120; CHECK-NEXT: vpst121; CHECK-NEXT: vrintzt.f16 q0, q1122; CHECK-NEXT: bx lr123entry:124 %0 = zext i16 %p to i32125 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)126 %2 = tail call <8 x half> @llvm.arm.mve.vrintz.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive)127 ret <8 x half> %2128}129 130define arm_aapcs_vfpcc <4 x float> @test_vrndq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) {131; CHECK-LABEL: test_vrndq_m_f32:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: vmsr p0, r0134; CHECK-NEXT: vpst135; CHECK-NEXT: vrintzt.f32 q0, q1136; CHECK-NEXT: bx lr137entry:138 %0 = zext i16 %p to i32139 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)140 %2 = tail call <4 x float> @llvm.arm.mve.vrintz.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive)141 ret <4 x float> %2142}143 144define arm_aapcs_vfpcc <8 x half> @test_vrndxq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) {145; CHECK-LABEL: test_vrndxq_m_f16:146; CHECK: @ %bb.0: @ %entry147; CHECK-NEXT: vmsr p0, r0148; CHECK-NEXT: vpst149; CHECK-NEXT: vrintxt.f16 q0, q1150; CHECK-NEXT: bx lr151entry:152 %0 = zext i16 %p to i32153 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)154 %2 = tail call <8 x half> @llvm.arm.mve.vrintx.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive)155 ret <8 x half> %2156}157 158define arm_aapcs_vfpcc <4 x float> @test_vrndxq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) {159; CHECK-LABEL: test_vrndxq_m_f32:160; CHECK: @ %bb.0: @ %entry161; CHECK-NEXT: vmsr p0, r0162; CHECK-NEXT: vpst163; CHECK-NEXT: vrintxt.f32 q0, q1164; CHECK-NEXT: bx lr165entry:166 %0 = zext i16 %p to i32167 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)168 %2 = tail call <4 x float> @llvm.arm.mve.vrintx.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive)169 ret <4 x float> %2170}171 172declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)173declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)174declare <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>)175declare <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>)176declare <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>)177declare <4 x float> @llvm.arm.mve.vrintm.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>)178declare <8 x half> @llvm.arm.mve.vrintn.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>)179declare <4 x float> @llvm.arm.mve.vrintn.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>)180declare <8 x half> @llvm.arm.mve.vrintp.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>)181declare <4 x float> @llvm.arm.mve.vrintp.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>)182declare <8 x half> @llvm.arm.mve.vrintz.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>)183declare <4 x float> @llvm.arm.mve.vrintz.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>)184declare <8 x half> @llvm.arm.mve.vrintx.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>)185declare <4 x float> @llvm.arm.mve.vrintx.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>)186