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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <16 x i8> @test_vshlcq_s8(<16 x i8> %a, ptr nocapture %b) {5; CHECK-LABEL: test_vshlcq_s8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: ldr r1, [r0]8; CHECK-NEXT: vshlc q0, r1, #189; CHECK-NEXT: str r1, [r0]10; CHECK-NEXT: bx lr11entry:12 %0 = load i32, ptr %b, align 413 %1 = tail call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %a, i32 %0, i32 18)14 %2 = extractvalue { i32, <16 x i8> } %1, 015 store i32 %2, ptr %b, align 416 %3 = extractvalue { i32, <16 x i8> } %1, 117 ret <16 x i8> %318}19 20define arm_aapcs_vfpcc <8 x i16> @test_vshlcq_s16(<8 x i16> %a, ptr nocapture %b) {21; CHECK-LABEL: test_vshlcq_s16:22; CHECK: @ %bb.0: @ %entry23; CHECK-NEXT: ldr r1, [r0]24; CHECK-NEXT: vshlc q0, r1, #1625; CHECK-NEXT: str r1, [r0]26; CHECK-NEXT: bx lr27entry:28 %0 = load i32, ptr %b, align 429 %1 = tail call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %a, i32 %0, i32 16)30 %2 = extractvalue { i32, <8 x i16> } %1, 031 store i32 %2, ptr %b, align 432 %3 = extractvalue { i32, <8 x i16> } %1, 133 ret <8 x i16> %334}35 36define arm_aapcs_vfpcc <4 x i32> @test_vshlcq_s32(<4 x i32> %a, ptr nocapture %b) {37; CHECK-LABEL: test_vshlcq_s32:38; CHECK: @ %bb.0: @ %entry39; CHECK-NEXT: ldr r1, [r0]40; CHECK-NEXT: vshlc q0, r1, #441; CHECK-NEXT: str r1, [r0]42; CHECK-NEXT: bx lr43entry:44 %0 = load i32, ptr %b, align 445 %1 = tail call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %a, i32 %0, i32 4)46 %2 = extractvalue { i32, <4 x i32> } %1, 047 store i32 %2, ptr %b, align 448 %3 = extractvalue { i32, <4 x i32> } %1, 149 ret <4 x i32> %350}51 52define arm_aapcs_vfpcc <16 x i8> @test_vshlcq_u8(<16 x i8> %a, ptr nocapture %b) {53; CHECK-LABEL: test_vshlcq_u8:54; CHECK: @ %bb.0: @ %entry55; CHECK-NEXT: ldr r1, [r0]56; CHECK-NEXT: vshlc q0, r1, #1757; CHECK-NEXT: str r1, [r0]58; CHECK-NEXT: bx lr59entry:60 %0 = load i32, ptr %b, align 461 %1 = tail call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %a, i32 %0, i32 17)62 %2 = extractvalue { i32, <16 x i8> } %1, 063 store i32 %2, ptr %b, align 464 %3 = extractvalue { i32, <16 x i8> } %1, 165 ret <16 x i8> %366}67 68define arm_aapcs_vfpcc <8 x i16> @test_vshlcq_u16(<8 x i16> %a, ptr nocapture %b) {69; CHECK-LABEL: test_vshlcq_u16:70; CHECK: @ %bb.0: @ %entry71; CHECK-NEXT: ldr r1, [r0]72; CHECK-NEXT: vshlc q0, r1, #1773; CHECK-NEXT: str r1, [r0]74; CHECK-NEXT: bx lr75entry:76 %0 = load i32, ptr %b, align 477 %1 = tail call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %a, i32 %0, i32 17)78 %2 = extractvalue { i32, <8 x i16> } %1, 079 store i32 %2, ptr %b, align 480 %3 = extractvalue { i32, <8 x i16> } %1, 181 ret <8 x i16> %382}83 84define arm_aapcs_vfpcc <4 x i32> @test_vshlcq_u32(<4 x i32> %a, ptr nocapture %b) {85; CHECK-LABEL: test_vshlcq_u32:86; CHECK: @ %bb.0: @ %entry87; CHECK-NEXT: ldr r1, [r0]88; CHECK-NEXT: vshlc q0, r1, #2089; CHECK-NEXT: str r1, [r0]90; CHECK-NEXT: bx lr91entry:92 %0 = load i32, ptr %b, align 493 %1 = tail call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %a, i32 %0, i32 20)94 %2 = extractvalue { i32, <4 x i32> } %1, 095 store i32 %2, ptr %b, align 496 %3 = extractvalue { i32, <4 x i32> } %1, 197 ret <4 x i32> %398}99 100define arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_s8(<16 x i8> %a, ptr nocapture %b, i16 zeroext %p) {101; CHECK-LABEL: test_vshlcq_m_s8:102; CHECK: @ %bb.0: @ %entry103; CHECK-NEXT: vmsr p0, r1104; CHECK-NEXT: ldr r1, [r0]105; CHECK-NEXT: vpst106; CHECK-NEXT: vshlct q0, r1, #29107; CHECK-NEXT: str r1, [r0]108; CHECK-NEXT: bx lr109entry:110 %0 = load i32, ptr %b, align 4111 %1 = zext i16 %p to i32112 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)113 %3 = tail call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %a, i32 %0, i32 29, <16 x i1> %2)114 %4 = extractvalue { i32, <16 x i8> } %3, 0115 store i32 %4, ptr %b, align 4116 %5 = extractvalue { i32, <16 x i8> } %3, 1117 ret <16 x i8> %5118}119 120define arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_s16(<8 x i16> %a, ptr nocapture %b, i16 zeroext %p) {121; CHECK-LABEL: test_vshlcq_m_s16:122; CHECK: @ %bb.0: @ %entry123; CHECK-NEXT: vmsr p0, r1124; CHECK-NEXT: ldr r1, [r0]125; CHECK-NEXT: vpst126; CHECK-NEXT: vshlct q0, r1, #17127; CHECK-NEXT: str r1, [r0]128; CHECK-NEXT: bx lr129entry:130 %0 = load i32, ptr %b, align 4131 %1 = zext i16 %p to i32132 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)133 %3 = tail call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %a, i32 %0, i32 17, <8 x i1> %2)134 %4 = extractvalue { i32, <8 x i16> } %3, 0135 store i32 %4, ptr %b, align 4136 %5 = extractvalue { i32, <8 x i16> } %3, 1137 ret <8 x i16> %5138}139 140define arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_s32(<4 x i32> %a, ptr nocapture %b, i16 zeroext %p) {141; CHECK-LABEL: test_vshlcq_m_s32:142; CHECK: @ %bb.0: @ %entry143; CHECK-NEXT: vmsr p0, r1144; CHECK-NEXT: ldr r1, [r0]145; CHECK-NEXT: vpst146; CHECK-NEXT: vshlct q0, r1, #9147; CHECK-NEXT: str r1, [r0]148; CHECK-NEXT: bx lr149entry:150 %0 = load i32, ptr %b, align 4151 %1 = zext i16 %p to i32152 %2 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)153 %3 = tail call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> %a, i32 %0, i32 9, <4 x i1> %2)154 %4 = extractvalue { i32, <4 x i32> } %3, 0155 store i32 %4, ptr %b, align 4156 %5 = extractvalue { i32, <4 x i32> } %3, 1157 ret <4 x i32> %5158}159 160define arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_u8(<16 x i8> %a, ptr nocapture %b, i16 zeroext %p) {161; CHECK-LABEL: test_vshlcq_m_u8:162; CHECK: @ %bb.0: @ %entry163; CHECK-NEXT: vmsr p0, r1164; CHECK-NEXT: ldr r1, [r0]165; CHECK-NEXT: vpst166; CHECK-NEXT: vshlct q0, r1, #21167; CHECK-NEXT: str r1, [r0]168; CHECK-NEXT: bx lr169entry:170 %0 = load i32, ptr %b, align 4171 %1 = zext i16 %p to i32172 %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)173 %3 = tail call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %a, i32 %0, i32 21, <16 x i1> %2)174 %4 = extractvalue { i32, <16 x i8> } %3, 0175 store i32 %4, ptr %b, align 4176 %5 = extractvalue { i32, <16 x i8> } %3, 1177 ret <16 x i8> %5178}179 180define arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_u16(<8 x i16> %a, ptr nocapture %b, i16 zeroext %p) {181; CHECK-LABEL: test_vshlcq_m_u16:182; CHECK: @ %bb.0: @ %entry183; CHECK-NEXT: vmsr p0, r1184; CHECK-NEXT: ldr r1, [r0]185; CHECK-NEXT: vpst186; CHECK-NEXT: vshlct q0, r1, #24187; CHECK-NEXT: str r1, [r0]188; CHECK-NEXT: bx lr189entry:190 %0 = load i32, ptr %b, align 4191 %1 = zext i16 %p to i32192 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)193 %3 = tail call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %a, i32 %0, i32 24, <8 x i1> %2)194 %4 = extractvalue { i32, <8 x i16> } %3, 0195 store i32 %4, ptr %b, align 4196 %5 = extractvalue { i32, <8 x i16> } %3, 1197 ret <8 x i16> %5198}199 200define arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_u32(<4 x i32> %a, ptr nocapture %b, i16 zeroext %p) {201; CHECK-LABEL: test_vshlcq_m_u32:202; CHECK: @ %bb.0: @ %entry203; CHECK-NEXT: vmsr p0, r1204; CHECK-NEXT: ldr r1, [r0]205; CHECK-NEXT: vpst206; CHECK-NEXT: vshlct q0, r1, #26207; CHECK-NEXT: str r1, [r0]208; CHECK-NEXT: bx lr209entry:210 %0 = load i32, ptr %b, align 4211 %1 = zext i16 %p to i32212 %2 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)213 %3 = tail call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> %a, i32 %0, i32 26, <4 x i1> %2)214 %4 = extractvalue { i32, <4 x i32> } %3, 0215 store i32 %4, ptr %b, align 4216 %5 = extractvalue { i32, <4 x i32> } %3, 1217 ret <4 x i32> %5218}219 220declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8>, i32, i32)221declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16>, i32, i32)222declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32>, i32, i32)223declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)224declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>)225declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)226declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>)227declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)228declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>)229