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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @test_vsubq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {5; CHECK-LABEL: test_vsubq_u32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vsub.i32 q0, q0, q18; CHECK-NEXT: bx lr9entry:10 %0 = sub <4 x i32> %a, %b11 ret <4 x i32> %012}13 14define arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 {15; CHECK-LABEL: test_vsubq_f16:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vsub.f16 q0, q0, q118; CHECK-NEXT: bx lr19entry:20 %0 = fsub <8 x half> %a, %b21 ret <8 x half> %022}23 24define arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {25; CHECK-LABEL: test_vsubq_m_s8:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vmsr p0, r028; CHECK-NEXT: vpst29; CHECK-NEXT: vsubt.i8 q0, q1, q230; CHECK-NEXT: bx lr31entry:32 %0 = zext i16 %p to i3233 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)34 %2 = tail call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)35 ret <16 x i8> %236}37 38declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #239 40declare <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #241 42define arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {43; CHECK-LABEL: test_vsubq_m_f32:44; CHECK: @ %bb.0: @ %entry45; CHECK-NEXT: vmsr p0, r046; CHECK-NEXT: vpst47; CHECK-NEXT: vsubt.f32 q0, q1, q248; CHECK-NEXT: bx lr49entry:50 %0 = zext i16 %p to i3251 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)52 %2 = tail call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> %inactive)53 ret <4 x float> %254}55 56declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #257 58declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #259 60define arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {61; CHECK-LABEL: test_vsubq_x_u16:62; CHECK: @ %bb.0: @ %entry63; CHECK-NEXT: vmsr p0, r064; CHECK-NEXT: vpst65; CHECK-NEXT: vsubt.i16 q0, q0, q166; CHECK-NEXT: bx lr67entry:68 %0 = zext i16 %p to i3269 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)70 %2 = tail call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)71 ret <8 x i16> %272}73 74declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #275 76declare <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #277 78define arm_aapcs_vfpcc <8 x half> @test_vsubq_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {79; CHECK-LABEL: test_vsubq_x_f16:80; CHECK: @ %bb.0: @ %entry81; CHECK-NEXT: vmsr p0, r082; CHECK-NEXT: vpst83; CHECK-NEXT: vsubt.f16 q0, q0, q184; CHECK-NEXT: bx lr85entry:86 %0 = zext i16 %p to i3287 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)88 %2 = tail call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> undef)89 ret <8 x half> %290}91 92declare <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #293 94define arm_aapcs_vfpcc <4 x i32> @test_vsubq_n_u32(<4 x i32> %a, i32 %b) {95; CHECK-LABEL: test_vsubq_n_u32:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: vsub.i32 q0, q0, r098; CHECK-NEXT: bx lr99entry:100 %.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0101 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer102 %0 = sub <4 x i32> %a, %.splat103 ret <4 x i32> %0104}105 106define arm_aapcs_vfpcc <8 x half> @test_vsubq_n_f16(<8 x half> %a, float %b.coerce) {107; CHECK-LABEL: test_vsubq_n_f16:108; CHECK: @ %bb.0: @ %entry109; CHECK-NEXT: vmov r0, s4110; CHECK-NEXT: vsub.f16 q0, q0, r0111; CHECK-NEXT: bx lr112entry:113 %0 = bitcast float %b.coerce to i32114 %tmp.0.extract.trunc = trunc i32 %0 to i16115 %1 = bitcast i16 %tmp.0.extract.trunc to half116 %.splatinsert = insertelement <8 x half> undef, half %1, i32 0117 %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> undef, <8 x i32> zeroinitializer118 %2 = fsub <8 x half> %a, %.splat119 ret <8 x half> %2120}121 122define arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i8 signext %b, i16 zeroext %p) {123; CHECK-LABEL: test_vsubq_m_n_s8:124; CHECK: @ %bb.0: @ %entry125; CHECK-NEXT: vmsr p0, r1126; CHECK-NEXT: vpst127; CHECK-NEXT: vsubt.i8 q0, q1, r0128; CHECK-NEXT: bx lr129entry:130 %.splatinsert = insertelement <16 x i8> undef, i8 %b, i32 0131 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer132 %0 = zext i16 %p to i32133 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)134 %2 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %.splat, <16 x i1> %1, <16 x i8> %inactive)135 ret <16 x i8> %2136}137 138define arm_aapcs_vfpcc <4 x float> @test_vsubq_m_n_f32(<4 x float> %inactive, <4 x float> %a, float %b, i16 zeroext %p) {139; CHECK-LABEL: test_vsubq_m_n_f32:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: vmov r1, s8142; CHECK-NEXT: vmsr p0, r0143; CHECK-NEXT: vpst144; CHECK-NEXT: vsubt.f32 q0, q1, r1145; CHECK-NEXT: bx lr146entry:147 %.splatinsert = insertelement <4 x float> undef, float %b, i32 0148 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer149 %0 = zext i16 %p to i32150 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)151 %2 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %.splat, <4 x i1> %1, <4 x float> %inactive)152 ret <4 x float> %2153}154 155define arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_n_u16(<8 x i16> %a, i16 zeroext %b, i16 zeroext %p) {156; CHECK-LABEL: test_vsubq_x_n_u16:157; CHECK: @ %bb.0: @ %entry158; CHECK-NEXT: vmsr p0, r1159; CHECK-NEXT: vpst160; CHECK-NEXT: vsubt.i16 q0, q0, r0161; CHECK-NEXT: bx lr162entry:163 %.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0164 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer165 %0 = zext i16 %p to i32166 %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)167 %2 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %.splat, <8 x i1> %1, <8 x i16> undef)168 ret <8 x i16> %2169}170 171define arm_aapcs_vfpcc <8 x half> @test_vsubq_x_n_f16(<8 x half> %a, float %b.coerce, i16 zeroext %p) {172; CHECK-LABEL: test_vsubq_x_n_f16:173; CHECK: @ %bb.0: @ %entry174; CHECK-NEXT: vmov r1, s4175; CHECK-NEXT: vmsr p0, r0176; CHECK-NEXT: vpst177; CHECK-NEXT: vsubt.f16 q0, q0, r1178; CHECK-NEXT: bx lr179entry:180 %0 = bitcast float %b.coerce to i32181 %tmp.0.extract.trunc = trunc i32 %0 to i16182 %1 = bitcast i16 %tmp.0.extract.trunc to half183 %.splatinsert = insertelement <8 x half> undef, half %1, i32 0184 %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> undef, <8 x i32> zeroinitializer185 %2 = zext i16 %p to i32186 %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)187 %4 = call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %.splat, <8 x i1> %3, <8 x half> undef)188 ret <8 x half> %4189}190