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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @loads_i32(ptr %A, ptr %B, ptr %C) {5; CHECK-LABEL: loads_i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: .save {r4, r5, r6, lr}8; CHECK-NEXT: push {r4, r5, r6, lr}9; CHECK-NEXT: vldrw.u32 q2, [r1]10; CHECK-NEXT: vmov.i64 q1, #0xffffffff11; CHECK-NEXT: vmov.f32 s0, s1012; CHECK-NEXT: vmov.f32 s2, s1113; CHECK-NEXT: vand q0, q0, q114; CHECK-NEXT: vmov.f32 s10, s915; CHECK-NEXT: vmov r1, r3, d016; CHECK-NEXT: vand q2, q2, q117; CHECK-NEXT: vmov r4, r5, d118; CHECK-NEXT: vldrw.u32 q0, [r0]19; CHECK-NEXT: vldrw.u32 q1, [r2]20; CHECK-NEXT: vmov lr, r12, d521; CHECK-NEXT: vmov.f32 s12, s222; CHECK-NEXT: vmov.f32 s2, s323; CHECK-NEXT: vmov r0, s1224; CHECK-NEXT: vmov.f32 s12, s625; CHECK-NEXT: vmov.f32 s6, s726; CHECK-NEXT: asrs r2, r0, #3127; CHECK-NEXT: adds r0, r0, r128; CHECK-NEXT: adc.w r1, r2, r329; CHECK-NEXT: vmov r2, s1230; CHECK-NEXT: asrl r0, r1, r231; CHECK-NEXT: vmov r1, s232; CHECK-NEXT: vmov.f32 s2, s133; CHECK-NEXT: adds r2, r1, r434; CHECK-NEXT: asr.w r3, r1, #3135; CHECK-NEXT: adc.w r1, r3, r536; CHECK-NEXT: vmov r3, s637; CHECK-NEXT: asrl r2, r1, r338; CHECK-NEXT: vmov r4, r5, d439; CHECK-NEXT: vmov r1, s240; CHECK-NEXT: vmov.f32 s2, s541; CHECK-NEXT: adds.w r6, r1, lr42; CHECK-NEXT: asr.w r3, r1, #3143; CHECK-NEXT: adc.w r1, r3, r1244; CHECK-NEXT: vmov r3, s245; CHECK-NEXT: asrl r6, r1, r346; CHECK-NEXT: vmov r1, s047; CHECK-NEXT: adds r4, r4, r148; CHECK-NEXT: asr.w r3, r1, #3149; CHECK-NEXT: adc.w r1, r3, r550; CHECK-NEXT: vmov r3, s451; CHECK-NEXT: asrl r4, r1, r352; CHECK-NEXT: vmov q0[2], q0[0], r4, r053; CHECK-NEXT: vmov q0[3], q0[1], r6, r254; CHECK-NEXT: pop {r4, r5, r6, pc}55entry:56 %a = load <4 x i32>, ptr %A, align 457 %b = load <4 x i32>, ptr %B, align 458 %c = load <4 x i32>, ptr %C, align 459 %sa = sext <4 x i32> %a to <4 x i64>60 %sb = zext <4 x i32> %b to <4 x i64>61 %sc = zext <4 x i32> %c to <4 x i64>62 %add = add <4 x i64> %sa, %sb63 %sh = ashr <4 x i64> %add, %sc64 %t = trunc <4 x i64> %sh to <4 x i32>65 ret <4 x i32> %t66}67 68define arm_aapcs_vfpcc <8 x i16> @loads_i16(ptr %A, ptr %B, ptr %C) {69; CHECK-LABEL: loads_i16:70; CHECK: @ %bb.0: @ %entry71; CHECK-NEXT: vldrw.u32 q0, [r1]72; CHECK-NEXT: vldrw.u32 q2, [r0]73; CHECK-NEXT: vmovlb.s16 q1, q074; CHECK-NEXT: vmovlb.s16 q3, q275; CHECK-NEXT: vmovlt.s16 q0, q076; CHECK-NEXT: vmovlt.s16 q2, q277; CHECK-NEXT: vadd.i32 q0, q2, q078; CHECK-NEXT: vldrw.u32 q2, [r2]79; CHECK-NEXT: vadd.i32 q1, q3, q180; CHECK-NEXT: vmovlt.u16 q3, q281; CHECK-NEXT: vneg.s32 q3, q382; CHECK-NEXT: vshl.s32 q3, q0, q383; CHECK-NEXT: vmovlb.u16 q0, q284; CHECK-NEXT: vneg.s32 q0, q085; CHECK-NEXT: vshl.s32 q0, q1, q086; CHECK-NEXT: vmovnt.i32 q0, q387; CHECK-NEXT: bx lr88entry:89 %a = load <8 x i16>, ptr %A, align 490 %b = load <8 x i16>, ptr %B, align 491 %c = load <8 x i16>, ptr %C, align 492 %sa = sext <8 x i16> %a to <8 x i32>93 %sb = sext <8 x i16> %b to <8 x i32>94 %sc = zext <8 x i16> %c to <8 x i32>95 %add = add <8 x i32> %sa, %sb96 %sh = ashr <8 x i32> %add, %sc97 %t = trunc <8 x i32> %sh to <8 x i16>98 ret <8 x i16> %t99}100 101define arm_aapcs_vfpcc <16 x i8> @loads_i8(ptr %A, ptr %B, ptr %C) {102; CHECK-LABEL: loads_i8:103; CHECK: @ %bb.0: @ %entry104; CHECK-NEXT: vldrw.u32 q0, [r1]105; CHECK-NEXT: vldrw.u32 q2, [r0]106; CHECK-NEXT: vmovlb.s8 q1, q0107; CHECK-NEXT: vmovlb.s8 q3, q2108; CHECK-NEXT: vmovlt.s8 q0, q0109; CHECK-NEXT: vmovlt.s8 q2, q2110; CHECK-NEXT: vadd.i16 q0, q2, q0111; CHECK-NEXT: vldrw.u32 q2, [r2]112; CHECK-NEXT: vadd.i16 q1, q3, q1113; CHECK-NEXT: vmovlt.u8 q3, q2114; CHECK-NEXT: vneg.s16 q3, q3115; CHECK-NEXT: vshl.s16 q3, q0, q3116; CHECK-NEXT: vmovlb.u8 q0, q2117; CHECK-NEXT: vneg.s16 q0, q0118; CHECK-NEXT: vshl.s16 q0, q1, q0119; CHECK-NEXT: vmovnt.i16 q0, q3120; CHECK-NEXT: bx lr121entry:122 %a = load <16 x i8>, ptr %A, align 4123 %b = load <16 x i8>, ptr %B, align 4124 %c = load <16 x i8>, ptr %C, align 4125 %sa = sext <16 x i8> %a to <16 x i16>126 %sb = sext <16 x i8> %b to <16 x i16>127 %sc = zext <16 x i8> %c to <16 x i16>128 %add = add <16 x i16> %sa, %sb129 %sh = ashr <16 x i16> %add, %sc130 %t = trunc <16 x i16> %sh to <16 x i8>131 ret <16 x i8> %t132}133 134define arm_aapcs_vfpcc void @load_store_i32(ptr %A, ptr %B, ptr %C, ptr %D) {135; CHECK-LABEL: load_store_i32:136; CHECK: @ %bb.0: @ %entry137; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}138; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}139; CHECK-NEXT: .vsave {d8, d9}140; CHECK-NEXT: vpush {d8, d9}141; CHECK-NEXT: vldrw.u32 q1, [r1]142; CHECK-NEXT: vmov.i64 q0, #0xffffffff143; CHECK-NEXT: vmov.f32 s8, s6144; CHECK-NEXT: vmov.f32 s10, s7145; CHECK-NEXT: vmov.f32 s6, s5146; CHECK-NEXT: vand q4, q2, q0147; CHECK-NEXT: vand q2, q1, q0148; CHECK-NEXT: vldrw.u32 q0, [r0]149; CHECK-NEXT: vmov r4, r5, d9150; CHECK-NEXT: vldrw.u32 q1, [r2]151; CHECK-NEXT: vmov.f32 s12, s2152; CHECK-NEXT: vmov.f32 s2, s3153; CHECK-NEXT: vmov lr, r12, d8154; CHECK-NEXT: vmov.f32 s16, s6155; CHECK-NEXT: vmov.f32 s6, s7156; CHECK-NEXT: vmov r6, r1, d5157; CHECK-NEXT: vmov.f32 s10, s1158; CHECK-NEXT: vmov r0, s2159; CHECK-NEXT: vmov.f32 s2, s5160; CHECK-NEXT: adds.w r8, r0, r4161; CHECK-NEXT: asr.w r2, r0, #31162; CHECK-NEXT: adcs r5, r2163; CHECK-NEXT: vmov r2, s6164; CHECK-NEXT: asrl r8, r5, r2165; CHECK-NEXT: vmov r2, s10166; CHECK-NEXT: vmov r5, r7, d4167; CHECK-NEXT: asrs r4, r2, #31168; CHECK-NEXT: adds r2, r2, r6169; CHECK-NEXT: adcs r1, r4170; CHECK-NEXT: vmov r4, s2171; CHECK-NEXT: asrl r2, r1, r4172; CHECK-NEXT: vmov r1, s12173; CHECK-NEXT: adds.w r6, r1, lr174; CHECK-NEXT: asr.w r4, r1, #31175; CHECK-NEXT: adc.w r1, r4, r12176; CHECK-NEXT: vmov r4, s16177; CHECK-NEXT: asrl r6, r1, r4178; CHECK-NEXT: vmov r1, s0179; CHECK-NEXT: adds r0, r1, r5180; CHECK-NEXT: asr.w r4, r1, #31181; CHECK-NEXT: adc.w r1, r4, r7182; CHECK-NEXT: vmov r7, s4183; CHECK-NEXT: asrl r0, r1, r7184; CHECK-NEXT: vmov q0[2], q0[0], r0, r6185; CHECK-NEXT: vmov q0[3], q0[1], r2, r8186; CHECK-NEXT: vstrw.32 q0, [r3]187; CHECK-NEXT: vpop {d8, d9}188; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}189entry:190 %a = load <4 x i32>, ptr %A, align 4191 %b = load <4 x i32>, ptr %B, align 4192 %c = load <4 x i32>, ptr %C, align 4193 %sa = sext <4 x i32> %a to <4 x i64>194 %sb = zext <4 x i32> %b to <4 x i64>195 %sc = zext <4 x i32> %c to <4 x i64>196 %add = add <4 x i64> %sa, %sb197 %sh = ashr <4 x i64> %add, %sc198 %t = trunc <4 x i64> %sh to <4 x i32>199 store <4 x i32> %t, ptr %D, align 4200 ret void201}202 203define arm_aapcs_vfpcc void @load_store_i16(ptr %A, ptr %B, ptr %C, ptr %D) {204; CHECK-LABEL: load_store_i16:205; CHECK: @ %bb.0: @ %entry206; CHECK-NEXT: vldrh.s32 q0, [r1, #8]207; CHECK-NEXT: vldrh.s32 q1, [r0, #8]208; CHECK-NEXT: vldrh.s32 q2, [r0]209; CHECK-NEXT: vadd.i32 q0, q1, q0210; CHECK-NEXT: vldrh.u32 q1, [r2, #8]211; CHECK-NEXT: vneg.s32 q1, q1212; CHECK-NEXT: vshl.s32 q0, q0, q1213; CHECK-NEXT: vldrh.s32 q1, [r1]214; CHECK-NEXT: vadd.i32 q1, q2, q1215; CHECK-NEXT: vldrh.u32 q2, [r2]216; CHECK-NEXT: vstrh.32 q0, [r3, #8]217; CHECK-NEXT: vneg.s32 q2, q2218; CHECK-NEXT: vshl.s32 q1, q1, q2219; CHECK-NEXT: vstrh.32 q1, [r3]220; CHECK-NEXT: bx lr221entry:222 %a = load <8 x i16>, ptr %A, align 4223 %b = load <8 x i16>, ptr %B, align 4224 %c = load <8 x i16>, ptr %C, align 4225 %sa = sext <8 x i16> %a to <8 x i32>226 %sb = sext <8 x i16> %b to <8 x i32>227 %sc = zext <8 x i16> %c to <8 x i32>228 %add = add <8 x i32> %sa, %sb229 %sh = ashr <8 x i32> %add, %sc230 %t = trunc <8 x i32> %sh to <8 x i16>231 store <8 x i16> %t, ptr %D, align 4232 ret void233}234 235define arm_aapcs_vfpcc void @load_store_i8(ptr %A, ptr %B, ptr %C, ptr %D) {236; CHECK-LABEL: load_store_i8:237; CHECK: @ %bb.0: @ %entry238; CHECK-NEXT: vldrb.s16 q0, [r1, #8]239; CHECK-NEXT: vldrb.s16 q1, [r0, #8]240; CHECK-NEXT: vldrb.s16 q2, [r0]241; CHECK-NEXT: vadd.i16 q0, q1, q0242; CHECK-NEXT: vldrb.u16 q1, [r2, #8]243; CHECK-NEXT: vneg.s16 q1, q1244; CHECK-NEXT: vshl.s16 q0, q0, q1245; CHECK-NEXT: vldrb.s16 q1, [r1]246; CHECK-NEXT: vadd.i16 q1, q2, q1247; CHECK-NEXT: vldrb.u16 q2, [r2]248; CHECK-NEXT: vstrb.16 q0, [r3, #8]249; CHECK-NEXT: vneg.s16 q2, q2250; CHECK-NEXT: vshl.s16 q1, q1, q2251; CHECK-NEXT: vstrb.16 q1, [r3]252; CHECK-NEXT: bx lr253entry:254 %a = load <16 x i8>, ptr %A, align 4255 %b = load <16 x i8>, ptr %B, align 4256 %c = load <16 x i8>, ptr %C, align 4257 %sa = sext <16 x i8> %a to <16 x i16>258 %sb = sext <16 x i8> %b to <16 x i16>259 %sc = zext <16 x i8> %c to <16 x i16>260 %add = add <16 x i16> %sa, %sb261 %sh = ashr <16 x i16> %add, %sc262 %t = trunc <16 x i16> %sh to <16 x i8>263 store <16 x i8> %t, ptr %D, align 4264 ret void265}266 267 268define arm_aapcs_vfpcc void @load_one_store_i32(ptr %A, ptr %D) {269; CHECK-LABEL: load_one_store_i32:270; CHECK: @ %bb.0: @ %entry271; CHECK-NEXT: .save {r4, r5, r6, lr}272; CHECK-NEXT: push {r4, r5, r6, lr}273; CHECK-NEXT: vldrw.u32 q0, [r0]274; CHECK-NEXT: vmov.f32 s4, s2275; CHECK-NEXT: vmov.f32 s2, s3276; CHECK-NEXT: vmov r2, s2277; CHECK-NEXT: vmov.f32 s2, s1278; CHECK-NEXT: adds.w r12, r2, r2279; CHECK-NEXT: asr.w r3, r2, #31280; CHECK-NEXT: adc.w r3, r3, r2, asr #31281; CHECK-NEXT: asrl r12, r3, r2282; CHECK-NEXT: vmov r3, s2283; CHECK-NEXT: adds r2, r3, r3284; CHECK-NEXT: asr.w r0, r3, #31285; CHECK-NEXT: adc.w r5, r0, r3, asr #31286; CHECK-NEXT: vmov r0, s4287; CHECK-NEXT: asrl r2, r5, r3288; CHECK-NEXT: adds r4, r0, r0289; CHECK-NEXT: asr.w r3, r0, #31290; CHECK-NEXT: adc.w r3, r3, r0, asr #31291; CHECK-NEXT: asrl r4, r3, r0292; CHECK-NEXT: vmov r0, s0293; CHECK-NEXT: adds r6, r0, r0294; CHECK-NEXT: asr.w r3, r0, #31295; CHECK-NEXT: adc.w r3, r3, r0, asr #31296; CHECK-NEXT: asrl r6, r3, r0297; CHECK-NEXT: vmov q0[2], q0[0], r6, r4298; CHECK-NEXT: vmov q0[3], q0[1], r2, r12299; CHECK-NEXT: vstrw.32 q0, [r1]300; CHECK-NEXT: pop {r4, r5, r6, pc}301entry:302 %a = load <4 x i32>, ptr %A, align 4303 %sa = sext <4 x i32> %a to <4 x i64>304 %add = add <4 x i64> %sa, %sa305 %sh = ashr <4 x i64> %add, %sa306 %t = trunc <4 x i64> %sh to <4 x i32>307 store <4 x i32> %t, ptr %D, align 4308 ret void309}310 311define arm_aapcs_vfpcc void @load_one_store_i16(ptr %A, ptr %D) {312; CHECK-LABEL: load_one_store_i16:313; CHECK: @ %bb.0: @ %entry314; CHECK-NEXT: vldrh.s32 q0, [r0, #8]315; CHECK-NEXT: vneg.s32 q1, q0316; CHECK-NEXT: vadd.i32 q0, q0, q0317; CHECK-NEXT: vshl.s32 q0, q0, q1318; CHECK-NEXT: vldrh.s32 q1, [r0]319; CHECK-NEXT: vstrh.32 q0, [r1, #8]320; CHECK-NEXT: vneg.s32 q2, q1321; CHECK-NEXT: vadd.i32 q1, q1, q1322; CHECK-NEXT: vshl.s32 q1, q1, q2323; CHECK-NEXT: vstrh.32 q1, [r1]324; CHECK-NEXT: bx lr325entry:326 %a = load <8 x i16>, ptr %A, align 4327 %sa = sext <8 x i16> %a to <8 x i32>328 %add = add <8 x i32> %sa, %sa329 %sh = ashr <8 x i32> %add, %sa330 %t = trunc <8 x i32> %sh to <8 x i16>331 store <8 x i16> %t, ptr %D, align 4332 ret void333}334 335define arm_aapcs_vfpcc void @load_one_store_i8(ptr %A, ptr %D) {336; CHECK-LABEL: load_one_store_i8:337; CHECK: @ %bb.0: @ %entry338; CHECK-NEXT: vldrb.s16 q0, [r0, #8]339; CHECK-NEXT: vneg.s16 q1, q0340; CHECK-NEXT: vadd.i16 q0, q0, q0341; CHECK-NEXT: vshl.s16 q0, q0, q1342; CHECK-NEXT: vldrb.s16 q1, [r0]343; CHECK-NEXT: vstrb.16 q0, [r1, #8]344; CHECK-NEXT: vneg.s16 q2, q1345; CHECK-NEXT: vadd.i16 q1, q1, q1346; CHECK-NEXT: vshl.s16 q1, q1, q2347; CHECK-NEXT: vstrb.16 q1, [r1]348; CHECK-NEXT: bx lr349entry:350 %a = load <16 x i8>, ptr %A, align 4351 %sa = sext <16 x i8> %a to <16 x i16>352 %add = add <16 x i16> %sa, %sa353 %sh = ashr <16 x i16> %add, %sa354 %t = trunc <16 x i16> %sh to <16 x i8>355 store <16 x i8> %t, ptr %D, align 4356 ret void357}358 359 360define arm_aapcs_vfpcc void @mul_i32(ptr %A, ptr %B, i64 %C, ptr %D) {361; CHECK-LABEL: mul_i32:362; CHECK: @ %bb.0: @ %entry363; CHECK-NEXT: .save {r4, r5, r6, r7, lr}364; CHECK-NEXT: push {r4, r5, r6, r7, lr}365; CHECK-NEXT: vldrw.u32 q1, [r0]366; CHECK-NEXT: vldrw.u32 q0, [r1]367; CHECK-NEXT: ldr.w lr, [sp, #20]368; CHECK-NEXT: vmov.f32 s10, s1369; CHECK-NEXT: vmov.f32 s14, s5370; CHECK-NEXT: vmov r5, s4371; CHECK-NEXT: vmov.f32 s4, s6372; CHECK-NEXT: vmov.f32 s6, s7373; CHECK-NEXT: vmov r0, s10374; CHECK-NEXT: vmov r1, s14375; CHECK-NEXT: smull r12, r3, r1, r0376; CHECK-NEXT: vmov r0, s0377; CHECK-NEXT: vmov.f32 s0, s2378; CHECK-NEXT: vmov.f32 s2, s3379; CHECK-NEXT: vmullb.s32 q2, q1, q0380; CHECK-NEXT: asrl r12, r3, r2381; CHECK-NEXT: vmov r6, r1, d4382; CHECK-NEXT: vmov r4, r7, d5383; CHECK-NEXT: asrl r6, r1, r2384; CHECK-NEXT: asrl r4, r7, r2385; CHECK-NEXT: smull r0, r5, r5, r0386; CHECK-NEXT: asrl r0, r5, r2387; CHECK-NEXT: vmov q0[2], q0[0], r0, r6388; CHECK-NEXT: vmov q0[3], q0[1], r12, r4389; CHECK-NEXT: vstrw.32 q0, [lr]390; CHECK-NEXT: pop {r4, r5, r6, r7, pc}391entry:392 %a = load <4 x i32>, ptr %A, align 4393 %b = load <4 x i32>, ptr %B, align 4394 %i = insertelement <4 x i64> undef, i64 %C, i32 0395 %c = shufflevector <4 x i64> %i, <4 x i64> undef, <4 x i32> zeroinitializer396 %sa = sext <4 x i32> %a to <4 x i64>397 %sb = sext <4 x i32> %b to <4 x i64>398 %add = mul <4 x i64> %sa, %sb399 %sh = ashr <4 x i64> %add, %c400 %t = trunc <4 x i64> %sh to <4 x i32>401 store <4 x i32> %t, ptr %D, align 4402 ret void403}404 405define arm_aapcs_vfpcc void @mul_i16(ptr %A, ptr %B, i32 %C, ptr %D) {406; CHECK-LABEL: mul_i16:407; CHECK: @ %bb.0: @ %entry408; CHECK-NEXT: vldrw.u32 q0, [r1]409; CHECK-NEXT: vldrw.u32 q1, [r0]410; CHECK-NEXT: rsbs r2, r2, #0411; CHECK-NEXT: vmullt.s16 q2, q1, q0412; CHECK-NEXT: vmullb.s16 q0, q1, q0413; CHECK-NEXT: vshl.s32 q2, r2414; CHECK-NEXT: vshl.s32 q0, r2415; CHECK-NEXT: vmovnt.i32 q0, q2416; CHECK-NEXT: vstrw.32 q0, [r3]417; CHECK-NEXT: bx lr418entry:419 %a = load <8 x i16>, ptr %A, align 4420 %b = load <8 x i16>, ptr %B, align 4421 %i = insertelement <8 x i32> undef, i32 %C, i32 0422 %c = shufflevector <8 x i32> %i, <8 x i32> undef, <8 x i32> zeroinitializer423 %sa = sext <8 x i16> %a to <8 x i32>424 %sb = sext <8 x i16> %b to <8 x i32>425 %add = mul <8 x i32> %sa, %sb426 %sh = ashr <8 x i32> %add, %c427 %t = trunc <8 x i32> %sh to <8 x i16>428 store <8 x i16> %t, ptr %D, align 4429 ret void430}431 432define arm_aapcs_vfpcc void @mul_i8(ptr %A, ptr %B, i16 %C, ptr %D) {433; CHECK-LABEL: mul_i8:434; CHECK: @ %bb.0: @ %entry435; CHECK-NEXT: vldrw.u32 q0, [r1]436; CHECK-NEXT: vldrw.u32 q1, [r0]437; CHECK-NEXT: rsbs r2, r2, #0438; CHECK-NEXT: vmullt.s8 q2, q1, q0439; CHECK-NEXT: vmullb.s8 q0, q1, q0440; CHECK-NEXT: vshl.s16 q2, r2441; CHECK-NEXT: vshl.s16 q0, r2442; CHECK-NEXT: vmovnt.i16 q0, q2443; CHECK-NEXT: vstrw.32 q0, [r3]444; CHECK-NEXT: bx lr445entry:446 %a = load <16 x i8>, ptr %A, align 4447 %b = load <16 x i8>, ptr %B, align 4448 %i = insertelement <16 x i16> undef, i16 %C, i32 0449 %c = shufflevector <16 x i16> %i, <16 x i16> undef, <16 x i32> zeroinitializer450 %sa = sext <16 x i8> %a to <16 x i16>451 %sb = sext <16 x i8> %b to <16 x i16>452 %add = mul <16 x i16> %sa, %sb453 %sh = ashr <16 x i16> %add, %c454 %t = trunc <16 x i16> %sh to <16 x i8>455 store <16 x i8> %t, ptr %D, align 4456 ret void457}458