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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @sext_trunc_i32(<4 x i32> %a) {5; CHECK-LABEL: sext_trunc_i32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: bx lr8entry:9 %sa = sext <4 x i32> %a to <4 x i64>10 %t = trunc <4 x i64> %sa to <4 x i32>11 ret <4 x i32> %t12}13 14define arm_aapcs_vfpcc <8 x i16> @sext_trunc_i16(<8 x i16> %a) {15; CHECK-LABEL: sext_trunc_i16:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: bx lr18entry:19 %sa = sext <8 x i16> %a to <8 x i32>20 %t = trunc <8 x i32> %sa to <8 x i16>21 ret <8 x i16> %t22}23 24define arm_aapcs_vfpcc <16 x i8> @sext_trunc_i8(<16 x i8> %a) {25; CHECK-LABEL: sext_trunc_i8:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: bx lr28entry:29 %sa = sext <16 x i8> %a to <16 x i16>30 %t = trunc <16 x i16> %sa to <16 x i8>31 ret <16 x i8> %t32}33 34define arm_aapcs_vfpcc <4 x i32> @zext_trunc_i32(<4 x i32> %a) {35; CHECK-LABEL: zext_trunc_i32:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: bx lr38entry:39 %sa = zext <4 x i32> %a to <4 x i64>40 %t = trunc <4 x i64> %sa to <4 x i32>41 ret <4 x i32> %t42}43 44define arm_aapcs_vfpcc <8 x i16> @zext_trunc_i16(<8 x i16> %a) {45; CHECK-LABEL: zext_trunc_i16:46; CHECK: @ %bb.0: @ %entry47; CHECK-NEXT: bx lr48entry:49 %sa = zext <8 x i16> %a to <8 x i32>50 %t = trunc <8 x i32> %sa to <8 x i16>51 ret <8 x i16> %t52}53 54define arm_aapcs_vfpcc <16 x i8> @zext_trunc_i8(<16 x i8> %a) {55; CHECK-LABEL: zext_trunc_i8:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: bx lr58entry:59 %sa = zext <16 x i8> %a to <16 x i16>60 %t = trunc <16 x i16> %sa to <16 x i8>61 ret <16 x i8> %t62}63 64define arm_aapcs_vfpcc <4 x i32> @ext_add_trunc_i32(<4 x i32> %a, <4 x i32> %b) {65; CHECK-LABEL: ext_add_trunc_i32:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vmov.f32 s8, s668; CHECK-NEXT: vmov.f32 s6, s769; CHECK-NEXT: vmov r0, s870; CHECK-NEXT: vmov.f32 s8, s271; CHECK-NEXT: vmov.f32 s2, s372; CHECK-NEXT: vmov r1, s873; CHECK-NEXT: vmov r2, s274; CHECK-NEXT: vmov.f32 s2, s575; CHECK-NEXT: add.w r12, r1, r076; CHECK-NEXT: vmov r1, s677; CHECK-NEXT: vmov r0, s078; CHECK-NEXT: add r1, r279; CHECK-NEXT: vmov r2, s280; CHECK-NEXT: vmov.f32 s2, s181; CHECK-NEXT: vmov r3, s282; CHECK-NEXT: add r2, r383; CHECK-NEXT: vmov r3, s484; CHECK-NEXT: add r0, r385; CHECK-NEXT: vmov q0[2], q0[0], r0, r1286; CHECK-NEXT: vmov q0[3], q0[1], r2, r187; CHECK-NEXT: bx lr88entry:89 %sa = sext <4 x i32> %a to <4 x i64>90 %sb = zext <4 x i32> %b to <4 x i64>91 %add = add <4 x i64> %sa, %sb92 %t = trunc <4 x i64> %add to <4 x i32>93 ret <4 x i32> %t94}95 96define arm_aapcs_vfpcc <8 x i16> @ext_add_trunc_v8i16(<8 x i16> %a, <8 x i16> %b) {97; CHECK-LABEL: ext_add_trunc_v8i16:98; CHECK: @ %bb.0: @ %entry99; CHECK-NEXT: vrev32.16 q3, q0100; CHECK-NEXT: vrev32.16 q2, q1101; CHECK-NEXT: vadd.i32 q2, q3, q2102; CHECK-NEXT: vadd.i32 q0, q0, q1103; CHECK-NEXT: vmovnt.i32 q0, q2104; CHECK-NEXT: bx lr105entry:106 %sa = sext <8 x i16> %a to <8 x i32>107 %sb = zext <8 x i16> %b to <8 x i32>108 %add = add <8 x i32> %sa, %sb109 %t = trunc <8 x i32> %add to <8 x i16>110 ret <8 x i16> %t111}112 113define arm_aapcs_vfpcc <16 x i8> @ext_add_trunc_v16i8(<16 x i8> %a, <16 x i8> %b) {114; CHECK-LABEL: ext_add_trunc_v16i8:115; CHECK: @ %bb.0: @ %entry116; CHECK-NEXT: vrev16.8 q3, q0117; CHECK-NEXT: vrev16.8 q2, q1118; CHECK-NEXT: vadd.i16 q2, q3, q2119; CHECK-NEXT: vadd.i16 q0, q0, q1120; CHECK-NEXT: vmovnt.i16 q0, q2121; CHECK-NEXT: bx lr122entry:123 %sa = sext <16 x i8> %a to <16 x i16>124 %sb = zext <16 x i8> %b to <16 x i16>125 %add = add <16 x i16> %sa, %sb126 %t = trunc <16 x i16> %add to <16 x i8>127 ret <16 x i8> %t128}129 130define arm_aapcs_vfpcc <16 x i16> @ext_add_trunc_v16i16(<16 x i16> %a, <16 x i16> %b) {131; CHECK-LABEL: ext_add_trunc_v16i16:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: .vsave {d8, d9, d10, d11}134; CHECK-NEXT: vpush {d8, d9, d10, d11}135; CHECK-NEXT: vrev32.16 q5, q0136; CHECK-NEXT: vrev32.16 q4, q2137; CHECK-NEXT: vadd.i32 q0, q0, q2138; CHECK-NEXT: vadd.i32 q4, q5, q4139; CHECK-NEXT: vmovnt.i32 q0, q4140; CHECK-NEXT: vrev32.16 q4, q1141; CHECK-NEXT: vrev32.16 q2, q3142; CHECK-NEXT: vadd.i32 q1, q1, q3143; CHECK-NEXT: vadd.i32 q2, q4, q2144; CHECK-NEXT: vmovnt.i32 q1, q2145; CHECK-NEXT: vpop {d8, d9, d10, d11}146; CHECK-NEXT: bx lr147entry:148 %sa = sext <16 x i16> %a to <16 x i32>149 %sb = zext <16 x i16> %b to <16 x i32>150 %add = add <16 x i32> %sa, %sb151 %t = trunc <16 x i32> %add to <16 x i16>152 ret <16 x i16> %t153}154 155define arm_aapcs_vfpcc <32 x i8> @ext_add_trunc_v32i8(<32 x i8> %a, <32 x i8> %b) {156; CHECK-LABEL: ext_add_trunc_v32i8:157; CHECK: @ %bb.0: @ %entry158; CHECK-NEXT: .vsave {d8, d9, d10, d11}159; CHECK-NEXT: vpush {d8, d9, d10, d11}160; CHECK-NEXT: vrev16.8 q5, q0161; CHECK-NEXT: vrev16.8 q4, q2162; CHECK-NEXT: vadd.i16 q0, q0, q2163; CHECK-NEXT: vadd.i16 q4, q5, q4164; CHECK-NEXT: vmovnt.i16 q0, q4165; CHECK-NEXT: vrev16.8 q4, q1166; CHECK-NEXT: vrev16.8 q2, q3167; CHECK-NEXT: vadd.i16 q1, q1, q3168; CHECK-NEXT: vadd.i16 q2, q4, q2169; CHECK-NEXT: vmovnt.i16 q1, q2170; CHECK-NEXT: vpop {d8, d9, d10, d11}171; CHECK-NEXT: bx lr172entry:173 %sa = sext <32 x i8> %a to <32 x i16>174 %sb = zext <32 x i8> %b to <32 x i16>175 %add = add <32 x i16> %sa, %sb176 %t = trunc <32 x i16> %add to <32 x i8>177 ret <32 x i8> %t178}179 180define arm_aapcs_vfpcc <4 x i32> @ext_add_ashr_trunc_i32(<4 x i32> %a, <4 x i32> %b) {181; CHECK-LABEL: ext_add_ashr_trunc_i32:182; CHECK: @ %bb.0: @ %entry183; CHECK-NEXT: .save {r4, r5, r6, r7, lr}184; CHECK-NEXT: push {r4, r5, r6, r7, lr}185; CHECK-NEXT: vmov.f32 s12, s6186; CHECK-NEXT: vmov.i64 q2, #0xffffffff187; CHECK-NEXT: vmov.f32 s6, s5188; CHECK-NEXT: vmov.f32 s14, s7189; CHECK-NEXT: vand q1, q1, q2190; CHECK-NEXT: vmov r3, r7, d2191; CHECK-NEXT: vand q3, q3, q2192; CHECK-NEXT: vmov.f32 s4, s2193; CHECK-NEXT: vmov r0, r1, d6194; CHECK-NEXT: vmov.f32 s2, s3195; CHECK-NEXT: vmov lr, r12, d7196; CHECK-NEXT: vmov r2, s4197; CHECK-NEXT: asrs r5, r2, #31198; CHECK-NEXT: adds r2, r2, r0199; CHECK-NEXT: vmov r0, s2200; CHECK-NEXT: adcs r1, r5201; CHECK-NEXT: vmov r5, s0202; CHECK-NEXT: asrl r2, r1, #1203; CHECK-NEXT: asrs r1, r0, #31204; CHECK-NEXT: adds.w r0, r0, lr205; CHECK-NEXT: adc.w r1, r1, r12206; CHECK-NEXT: asrs r4, r5, #31207; CHECK-NEXT: adds r6, r5, r3208; CHECK-NEXT: vmov r3, r5, d3209; CHECK-NEXT: vmov.f32 s6, s1210; CHECK-NEXT: asrl r0, r1, #1211; CHECK-NEXT: adcs r7, r4212; CHECK-NEXT: asrl r6, r7, #1213; CHECK-NEXT: vmov q0[2], q0[0], r6, r2214; CHECK-NEXT: vmov r1, s6215; CHECK-NEXT: adds r6, r1, r3216; CHECK-NEXT: asr.w r2, r1, #31217; CHECK-NEXT: adc.w r1, r2, r5218; CHECK-NEXT: asrl r6, r1, #1219; CHECK-NEXT: vmov q0[3], q0[1], r6, r0220; CHECK-NEXT: pop {r4, r5, r6, r7, pc}221entry:222 %sa = sext <4 x i32> %a to <4 x i64>223 %sb = zext <4 x i32> %b to <4 x i64>224 %add = add <4 x i64> %sa, %sb225 %sh = ashr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>226 %t = trunc <4 x i64> %sh to <4 x i32>227 ret <4 x i32> %t228}229 230define arm_aapcs_vfpcc <8 x i16> @ext_add_ashr_trunc_i16(<8 x i16> %a, <8 x i16> %b) {231; CHECK-LABEL: ext_add_ashr_trunc_i16:232; CHECK: @ %bb.0: @ %entry233; CHECK-NEXT: vmovlt.u16 q2, q1234; CHECK-NEXT: vmovlt.s16 q3, q0235; CHECK-NEXT: vmovlb.u16 q1, q1236; CHECK-NEXT: vmovlb.s16 q0, q0237; CHECK-NEXT: vhadd.s32 q2, q3, q2238; CHECK-NEXT: vhadd.s32 q0, q0, q1239; CHECK-NEXT: vmovnt.i32 q0, q2240; CHECK-NEXT: bx lr241entry:242 %sa = sext <8 x i16> %a to <8 x i32>243 %sb = zext <8 x i16> %b to <8 x i32>244 %add = add <8 x i32> %sa, %sb245 %sh = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>246 %t = trunc <8 x i32> %sh to <8 x i16>247 ret <8 x i16> %t248}249 250define arm_aapcs_vfpcc <16 x i8> @ext_add_ashr_trunc_i8(<16 x i8> %a, <16 x i8> %b) {251; CHECK-LABEL: ext_add_ashr_trunc_i8:252; CHECK: @ %bb.0: @ %entry253; CHECK-NEXT: vmovlt.u8 q2, q1254; CHECK-NEXT: vmovlt.s8 q3, q0255; CHECK-NEXT: vmovlb.u8 q1, q1256; CHECK-NEXT: vmovlb.s8 q0, q0257; CHECK-NEXT: vhadd.s16 q2, q3, q2258; CHECK-NEXT: vhadd.s16 q0, q0, q1259; CHECK-NEXT: vmovnt.i16 q0, q2260; CHECK-NEXT: bx lr261entry:262 %sa = sext <16 x i8> %a to <16 x i16>263 %sb = zext <16 x i8> %b to <16 x i16>264 %add = add <16 x i16> %sa, %sb265 %sh = ashr <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>266 %t = trunc <16 x i16> %sh to <16 x i8>267 ret <16 x i8> %t268}269 270define arm_aapcs_vfpcc <16 x i8> @ext_add_ashr_trunc_i8i32(<16 x i8> %a, <16 x i8> %b) {271; CHECK-LABEL: ext_add_ashr_trunc_i8i32:272; CHECK: @ %bb.0: @ %entry273; CHECK-NEXT: .pad #48274; CHECK-NEXT: sub sp, #48275; CHECK-NEXT: add r0, sp, #16276; CHECK-NEXT: mov r1, sp277; CHECK-NEXT: vstrw.32 q1, [r0]278; CHECK-NEXT: vstrw.32 q0, [r1]279; CHECK-NEXT: vldrb.u16 q0, [r0, #8]280; CHECK-NEXT: vldrb.s16 q1, [r1, #8]281; CHECK-NEXT: add r2, sp, #32282; CHECK-NEXT: vhadd.s16 q0, q1, q0283; CHECK-NEXT: vstrb.16 q0, [r2, #8]284; CHECK-NEXT: vldrb.u16 q0, [r0]285; CHECK-NEXT: vldrb.s16 q1, [r1]286; CHECK-NEXT: vhadd.s16 q0, q1, q0287; CHECK-NEXT: vstrb.16 q0, [r2]288; CHECK-NEXT: vldrw.u32 q0, [r2]289; CHECK-NEXT: add sp, #48290; CHECK-NEXT: bx lr291entry:292 %sa = sext <16 x i8> %a to <16 x i32>293 %sb = zext <16 x i8> %b to <16 x i32>294 %add = add <16 x i32> %sa, %sb295 %sh = ashr <16 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>296 %t = trunc <16 x i32> %sh to <16 x i8>297 ret <16 x i8> %t298}299 300define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b) {301; CHECK-LABEL: ext_ops_trunc_i32:302; CHECK: @ %bb.0: @ %entry303; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}304; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}305; CHECK-NEXT: vmov.f32 s8, s2306; CHECK-NEXT: vmov.f32 s2, s3307; CHECK-NEXT: vmov.f32 s10, s7308; CHECK-NEXT: vmov r10, s8309; CHECK-NEXT: vmov.f32 s8, s6310; CHECK-NEXT: vmov.f32 s6, s5311; CHECK-NEXT: vmov r2, s8312; CHECK-NEXT: asr.w r0, r10, #31313; CHECK-NEXT: adds.w r6, r10, r2314; CHECK-NEXT: eor.w r7, r10, r2315; CHECK-NEXT: adc r3, r0, #0316; CHECK-NEXT: asrl r6, r3, r2317; CHECK-NEXT: subs r0, r6, r2318; CHECK-NEXT: vmov r6, s2319; CHECK-NEXT: sbc lr, r3, #0320; CHECK-NEXT: vmov r3, s10321; CHECK-NEXT: vmov.f32 s2, s1322; CHECK-NEXT: umull r0, r8, r0, r2323; CHECK-NEXT: asrs r5, r6, #31324; CHECK-NEXT: adds r4, r6, r3325; CHECK-NEXT: adc r5, r5, #0326; CHECK-NEXT: eor.w r1, r6, r3327; CHECK-NEXT: asrl r4, r5, r3328; CHECK-NEXT: subs r4, r4, r3329; CHECK-NEXT: sbc r5, r5, #0330; CHECK-NEXT: orrs.w r7, r7, r10, asr #31331; CHECK-NEXT: umull r4, r12, r4, r3332; CHECK-NEXT: csetm r9, eq333; CHECK-NEXT: orrs.w r1, r1, r6, asr #31334; CHECK-NEXT: mov.w r7, #0335; CHECK-NEXT: csetm r1, eq336; CHECK-NEXT: bfi r7, r9, #0, #8337; CHECK-NEXT: mla r5, r5, r3, r12338; CHECK-NEXT: bfi r7, r1, #8, #8339; CHECK-NEXT: rsbs r1, r6, #0340; CHECK-NEXT: vmsr p0, r7341; CHECK-NEXT: mla r7, lr, r2, r8342; CHECK-NEXT: lsll r4, r5, r1343; CHECK-NEXT: rsb.w r1, r10, #0344; CHECK-NEXT: lsll r4, r5, r3345; CHECK-NEXT: lsll r0, r7, r1346; CHECK-NEXT: vmov r3, s2347; CHECK-NEXT: vmov r1, s6348; CHECK-NEXT: lsll r0, r7, r2349; CHECK-NEXT: vmov q3[2], q3[0], r0, r4350; CHECK-NEXT: mov.w r12, #0351; CHECK-NEXT: vpsel q2, q3, q2352; CHECK-NEXT: adds r2, r3, r1353; CHECK-NEXT: asr.w r0, r3, #31354; CHECK-NEXT: adc r5, r0, #0355; CHECK-NEXT: asrl r2, r5, r1356; CHECK-NEXT: subs r0, r2, r1357; CHECK-NEXT: vmov r2, s0358; CHECK-NEXT: sbc r8, r5, #0359; CHECK-NEXT: umull r4, lr, r0, r1360; CHECK-NEXT: vmov r0, s4361; CHECK-NEXT: asrs r5, r2, #31362; CHECK-NEXT: adds r6, r2, r0363; CHECK-NEXT: adc r7, r5, #0364; CHECK-NEXT: mla r5, r8, r1, lr365; CHECK-NEXT: asrl r6, r7, r0366; CHECK-NEXT: subs.w r8, r6, r0367; CHECK-NEXT: eor.w r6, r2, r0368; CHECK-NEXT: sbc lr, r7, #0369; CHECK-NEXT: eor.w r7, r3, r1370; CHECK-NEXT: orrs.w r6, r6, r2, asr #31371; CHECK-NEXT: orr.w r7, r7, r3, asr #31372; CHECK-NEXT: csetm r6, eq373; CHECK-NEXT: cmp r7, #0374; CHECK-NEXT: bfi r12, r6, #0, #8375; CHECK-NEXT: csetm r6, eq376; CHECK-NEXT: bfi r12, r6, #8, #8377; CHECK-NEXT: umull r6, r7, r8, r0378; CHECK-NEXT: rsb.w r8, r3, #0379; CHECK-NEXT: lsll r4, r5, r8380; CHECK-NEXT: vmsr p0, r12381; CHECK-NEXT: mla r3, lr, r0, r7382; CHECK-NEXT: lsll r4, r5, r1383; CHECK-NEXT: rsbs r1, r2, #0384; CHECK-NEXT: lsll r6, r3, r1385; CHECK-NEXT: lsll r6, r3, r0386; CHECK-NEXT: vmov q0[2], q0[0], r6, r4387; CHECK-NEXT: vpsel q0, q0, q1388; CHECK-NEXT: vmov.f32 s1, s2389; CHECK-NEXT: vmov.f32 s2, s8390; CHECK-NEXT: vmov.f32 s3, s10391; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}392entry:393 %sa = sext <4 x i32> %a to <4 x i64>394 %sb = zext <4 x i32> %b to <4 x i64>395 %add = add <4 x i64> %sa, %sb396 %ashr = ashr <4 x i64> %add, %sb397 %sub = sub <4 x i64> %ashr, %sb398 %mul = mul <4 x i64> %sub, %sb399 %lshr = lshr <4 x i64> %mul, %sa400 %shl = shl <4 x i64> %lshr, %sb401 %cmp = icmp eq <4 x i64> %sa, %sb402 %sel = select <4 x i1> %cmp, <4 x i64> %shl, <4 x i64> %sb403 %t = trunc <4 x i64> %sel to <4 x i32>404 ret <4 x i32> %t405}406 407define arm_aapcs_vfpcc <8 x i16> @ext_ops_trunc_i16(<8 x i16> %a, <8 x i16> %b) {408; CHECK-LABEL: ext_ops_trunc_i16:409; CHECK: @ %bb.0: @ %entry410; CHECK-NEXT: .vsave {d8, d9, d10, d11}411; CHECK-NEXT: vpush {d8, d9, d10, d11}412; CHECK-NEXT: vmovlt.u16 q2, q1413; CHECK-NEXT: vmovlt.s16 q3, q0414; CHECK-NEXT: vadd.i32 q4, q3, q2415; CHECK-NEXT: vneg.s32 q5, q2416; CHECK-NEXT: vshl.s32 q4, q4, q5417; CHECK-NEXT: vneg.s32 q5, q3418; CHECK-NEXT: vsub.i32 q4, q4, q2419; CHECK-NEXT: vmul.i32 q4, q4, q2420; CHECK-NEXT: vmovlb.u16 q1, q1421; CHECK-NEXT: vshl.u32 q4, q4, q5422; CHECK-NEXT: vmovlb.s16 q0, q0423; CHECK-NEXT: vpt.i32 eq, q3, q2424; CHECK-NEXT: vshlt.u32 q2, q4, q2425; CHECK-NEXT: vadd.i32 q3, q0, q1426; CHECK-NEXT: vneg.s32 q4, q1427; CHECK-NEXT: vshl.s32 q3, q3, q4428; CHECK-NEXT: vneg.s32 q4, q0429; CHECK-NEXT: vsub.i32 q3, q3, q1430; CHECK-NEXT: vmul.i32 q3, q3, q1431; CHECK-NEXT: vshl.u32 q3, q3, q4432; CHECK-NEXT: vpt.i32 eq, q0, q1433; CHECK-NEXT: vshlt.u32 q1, q3, q1434; CHECK-NEXT: vmovnt.i32 q1, q2435; CHECK-NEXT: vmov q0, q1436; CHECK-NEXT: vpop {d8, d9, d10, d11}437; CHECK-NEXT: bx lr438entry:439 %sa = sext <8 x i16> %a to <8 x i32>440 %sb = zext <8 x i16> %b to <8 x i32>441 %add = add <8 x i32> %sa, %sb442 %ashr = ashr <8 x i32> %add, %sb443 %sub = sub <8 x i32> %ashr, %sb444 %mul = mul <8 x i32> %sub, %sb445 %lshr = lshr <8 x i32> %mul, %sa446 %shl = shl <8 x i32> %lshr, %sb447 %cmp = icmp eq <8 x i32> %sa, %sb448 %sel = select <8 x i1> %cmp, <8 x i32> %shl, <8 x i32> %sb449 %t = trunc <8 x i32> %sel to <8 x i16>450 ret <8 x i16> %t451}452 453define arm_aapcs_vfpcc <16 x i8> @ext_ops_trunc_i8(<16 x i8> %a, <16 x i8> %b) {454; CHECK-LABEL: ext_ops_trunc_i8:455; CHECK: @ %bb.0: @ %entry456; CHECK-NEXT: .vsave {d8, d9, d10, d11}457; CHECK-NEXT: vpush {d8, d9, d10, d11}458; CHECK-NEXT: vmovlt.u8 q2, q1459; CHECK-NEXT: vmovlt.s8 q3, q0460; CHECK-NEXT: vadd.i16 q4, q3, q2461; CHECK-NEXT: vneg.s16 q5, q2462; CHECK-NEXT: vshl.s16 q4, q4, q5463; CHECK-NEXT: vneg.s16 q5, q3464; CHECK-NEXT: vsub.i16 q4, q4, q2465; CHECK-NEXT: vmul.i16 q4, q4, q2466; CHECK-NEXT: vmovlb.u8 q1, q1467; CHECK-NEXT: vshl.u16 q4, q4, q5468; CHECK-NEXT: vmovlb.s8 q0, q0469; CHECK-NEXT: vpt.i16 eq, q3, q2470; CHECK-NEXT: vshlt.u16 q2, q4, q2471; CHECK-NEXT: vadd.i16 q3, q0, q1472; CHECK-NEXT: vneg.s16 q4, q1473; CHECK-NEXT: vshl.s16 q3, q3, q4474; CHECK-NEXT: vneg.s16 q4, q0475; CHECK-NEXT: vsub.i16 q3, q3, q1476; CHECK-NEXT: vmul.i16 q3, q3, q1477; CHECK-NEXT: vshl.u16 q3, q3, q4478; CHECK-NEXT: vpt.i16 eq, q0, q1479; CHECK-NEXT: vshlt.u16 q1, q3, q1480; CHECK-NEXT: vmovnt.i16 q1, q2481; CHECK-NEXT: vmov q0, q1482; CHECK-NEXT: vpop {d8, d9, d10, d11}483; CHECK-NEXT: bx lr484entry:485 %sa = sext <16 x i8> %a to <16 x i16>486 %sb = zext <16 x i8> %b to <16 x i16>487 %add = add <16 x i16> %sa, %sb488 %ashr = ashr <16 x i16> %add, %sb489 %sub = sub <16 x i16> %ashr, %sb490 %mul = mul <16 x i16> %sub, %sb491 %lshr = lshr <16 x i16> %mul, %sa492 %shl = shl <16 x i16> %lshr, %sb493 %cmp = icmp eq <16 x i16> %sa, %sb494 %sel = select <16 x i1> %cmp, <16 x i16> %shl, <16 x i16> %sb495 %t = trunc <16 x i16> %sel to <16 x i8>496 ret <16 x i8> %t497}498 499define arm_aapcs_vfpcc <8 x i16> @ext_intrinsics_trunc_i16(<8 x i16> %a, <8 x i16> %b) {500; CHECK-LABEL: ext_intrinsics_trunc_i16:501; CHECK: @ %bb.0: @ %entry502; CHECK-NEXT: .vsave {d8, d9}503; CHECK-NEXT: vpush {d8, d9}504; CHECK-NEXT: vmovlb.u16 q2, q1505; CHECK-NEXT: vmovlb.s16 q3, q0506; CHECK-NEXT: vadd.i32 q4, q3, q2507; CHECK-NEXT: vmovlt.u16 q1, q1508; CHECK-NEXT: vqadd.u32 q4, q4, q2509; CHECK-NEXT: vmovlt.s16 q0, q0510; CHECK-NEXT: vqsub.s32 q4, q4, q3511; CHECK-NEXT: vqsub.u32 q4, q4, q2512; CHECK-NEXT: vabs.s32 q4, q4513; CHECK-NEXT: vmin.s32 q4, q4, q3514; CHECK-NEXT: vmax.s32 q4, q4, q2515; CHECK-NEXT: vmin.u32 q3, q4, q3516; CHECK-NEXT: vadd.i32 q4, q0, q1517; CHECK-NEXT: vqadd.u32 q4, q4, q1518; CHECK-NEXT: vqsub.s32 q4, q4, q0519; CHECK-NEXT: vqsub.u32 q4, q4, q1520; CHECK-NEXT: vabs.s32 q4, q4521; CHECK-NEXT: vmin.s32 q4, q4, q0522; CHECK-NEXT: vmax.s32 q4, q4, q1523; CHECK-NEXT: vmin.u32 q0, q4, q0524; CHECK-NEXT: vmax.u32 q1, q0, q1525; CHECK-NEXT: vmax.u32 q0, q3, q2526; CHECK-NEXT: vmovnt.i32 q0, q1527; CHECK-NEXT: vpop {d8, d9}528; CHECK-NEXT: bx lr529entry:530 %sa = sext <8 x i16> %a to <8 x i32>531 %sb = zext <8 x i16> %b to <8 x i32>532 %sadd = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> %sa, <8 x i32> %sb)533 %uadd = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %sadd, <8 x i32> %sb)534 %ssub = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %uadd, <8 x i32> %sa)535 %usub = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %ssub, <8 x i32> %sb)536 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %usub, i1 true)537 %smin = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %abs, <8 x i32> %sa)538 %smax = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %smin, <8 x i32> %sb)539 %umin = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %smax, <8 x i32> %sa)540 %umax = call <8 x i32> @llvm.umax.v8i32(<8 x i32> %umin, <8 x i32> %sb)541 %t = trunc <8 x i32> %umax to <8 x i16>542 ret <8 x i16> %t543}544 545define arm_aapcs_vfpcc <8 x half> @ext_fpintrinsics_trunc_half(<8 x half> %a, <8 x half> %b) {546; CHECK-LABEL: ext_fpintrinsics_trunc_half:547; CHECK: @ %bb.0: @ %entry548; CHECK-NEXT: .vsave {d8, d9, d10, d11}549; CHECK-NEXT: vpush {d8, d9, d10, d11}550; CHECK-NEXT: vcvtb.f32.f16 q2, q0551; CHECK-NEXT: vcvtb.f32.f16 q4, q1552; CHECK-NEXT: vrintm.f32 q3, q2553; CHECK-NEXT: vrintx.f32 q5, q4554; CHECK-NEXT: vabs.f32 q3, q3555; CHECK-NEXT: vrinta.f32 q4, q4556; CHECK-NEXT: vminnm.f32 q3, q3, q2557; CHECK-NEXT: vrintp.f32 q2, q2558; CHECK-NEXT: vmaxnm.f32 q3, q3, q5559; CHECK-NEXT: vcvtt.f32.f16 q0, q0560; CHECK-NEXT: vfma.f32 q2, q3, q4561; CHECK-NEXT: vrintm.f32 q3, q0562; CHECK-NEXT: vabs.f32 q3, q3563; CHECK-NEXT: vcvtt.f32.f16 q1, q1564; CHECK-NEXT: vminnm.f32 q3, q3, q0565; CHECK-NEXT: vrintx.f32 q4, q1566; CHECK-NEXT: vmaxnm.f32 q3, q3, q4567; CHECK-NEXT: vrinta.f32 q1, q1568; CHECK-NEXT: vrintp.f32 q0, q0569; CHECK-NEXT: vrintz.f32 q2, q2570; CHECK-NEXT: vfma.f32 q0, q3, q1571; CHECK-NEXT: vrintz.f32 q1, q0572; CHECK-NEXT: vcvtb.f16.f32 q0, q2573; CHECK-NEXT: vcvtt.f16.f32 q0, q1574; CHECK-NEXT: vpop {d8, d9, d10, d11}575; CHECK-NEXT: bx lr576entry:577 %sa = fpext <8 x half> %a to <8 x float>578 %sb = fpext <8 x half> %b to <8 x float>579 %floor = call <8 x float> @llvm.floor.v8f32(<8 x float> %sa)580 %rint = call <8 x float> @llvm.rint.v8f32(<8 x float> %sb)581 %ceil = call <8 x float> @llvm.ceil.v8f32(<8 x float> %sa)582 %round = call <8 x float> @llvm.round.v8f32(<8 x float> %sb)583 %abs = call <8 x float> @llvm.fabs.v8f32(<8 x float> %floor)584 %min = call <8 x float> @llvm.minnum.v8f32(<8 x float> %abs, <8 x float> %sa)585 %max = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %min, <8 x float> %rint)586 %fma = call <8 x float> @llvm.fma.v8f32(<8 x float> %max, <8 x float> %round, <8 x float> %ceil)587 %trunc = call <8 x float> @llvm.trunc.v8f32(<8 x float> %fma)588 %t = fptrunc <8 x float> %trunc to <8 x half>589 ret <8 x half> %t590}591 592declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)593declare <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32>, <8 x i32>)594declare <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32>, <8 x i32>)595declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>)596declare <8 x i32> @llvm.usub.sat.v8i32(<8 x i32>, <8 x i32>)597declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)598declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>)599declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)600declare <8 x i32> @llvm.umax.v8i32(<8 x i32>, <8 x i32>)601declare <8 x float> @llvm.fabs.v8f32(<8 x float>)602declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>)603declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>)604declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>)605declare <8 x float> @llvm.ceil.v8f32(<8 x float>)606declare <8 x float> @llvm.floor.v8f32(<8 x float>)607declare <8 x float> @llvm.rint.v8f32(<8 x float>)608declare <8 x float> @llvm.round.v8f32(<8 x float>)609declare <8 x float> @llvm.trunc.v8f32(<8 x float>)610