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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-LE3; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-BE4 5define arm_aapcs_vfpcc <4 x i32> @load_4xi32_a4(ptr %vp) {6; CHECK-LE-LABEL: load_4xi32_a4:7; CHECK-LE: @ %bb.0: @ %entry8; CHECK-LE-NEXT: vldrw.u32 q0, [r0]9; CHECK-LE-NEXT: vshr.u32 q0, q0, #110; CHECK-LE-NEXT: bx lr11;12; CHECK-BE-LABEL: load_4xi32_a4:13; CHECK-BE: @ %bb.0: @ %entry14; CHECK-BE-NEXT: vldrw.u32 q0, [r0]15; CHECK-BE-NEXT: vshr.u32 q1, q0, #116; CHECK-BE-NEXT: vrev64.32 q0, q117; CHECK-BE-NEXT: bx lr18entry:19 %0 = load <4 x i32>, ptr %vp, align 420 %1 = lshr <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>21 ret <4 x i32> %122}23 24define arm_aapcs_vfpcc <4 x i32> @load_4xi32_a2(ptr %vp) {25; CHECK-LE-LABEL: load_4xi32_a2:26; CHECK-LE: @ %bb.0: @ %entry27; CHECK-LE-NEXT: vldrh.u16 q0, [r0]28; CHECK-LE-NEXT: vshr.u32 q0, q0, #129; CHECK-LE-NEXT: bx lr30;31; CHECK-BE-LABEL: load_4xi32_a2:32; CHECK-BE: @ %bb.0: @ %entry33; CHECK-BE-NEXT: vldrb.u8 q0, [r0]34; CHECK-BE-NEXT: vrev32.8 q0, q035; CHECK-BE-NEXT: vshr.u32 q1, q0, #136; CHECK-BE-NEXT: vrev64.32 q0, q137; CHECK-BE-NEXT: bx lr38entry:39 %0 = load <4 x i32>, ptr %vp, align 240 %1 = lshr <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>41 ret <4 x i32> %142}43 44define arm_aapcs_vfpcc <4 x i32> @load_4xi32_a1(ptr %vp) {45; CHECK-LE-LABEL: load_4xi32_a1:46; CHECK-LE: @ %bb.0: @ %entry47; CHECK-LE-NEXT: vldrb.u8 q0, [r0]48; CHECK-LE-NEXT: vshr.u32 q0, q0, #149; CHECK-LE-NEXT: bx lr50;51; CHECK-BE-LABEL: load_4xi32_a1:52; CHECK-BE: @ %bb.0: @ %entry53; CHECK-BE-NEXT: vldrb.u8 q0, [r0]54; CHECK-BE-NEXT: vrev32.8 q0, q055; CHECK-BE-NEXT: vshr.u32 q1, q0, #156; CHECK-BE-NEXT: vrev64.32 q0, q157; CHECK-BE-NEXT: bx lr58entry:59 %0 = load <4 x i32>, ptr %vp, align 160 %1 = lshr <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>61 ret <4 x i32> %162}63 64define arm_aapcs_vfpcc void @store_4xi32_a4(ptr %vp, <4 x i32> %val) {65; CHECK-LE-LABEL: store_4xi32_a4:66; CHECK-LE: @ %bb.0: @ %entry67; CHECK-LE-NEXT: vshr.u32 q0, q0, #168; CHECK-LE-NEXT: vstrw.32 q0, [r0]69; CHECK-LE-NEXT: bx lr70;71; CHECK-BE-LABEL: store_4xi32_a4:72; CHECK-BE: @ %bb.0: @ %entry73; CHECK-BE-NEXT: vrev64.32 q1, q074; CHECK-BE-NEXT: vshr.u32 q0, q1, #175; CHECK-BE-NEXT: vstrw.32 q0, [r0]76; CHECK-BE-NEXT: bx lr77entry:78 %0 = lshr <4 x i32> %val, <i32 1, i32 1, i32 1, i32 1>79 store <4 x i32> %0, ptr %vp, align 480 ret void81}82 83define arm_aapcs_vfpcc void @store_4xi32_a2(ptr %vp, <4 x i32> %val) {84; CHECK-LE-LABEL: store_4xi32_a2:85; CHECK-LE: @ %bb.0: @ %entry86; CHECK-LE-NEXT: vshr.u32 q0, q0, #187; CHECK-LE-NEXT: vstrh.16 q0, [r0]88; CHECK-LE-NEXT: bx lr89;90; CHECK-BE-LABEL: store_4xi32_a2:91; CHECK-BE: @ %bb.0: @ %entry92; CHECK-BE-NEXT: vrev64.32 q1, q093; CHECK-BE-NEXT: vshr.u32 q0, q1, #194; CHECK-BE-NEXT: vrev32.8 q0, q095; CHECK-BE-NEXT: vstrb.8 q0, [r0]96; CHECK-BE-NEXT: bx lr97entry:98 %0 = lshr <4 x i32> %val, <i32 1, i32 1, i32 1, i32 1>99 store <4 x i32> %0, ptr %vp, align 2100 ret void101}102 103define arm_aapcs_vfpcc void @store_4xi32_a1(ptr %vp, <4 x i32> %val) {104; CHECK-LE-LABEL: store_4xi32_a1:105; CHECK-LE: @ %bb.0: @ %entry106; CHECK-LE-NEXT: vshr.u32 q0, q0, #1107; CHECK-LE-NEXT: vstrb.8 q0, [r0]108; CHECK-LE-NEXT: bx lr109;110; CHECK-BE-LABEL: store_4xi32_a1:111; CHECK-BE: @ %bb.0: @ %entry112; CHECK-BE-NEXT: vrev64.32 q1, q0113; CHECK-BE-NEXT: vshr.u32 q0, q1, #1114; CHECK-BE-NEXT: vrev32.8 q0, q0115; CHECK-BE-NEXT: vstrb.8 q0, [r0]116; CHECK-BE-NEXT: bx lr117entry:118 %0 = lshr <4 x i32> %val, <i32 1, i32 1, i32 1, i32 1>119 store <4 x i32> %0, ptr %vp, align 1120 ret void121}122 123define arm_aapcs_vfpcc <4 x i32> @load_4xi32_a4_offset_pos(ptr %ip) {124; CHECK-LE-LABEL: load_4xi32_a4_offset_pos:125; CHECK-LE: @ %bb.0: @ %entry126; CHECK-LE-NEXT: vldrw.u32 q0, [r0, #508]127; CHECK-LE-NEXT: bx lr128;129; CHECK-BE-LABEL: load_4xi32_a4_offset_pos:130; CHECK-BE: @ %bb.0: @ %entry131; CHECK-BE-NEXT: add.w r0, r0, #508132; CHECK-BE-NEXT: vldrb.u8 q1, [r0]133; CHECK-BE-NEXT: vrev64.8 q0, q1134; CHECK-BE-NEXT: bx lr135entry:136 %ipoffset = getelementptr inbounds i32, ptr %ip, i32 127137 %0 = load <4 x i32>, ptr %ipoffset, align 4138 ret <4 x i32> %0139}140 141define arm_aapcs_vfpcc <4 x i32> @load_4xi32_a4_offset_neg(ptr %ip) {142; CHECK-LE-LABEL: load_4xi32_a4_offset_neg:143; CHECK-LE: @ %bb.0: @ %entry144; CHECK-LE-NEXT: vldrw.u32 q0, [r0, #-508]145; CHECK-LE-NEXT: bx lr146;147; CHECK-BE-LABEL: load_4xi32_a4_offset_neg:148; CHECK-BE: @ %bb.0: @ %entry149; CHECK-BE-NEXT: sub.w r0, r0, #508150; CHECK-BE-NEXT: vldrb.u8 q1, [r0]151; CHECK-BE-NEXT: vrev64.8 q0, q1152; CHECK-BE-NEXT: bx lr153entry:154 %ipoffset = getelementptr inbounds i32, ptr %ip, i32 -127155 %0 = load <4 x i32>, ptr %ipoffset, align 4156 ret <4 x i32> %0157}158 159define arm_aapcs_vfpcc <4 x i32> @loadstore_4xi32_stack_off16() {160; CHECK-LE-LABEL: loadstore_4xi32_stack_off16:161; CHECK-LE: @ %bb.0: @ %entry162; CHECK-LE-NEXT: .pad #40163; CHECK-LE-NEXT: sub sp, #40164; CHECK-LE-NEXT: vmov.i32 q0, #0x1165; CHECK-LE-NEXT: mov r0, sp166; CHECK-LE-NEXT: vstrw.32 q0, [r0]167; CHECK-LE-NEXT: movs r0, #3168; CHECK-LE-NEXT: vstrw.32 q0, [sp, #16]169; CHECK-LE-NEXT: str r0, [sp, #16]170; CHECK-LE-NEXT: vldrw.u32 q0, [sp, #16]171; CHECK-LE-NEXT: add sp, #40172; CHECK-LE-NEXT: bx lr173;174; CHECK-BE-LABEL: loadstore_4xi32_stack_off16:175; CHECK-BE: @ %bb.0: @ %entry176; CHECK-BE-NEXT: .pad #40177; CHECK-BE-NEXT: sub sp, #40178; CHECK-BE-NEXT: vmov.i32 q0, #0x1179; CHECK-BE-NEXT: mov r0, sp180; CHECK-BE-NEXT: vstrw.32 q0, [r0]181; CHECK-BE-NEXT: movs r0, #3182; CHECK-BE-NEXT: vstrw.32 q0, [sp, #16]183; CHECK-BE-NEXT: str r0, [sp, #16]184; CHECK-BE-NEXT: vldrb.u8 q1, [sp, #16]185; CHECK-BE-NEXT: vrev64.8 q0, q1186; CHECK-BE-NEXT: add sp, #40187; CHECK-BE-NEXT: bx lr188entry:189 %c = alloca [1 x [5 x [2 x i32]]], align 4190 store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr %c, align 4191 %arrayidx5.2 = getelementptr inbounds [1 x [5 x [2 x i32]]], ptr %c, i32 0, i32 0, i32 2, i32 0192 store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr %arrayidx5.2, align 4193 store i32 3, ptr %arrayidx5.2, align 4194 %0 = load <4 x i32>, ptr %arrayidx5.2, align 4195 ret <4 x i32> %0196}197 198define arm_aapcs_vfpcc <8 x i16> @loadstore_8xi16_stack_off16() {199; CHECK-LE-LABEL: loadstore_8xi16_stack_off16:200; CHECK-LE: @ %bb.0: @ %entry201; CHECK-LE-NEXT: .pad #40202; CHECK-LE-NEXT: sub sp, #40203; CHECK-LE-NEXT: vmov.i16 q0, #0x1204; CHECK-LE-NEXT: mov r0, sp205; CHECK-LE-NEXT: vstrh.16 q0, [r0]206; CHECK-LE-NEXT: movs r0, #3207; CHECK-LE-NEXT: vstrh.16 q0, [sp, #16]208; CHECK-LE-NEXT: strh.w r0, [sp, #16]209; CHECK-LE-NEXT: vldrh.u16 q0, [sp, #16]210; CHECK-LE-NEXT: add sp, #40211; CHECK-LE-NEXT: bx lr212;213; CHECK-BE-LABEL: loadstore_8xi16_stack_off16:214; CHECK-BE: @ %bb.0: @ %entry215; CHECK-BE-NEXT: .pad #40216; CHECK-BE-NEXT: sub sp, #40217; CHECK-BE-NEXT: vmov.i16 q0, #0x1218; CHECK-BE-NEXT: mov r0, sp219; CHECK-BE-NEXT: vstrh.16 q0, [r0]220; CHECK-BE-NEXT: movs r0, #3221; CHECK-BE-NEXT: vstrh.16 q0, [sp, #16]222; CHECK-BE-NEXT: strh.w r0, [sp, #16]223; CHECK-BE-NEXT: vldrb.u8 q1, [sp, #16]224; CHECK-BE-NEXT: vrev64.8 q0, q1225; CHECK-BE-NEXT: add sp, #40226; CHECK-BE-NEXT: bx lr227entry:228 %c = alloca [1 x [10 x [2 x i16]]], align 2229 store <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, ptr %c, align 2230 %arrayidx5.2 = getelementptr inbounds [1 x [10 x [2 x i16]]], ptr %c, i32 0, i32 0, i32 4, i32 0231 store <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, ptr %arrayidx5.2, align 2232 store i16 3, ptr %arrayidx5.2, align 2233 %0 = load <8 x i16>, ptr %arrayidx5.2, align 2234 ret <8 x i16> %0235}236 237define arm_aapcs_vfpcc <16 x i8> @loadstore_16xi8_stack_off16() {238; CHECK-LE-LABEL: loadstore_16xi8_stack_off16:239; CHECK-LE: @ %bb.0: @ %entry240; CHECK-LE-NEXT: .pad #40241; CHECK-LE-NEXT: sub sp, #40242; CHECK-LE-NEXT: vmov.i8 q0, #0x1243; CHECK-LE-NEXT: mov r0, sp244; CHECK-LE-NEXT: vstrb.8 q0, [r0]245; CHECK-LE-NEXT: movs r0, #3246; CHECK-LE-NEXT: vstrb.8 q0, [sp, #16]247; CHECK-LE-NEXT: strb.w r0, [sp, #16]248; CHECK-LE-NEXT: vldrb.u8 q0, [sp, #16]249; CHECK-LE-NEXT: add sp, #40250; CHECK-LE-NEXT: bx lr251;252; CHECK-BE-LABEL: loadstore_16xi8_stack_off16:253; CHECK-BE: @ %bb.0: @ %entry254; CHECK-BE-NEXT: .pad #40255; CHECK-BE-NEXT: sub sp, #40256; CHECK-BE-NEXT: vmov.i8 q0, #0x1257; CHECK-BE-NEXT: mov r0, sp258; CHECK-BE-NEXT: vstrb.8 q0, [r0]259; CHECK-BE-NEXT: movs r0, #3260; CHECK-BE-NEXT: vstrb.8 q0, [sp, #16]261; CHECK-BE-NEXT: strb.w r0, [sp, #16]262; CHECK-BE-NEXT: vldrb.u8 q1, [sp, #16]263; CHECK-BE-NEXT: vrev64.8 q0, q1264; CHECK-BE-NEXT: add sp, #40265; CHECK-BE-NEXT: bx lr266entry:267 %c = alloca [1 x [20 x [2 x i8]]], align 1268 store <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, ptr %c, align 1269 %arrayidx5.2 = getelementptr inbounds [1 x [20 x [2 x i8]]], ptr %c, i32 0, i32 0, i32 8, i32 0270 store <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, ptr %arrayidx5.2, align 1271 store i8 3, ptr %arrayidx5.2, align 1272 %0 = load <16 x i8>, ptr %arrayidx5.2, align 1273 ret <16 x i8> %0274}275