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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-LE3; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-BE4 5define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align4_zero(ptr %dest, <4 x i32> %a) {6; CHECK-LE-LABEL: masked_v4i32_align4_zero:7; CHECK-LE: @ %bb.0: @ %entry8; CHECK-LE-NEXT: vpt.s32 gt, q0, zr9; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]10; CHECK-LE-NEXT: bx lr11;12; CHECK-BE-LABEL: masked_v4i32_align4_zero:13; CHECK-BE: @ %bb.0: @ %entry14; CHECK-BE-NEXT: vrev64.32 q1, q015; CHECK-BE-NEXT: vpt.s32 gt, q1, zr16; CHECK-BE-NEXT: vldrwt.u32 q1, [r0]17; CHECK-BE-NEXT: vrev64.32 q0, q118; CHECK-BE-NEXT: bx lr19entry:20 %c = icmp sgt <4 x i32> %a, zeroinitializer21 %l = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %dest, i32 4, <4 x i1> %c, <4 x i32> zeroinitializer)22 ret <4 x i32> %l23}24 25define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align4_undef(ptr %dest, <4 x i32> %a) {26; CHECK-LE-LABEL: masked_v4i32_align4_undef:27; CHECK-LE: @ %bb.0: @ %entry28; CHECK-LE-NEXT: vpt.s32 gt, q0, zr29; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]30; CHECK-LE-NEXT: bx lr31;32; CHECK-BE-LABEL: masked_v4i32_align4_undef:33; CHECK-BE: @ %bb.0: @ %entry34; CHECK-BE-NEXT: vrev64.32 q1, q035; CHECK-BE-NEXT: vpt.s32 gt, q1, zr36; CHECK-BE-NEXT: vldrwt.u32 q1, [r0]37; CHECK-BE-NEXT: vrev64.32 q0, q138; CHECK-BE-NEXT: bx lr39entry:40 %c = icmp sgt <4 x i32> %a, zeroinitializer41 %l = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %dest, i32 4, <4 x i1> %c, <4 x i32> undef)42 ret <4 x i32> %l43}44 45define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align1_undef(ptr %dest, <4 x i32> %a) {46; CHECK-LE-LABEL: masked_v4i32_align1_undef:47; CHECK-LE: @ %bb.0: @ %entry48; CHECK-LE-NEXT: .pad #449; CHECK-LE-NEXT: sub sp, #450; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr51; CHECK-LE-NEXT: @ implicit-def: $q052; CHECK-LE-NEXT: vmrs r2, p053; CHECK-LE-NEXT: and r1, r2, #154; CHECK-LE-NEXT: rsbs r3, r1, #055; CHECK-LE-NEXT: movs r1, #056; CHECK-LE-NEXT: bfi r1, r3, #0, #157; CHECK-LE-NEXT: ubfx r3, r2, #4, #158; CHECK-LE-NEXT: rsbs r3, r3, #059; CHECK-LE-NEXT: bfi r1, r3, #1, #160; CHECK-LE-NEXT: ubfx r3, r2, #8, #161; CHECK-LE-NEXT: ubfx r2, r2, #12, #162; CHECK-LE-NEXT: rsbs r3, r3, #063; CHECK-LE-NEXT: bfi r1, r3, #2, #164; CHECK-LE-NEXT: rsbs r2, r2, #065; CHECK-LE-NEXT: bfi r1, r2, #3, #166; CHECK-LE-NEXT: lsls r2, r1, #3167; CHECK-LE-NEXT: itt ne68; CHECK-LE-NEXT: ldrne r2, [r0]69; CHECK-LE-NEXT: vmovne.32 q0[0], r270; CHECK-LE-NEXT: lsls r2, r1, #3071; CHECK-LE-NEXT: itt mi72; CHECK-LE-NEXT: ldrmi r2, [r0, #4]73; CHECK-LE-NEXT: vmovmi.32 q0[1], r274; CHECK-LE-NEXT: lsls r2, r1, #2975; CHECK-LE-NEXT: itt mi76; CHECK-LE-NEXT: ldrmi r2, [r0, #8]77; CHECK-LE-NEXT: vmovmi.32 q0[2], r278; CHECK-LE-NEXT: lsls r1, r1, #2879; CHECK-LE-NEXT: itt mi80; CHECK-LE-NEXT: ldrmi r0, [r0, #12]81; CHECK-LE-NEXT: vmovmi.32 q0[3], r082; CHECK-LE-NEXT: add sp, #483; CHECK-LE-NEXT: bx lr84;85; CHECK-BE-LABEL: masked_v4i32_align1_undef:86; CHECK-BE: @ %bb.0: @ %entry87; CHECK-BE-NEXT: .pad #488; CHECK-BE-NEXT: sub sp, #489; CHECK-BE-NEXT: vrev64.32 q1, q090; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr91; CHECK-BE-NEXT: @ implicit-def: $q192; CHECK-BE-NEXT: vmrs r2, p093; CHECK-BE-NEXT: ubfx r1, r2, #12, #194; CHECK-BE-NEXT: rsbs r3, r1, #095; CHECK-BE-NEXT: movs r1, #096; CHECK-BE-NEXT: bfi r1, r3, #0, #197; CHECK-BE-NEXT: ubfx r3, r2, #8, #198; CHECK-BE-NEXT: rsbs r3, r3, #099; CHECK-BE-NEXT: bfi r1, r3, #1, #1100; CHECK-BE-NEXT: ubfx r3, r2, #4, #1101; CHECK-BE-NEXT: and r2, r2, #1102; CHECK-BE-NEXT: rsbs r3, r3, #0103; CHECK-BE-NEXT: bfi r1, r3, #2, #1104; CHECK-BE-NEXT: rsbs r2, r2, #0105; CHECK-BE-NEXT: bfi r1, r2, #3, #1106; CHECK-BE-NEXT: lsls r2, r1, #28107; CHECK-BE-NEXT: itt mi108; CHECK-BE-NEXT: ldrmi r2, [r0]109; CHECK-BE-NEXT: vmovmi.32 q1[0], r2110; CHECK-BE-NEXT: lsls r2, r1, #29111; CHECK-BE-NEXT: itt mi112; CHECK-BE-NEXT: ldrmi r2, [r0, #4]113; CHECK-BE-NEXT: vmovmi.32 q1[1], r2114; CHECK-BE-NEXT: lsls r2, r1, #30115; CHECK-BE-NEXT: itt mi116; CHECK-BE-NEXT: ldrmi r2, [r0, #8]117; CHECK-BE-NEXT: vmovmi.32 q1[2], r2118; CHECK-BE-NEXT: lsls r1, r1, #31119; CHECK-BE-NEXT: itt ne120; CHECK-BE-NEXT: ldrne r0, [r0, #12]121; CHECK-BE-NEXT: vmovne.32 q1[3], r0122; CHECK-BE-NEXT: vrev64.32 q0, q1123; CHECK-BE-NEXT: add sp, #4124; CHECK-BE-NEXT: bx lr125entry:126 %c = icmp sgt <4 x i32> %a, zeroinitializer127 %l = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x i32> undef)128 ret <4 x i32> %l129}130 131define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align4_other(ptr %dest, <4 x i32> %a) {132; CHECK-LE-LABEL: masked_v4i32_align4_other:133; CHECK-LE: @ %bb.0: @ %entry134; CHECK-LE-NEXT: vpt.s32 gt, q0, zr135; CHECK-LE-NEXT: vldrwt.u32 q1, [r0]136; CHECK-LE-NEXT: vpsel q0, q1, q0137; CHECK-LE-NEXT: bx lr138;139; CHECK-BE-LABEL: masked_v4i32_align4_other:140; CHECK-BE: @ %bb.0: @ %entry141; CHECK-BE-NEXT: vrev64.32 q1, q0142; CHECK-BE-NEXT: vpt.s32 gt, q1, zr143; CHECK-BE-NEXT: vldrwt.u32 q0, [r0]144; CHECK-BE-NEXT: vpsel q1, q0, q1145; CHECK-BE-NEXT: vrev64.32 q0, q1146; CHECK-BE-NEXT: bx lr147entry:148 %c = icmp sgt <4 x i32> %a, zeroinitializer149 %l = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %dest, i32 4, <4 x i1> %c, <4 x i32> %a)150 ret <4 x i32> %l151}152 153define arm_aapcs_vfpcc <4 x i32> @zext16_masked_v4i32_align2_zero(ptr %dest, <4 x i32> %a) {154; CHECK-LE-LABEL: zext16_masked_v4i32_align2_zero:155; CHECK-LE: @ %bb.0: @ %entry156; CHECK-LE-NEXT: vpt.s32 gt, q0, zr157; CHECK-LE-NEXT: vldrht.u32 q0, [r0]158; CHECK-LE-NEXT: bx lr159;160; CHECK-BE-LABEL: zext16_masked_v4i32_align2_zero:161; CHECK-BE: @ %bb.0: @ %entry162; CHECK-BE-NEXT: vrev64.32 q1, q0163; CHECK-BE-NEXT: vpt.s32 gt, q1, zr164; CHECK-BE-NEXT: vldrht.u32 q1, [r0]165; CHECK-BE-NEXT: vrev64.32 q0, q1166; CHECK-BE-NEXT: bx lr167entry:168 %c = icmp sgt <4 x i32> %a, zeroinitializer169 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 2, <4 x i1> %c, <4 x i16> zeroinitializer)170 %ext = zext <4 x i16> %l to <4 x i32>171 ret <4 x i32> %ext172}173 174define arm_aapcs_vfpcc <4 x i32> @zext16_masked_v4i32_align2_undef(ptr %dest, <4 x i32> %a) {175; CHECK-LE-LABEL: zext16_masked_v4i32_align2_undef:176; CHECK-LE: @ %bb.0: @ %entry177; CHECK-LE-NEXT: vpt.s32 gt, q0, zr178; CHECK-LE-NEXT: vldrht.u32 q0, [r0]179; CHECK-LE-NEXT: bx lr180;181; CHECK-BE-LABEL: zext16_masked_v4i32_align2_undef:182; CHECK-BE: @ %bb.0: @ %entry183; CHECK-BE-NEXT: vrev64.32 q1, q0184; CHECK-BE-NEXT: vpt.s32 gt, q1, zr185; CHECK-BE-NEXT: vldrht.u32 q1, [r0]186; CHECK-BE-NEXT: vrev64.32 q0, q1187; CHECK-BE-NEXT: bx lr188entry:189 %c = icmp sgt <4 x i32> %a, zeroinitializer190 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 2, <4 x i1> %c, <4 x i16> undef)191 %ext = zext <4 x i16> %l to <4 x i32>192 ret <4 x i32> %ext193}194 195define arm_aapcs_vfpcc <4 x i32> @zext16_masked_v4i32_align1_undef(ptr %dest, <4 x i32> %a) {196; CHECK-LE-LABEL: zext16_masked_v4i32_align1_undef:197; CHECK-LE: @ %bb.0: @ %entry198; CHECK-LE-NEXT: .pad #4199; CHECK-LE-NEXT: sub sp, #4200; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr201; CHECK-LE-NEXT: @ implicit-def: $q0202; CHECK-LE-NEXT: vmrs r2, p0203; CHECK-LE-NEXT: and r1, r2, #1204; CHECK-LE-NEXT: rsbs r3, r1, #0205; CHECK-LE-NEXT: movs r1, #0206; CHECK-LE-NEXT: bfi r1, r3, #0, #1207; CHECK-LE-NEXT: ubfx r3, r2, #4, #1208; CHECK-LE-NEXT: rsbs r3, r3, #0209; CHECK-LE-NEXT: bfi r1, r3, #1, #1210; CHECK-LE-NEXT: ubfx r3, r2, #8, #1211; CHECK-LE-NEXT: ubfx r2, r2, #12, #1212; CHECK-LE-NEXT: rsbs r3, r3, #0213; CHECK-LE-NEXT: bfi r1, r3, #2, #1214; CHECK-LE-NEXT: rsbs r2, r2, #0215; CHECK-LE-NEXT: bfi r1, r2, #3, #1216; CHECK-LE-NEXT: lsls r2, r1, #31217; CHECK-LE-NEXT: itt ne218; CHECK-LE-NEXT: ldrhne r2, [r0]219; CHECK-LE-NEXT: vmovne.32 q0[0], r2220; CHECK-LE-NEXT: lsls r2, r1, #30221; CHECK-LE-NEXT: itt mi222; CHECK-LE-NEXT: ldrhmi r2, [r0, #2]223; CHECK-LE-NEXT: vmovmi.32 q0[1], r2224; CHECK-LE-NEXT: lsls r2, r1, #29225; CHECK-LE-NEXT: itt mi226; CHECK-LE-NEXT: ldrhmi r2, [r0, #4]227; CHECK-LE-NEXT: vmovmi.32 q0[2], r2228; CHECK-LE-NEXT: lsls r1, r1, #28229; CHECK-LE-NEXT: itt mi230; CHECK-LE-NEXT: ldrhmi r0, [r0, #6]231; CHECK-LE-NEXT: vmovmi.32 q0[3], r0232; CHECK-LE-NEXT: vmovlb.s16 q0, q0233; CHECK-LE-NEXT: add sp, #4234; CHECK-LE-NEXT: bx lr235;236; CHECK-BE-LABEL: zext16_masked_v4i32_align1_undef:237; CHECK-BE: @ %bb.0: @ %entry238; CHECK-BE-NEXT: .pad #4239; CHECK-BE-NEXT: sub sp, #4240; CHECK-BE-NEXT: vrev64.32 q1, q0241; CHECK-BE-NEXT: @ implicit-def: $q0242; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr243; CHECK-BE-NEXT: vmrs r2, p0244; CHECK-BE-NEXT: ubfx r1, r2, #12, #1245; CHECK-BE-NEXT: rsbs r3, r1, #0246; CHECK-BE-NEXT: movs r1, #0247; CHECK-BE-NEXT: bfi r1, r3, #0, #1248; CHECK-BE-NEXT: ubfx r3, r2, #8, #1249; CHECK-BE-NEXT: rsbs r3, r3, #0250; CHECK-BE-NEXT: bfi r1, r3, #1, #1251; CHECK-BE-NEXT: ubfx r3, r2, #4, #1252; CHECK-BE-NEXT: and r2, r2, #1253; CHECK-BE-NEXT: rsbs r3, r3, #0254; CHECK-BE-NEXT: bfi r1, r3, #2, #1255; CHECK-BE-NEXT: rsbs r2, r2, #0256; CHECK-BE-NEXT: bfi r1, r2, #3, #1257; CHECK-BE-NEXT: lsls r2, r1, #28258; CHECK-BE-NEXT: itt mi259; CHECK-BE-NEXT: ldrhmi r2, [r0]260; CHECK-BE-NEXT: vmovmi.32 q0[0], r2261; CHECK-BE-NEXT: lsls r2, r1, #29262; CHECK-BE-NEXT: itt mi263; CHECK-BE-NEXT: ldrhmi r2, [r0, #2]264; CHECK-BE-NEXT: vmovmi.32 q0[1], r2265; CHECK-BE-NEXT: lsls r2, r1, #30266; CHECK-BE-NEXT: itt mi267; CHECK-BE-NEXT: ldrhmi r2, [r0, #4]268; CHECK-BE-NEXT: vmovmi.32 q0[2], r2269; CHECK-BE-NEXT: lsls r1, r1, #31270; CHECK-BE-NEXT: itt ne271; CHECK-BE-NEXT: ldrhne r0, [r0, #6]272; CHECK-BE-NEXT: vmovne.32 q0[3], r0273; CHECK-BE-NEXT: vmovlb.s16 q1, q0274; CHECK-BE-NEXT: vrev64.32 q0, q1275; CHECK-BE-NEXT: add sp, #4276; CHECK-BE-NEXT: bx lr277entry:278 %c = icmp sgt <4 x i32> %a, zeroinitializer279 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x i16> undef)280 %ext = sext <4 x i16> %l to <4 x i32>281 ret <4 x i32> %ext282}283 284define arm_aapcs_vfpcc <4 x i32> @zext16_masked_v4i32_align2_other(ptr %dest, <4 x i16> %a) {285; CHECK-LE-LABEL: zext16_masked_v4i32_align2_other:286; CHECK-LE: @ %bb.0: @ %entry287; CHECK-LE-NEXT: vmovlb.u16 q1, q0288; CHECK-LE-NEXT: vmovlb.s16 q0, q0289; CHECK-LE-NEXT: vpt.s32 gt, q0, zr290; CHECK-LE-NEXT: vldrht.u32 q0, [r0]291; CHECK-LE-NEXT: vpsel q0, q0, q1292; CHECK-LE-NEXT: bx lr293;294; CHECK-BE-LABEL: zext16_masked_v4i32_align2_other:295; CHECK-BE: @ %bb.0: @ %entry296; CHECK-BE-NEXT: vrev64.32 q1, q0297; CHECK-BE-NEXT: vmovlb.u16 q0, q1298; CHECK-BE-NEXT: vmovlb.s16 q1, q1299; CHECK-BE-NEXT: vpt.s32 gt, q1, zr300; CHECK-BE-NEXT: vldrht.u32 q1, [r0]301; CHECK-BE-NEXT: vpsel q1, q1, q0302; CHECK-BE-NEXT: vrev64.32 q0, q1303; CHECK-BE-NEXT: bx lr304entry:305 %c = icmp sgt <4 x i16> %a, zeroinitializer306 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 2, <4 x i1> %c, <4 x i16> %a)307 %ext = zext <4 x i16> %l to <4 x i32>308 ret <4 x i32> %ext309}310 311define arm_aapcs_vfpcc <4 x i32> @sext16_masked_v4i32_align2_zero(ptr %dest, <4 x i32> %a) {312; CHECK-LE-LABEL: sext16_masked_v4i32_align2_zero:313; CHECK-LE: @ %bb.0: @ %entry314; CHECK-LE-NEXT: vpt.s32 gt, q0, zr315; CHECK-LE-NEXT: vldrht.s32 q0, [r0]316; CHECK-LE-NEXT: bx lr317;318; CHECK-BE-LABEL: sext16_masked_v4i32_align2_zero:319; CHECK-BE: @ %bb.0: @ %entry320; CHECK-BE-NEXT: vrev64.32 q1, q0321; CHECK-BE-NEXT: vpt.s32 gt, q1, zr322; CHECK-BE-NEXT: vldrht.s32 q1, [r0]323; CHECK-BE-NEXT: vrev64.32 q0, q1324; CHECK-BE-NEXT: bx lr325entry:326 %c = icmp sgt <4 x i32> %a, zeroinitializer327 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 2, <4 x i1> %c, <4 x i16> zeroinitializer)328 %sext = sext <4 x i16> %l to <4 x i32>329 ret <4 x i32> %sext330}331 332define arm_aapcs_vfpcc <4 x i32> @sext16_masked_v4i32_align2_undef(ptr %dest, <4 x i32> %a) {333; CHECK-LE-LABEL: sext16_masked_v4i32_align2_undef:334; CHECK-LE: @ %bb.0: @ %entry335; CHECK-LE-NEXT: vpt.s32 gt, q0, zr336; CHECK-LE-NEXT: vldrht.s32 q0, [r0]337; CHECK-LE-NEXT: bx lr338;339; CHECK-BE-LABEL: sext16_masked_v4i32_align2_undef:340; CHECK-BE: @ %bb.0: @ %entry341; CHECK-BE-NEXT: vrev64.32 q1, q0342; CHECK-BE-NEXT: vpt.s32 gt, q1, zr343; CHECK-BE-NEXT: vldrht.s32 q1, [r0]344; CHECK-BE-NEXT: vrev64.32 q0, q1345; CHECK-BE-NEXT: bx lr346entry:347 %c = icmp sgt <4 x i32> %a, zeroinitializer348 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 2, <4 x i1> %c, <4 x i16> undef)349 %sext = sext <4 x i16> %l to <4 x i32>350 ret <4 x i32> %sext351}352 353define arm_aapcs_vfpcc <4 x i32> @sext16_masked_v4i32_align1_undef(ptr %dest, <4 x i32> %a) {354; CHECK-LE-LABEL: sext16_masked_v4i32_align1_undef:355; CHECK-LE: @ %bb.0: @ %entry356; CHECK-LE-NEXT: .pad #4357; CHECK-LE-NEXT: sub sp, #4358; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr359; CHECK-LE-NEXT: @ implicit-def: $q0360; CHECK-LE-NEXT: vmrs r2, p0361; CHECK-LE-NEXT: and r1, r2, #1362; CHECK-LE-NEXT: rsbs r3, r1, #0363; CHECK-LE-NEXT: movs r1, #0364; CHECK-LE-NEXT: bfi r1, r3, #0, #1365; CHECK-LE-NEXT: ubfx r3, r2, #4, #1366; CHECK-LE-NEXT: rsbs r3, r3, #0367; CHECK-LE-NEXT: bfi r1, r3, #1, #1368; CHECK-LE-NEXT: ubfx r3, r2, #8, #1369; CHECK-LE-NEXT: ubfx r2, r2, #12, #1370; CHECK-LE-NEXT: rsbs r3, r3, #0371; CHECK-LE-NEXT: bfi r1, r3, #2, #1372; CHECK-LE-NEXT: rsbs r2, r2, #0373; CHECK-LE-NEXT: bfi r1, r2, #3, #1374; CHECK-LE-NEXT: lsls r2, r1, #31375; CHECK-LE-NEXT: itt ne376; CHECK-LE-NEXT: ldrhne r2, [r0]377; CHECK-LE-NEXT: vmovne.32 q0[0], r2378; CHECK-LE-NEXT: lsls r2, r1, #30379; CHECK-LE-NEXT: itt mi380; CHECK-LE-NEXT: ldrhmi r2, [r0, #2]381; CHECK-LE-NEXT: vmovmi.32 q0[1], r2382; CHECK-LE-NEXT: lsls r2, r1, #29383; CHECK-LE-NEXT: itt mi384; CHECK-LE-NEXT: ldrhmi r2, [r0, #4]385; CHECK-LE-NEXT: vmovmi.32 q0[2], r2386; CHECK-LE-NEXT: lsls r1, r1, #28387; CHECK-LE-NEXT: itt mi388; CHECK-LE-NEXT: ldrhmi r0, [r0, #6]389; CHECK-LE-NEXT: vmovmi.32 q0[3], r0390; CHECK-LE-NEXT: vmovlb.s16 q0, q0391; CHECK-LE-NEXT: add sp, #4392; CHECK-LE-NEXT: bx lr393;394; CHECK-BE-LABEL: sext16_masked_v4i32_align1_undef:395; CHECK-BE: @ %bb.0: @ %entry396; CHECK-BE-NEXT: .pad #4397; CHECK-BE-NEXT: sub sp, #4398; CHECK-BE-NEXT: vrev64.32 q1, q0399; CHECK-BE-NEXT: @ implicit-def: $q0400; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr401; CHECK-BE-NEXT: vmrs r2, p0402; CHECK-BE-NEXT: ubfx r1, r2, #12, #1403; CHECK-BE-NEXT: rsbs r3, r1, #0404; CHECK-BE-NEXT: movs r1, #0405; CHECK-BE-NEXT: bfi r1, r3, #0, #1406; CHECK-BE-NEXT: ubfx r3, r2, #8, #1407; CHECK-BE-NEXT: rsbs r3, r3, #0408; CHECK-BE-NEXT: bfi r1, r3, #1, #1409; CHECK-BE-NEXT: ubfx r3, r2, #4, #1410; CHECK-BE-NEXT: and r2, r2, #1411; CHECK-BE-NEXT: rsbs r3, r3, #0412; CHECK-BE-NEXT: bfi r1, r3, #2, #1413; CHECK-BE-NEXT: rsbs r2, r2, #0414; CHECK-BE-NEXT: bfi r1, r2, #3, #1415; CHECK-BE-NEXT: lsls r2, r1, #28416; CHECK-BE-NEXT: itt mi417; CHECK-BE-NEXT: ldrhmi r2, [r0]418; CHECK-BE-NEXT: vmovmi.32 q0[0], r2419; CHECK-BE-NEXT: lsls r2, r1, #29420; CHECK-BE-NEXT: itt mi421; CHECK-BE-NEXT: ldrhmi r2, [r0, #2]422; CHECK-BE-NEXT: vmovmi.32 q0[1], r2423; CHECK-BE-NEXT: lsls r2, r1, #30424; CHECK-BE-NEXT: itt mi425; CHECK-BE-NEXT: ldrhmi r2, [r0, #4]426; CHECK-BE-NEXT: vmovmi.32 q0[2], r2427; CHECK-BE-NEXT: lsls r1, r1, #31428; CHECK-BE-NEXT: itt ne429; CHECK-BE-NEXT: ldrhne r0, [r0, #6]430; CHECK-BE-NEXT: vmovne.32 q0[3], r0431; CHECK-BE-NEXT: vmovlb.s16 q1, q0432; CHECK-BE-NEXT: vrev64.32 q0, q1433; CHECK-BE-NEXT: add sp, #4434; CHECK-BE-NEXT: bx lr435entry:436 %c = icmp sgt <4 x i32> %a, zeroinitializer437 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x i16> undef)438 %sext = sext <4 x i16> %l to <4 x i32>439 ret <4 x i32> %sext440}441 442define arm_aapcs_vfpcc <4 x i32> @sext16_masked_v4i32_align2_other(ptr %dest, <4 x i16> %a) {443; CHECK-LE-LABEL: sext16_masked_v4i32_align2_other:444; CHECK-LE: @ %bb.0: @ %entry445; CHECK-LE-NEXT: vmovlb.s16 q0, q0446; CHECK-LE-NEXT: vpt.s32 gt, q0, zr447; CHECK-LE-NEXT: vldrht.s32 q1, [r0]448; CHECK-LE-NEXT: vpsel q0, q1, q0449; CHECK-LE-NEXT: bx lr450;451; CHECK-BE-LABEL: sext16_masked_v4i32_align2_other:452; CHECK-BE: @ %bb.0: @ %entry453; CHECK-BE-NEXT: vrev64.32 q1, q0454; CHECK-BE-NEXT: vmovlb.s16 q0, q1455; CHECK-BE-NEXT: vpt.s32 gt, q0, zr456; CHECK-BE-NEXT: vldrht.s32 q1, [r0]457; CHECK-BE-NEXT: vpsel q1, q1, q0458; CHECK-BE-NEXT: vrev64.32 q0, q1459; CHECK-BE-NEXT: bx lr460entry:461 %c = icmp sgt <4 x i16> %a, zeroinitializer462 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 2, <4 x i1> %c, <4 x i16> %a)463 %sext = sext <4 x i16> %l to <4 x i32>464 ret <4 x i32> %sext465}466 467define arm_aapcs_vfpcc ptr @masked_v4i32_preinc(ptr %x, ptr %y, <4 x i32> %a) {468; CHECK-LE-LABEL: masked_v4i32_preinc:469; CHECK-LE: @ %bb.0: @ %entry470; CHECK-LE-NEXT: vpt.s32 gt, q0, zr471; CHECK-LE-NEXT: vldrwt.u32 q0, [r0, #4]!472; CHECK-LE-NEXT: vstrw.32 q0, [r1]473; CHECK-LE-NEXT: bx lr474;475; CHECK-BE-LABEL: masked_v4i32_preinc:476; CHECK-BE: @ %bb.0: @ %entry477; CHECK-BE-NEXT: vrev64.32 q1, q0478; CHECK-BE-NEXT: vpt.s32 gt, q1, zr479; CHECK-BE-NEXT: vldrwt.u32 q0, [r0, #4]!480; CHECK-BE-NEXT: vstrw.32 q0, [r1]481; CHECK-BE-NEXT: bx lr482entry:483 %z = getelementptr inbounds i8, ptr %x, i32 4484 %c = icmp sgt <4 x i32> %a, zeroinitializer485 %0 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %z, i32 4, <4 x i1> %c, <4 x i32> undef)486 store <4 x i32> %0, ptr %y, align 4487 ret ptr %z488}489 490define arm_aapcs_vfpcc ptr @masked_v4i32_postinc(ptr %x, ptr %y, <4 x i32> %a) {491; CHECK-LE-LABEL: masked_v4i32_postinc:492; CHECK-LE: @ %bb.0: @ %entry493; CHECK-LE-NEXT: vpt.s32 gt, q0, zr494; CHECK-LE-NEXT: vldrwt.u32 q0, [r0], #4495; CHECK-LE-NEXT: vstrw.32 q0, [r1]496; CHECK-LE-NEXT: bx lr497;498; CHECK-BE-LABEL: masked_v4i32_postinc:499; CHECK-BE: @ %bb.0: @ %entry500; CHECK-BE-NEXT: vrev64.32 q1, q0501; CHECK-BE-NEXT: vpt.s32 gt, q1, zr502; CHECK-BE-NEXT: vldrwt.u32 q0, [r0], #4503; CHECK-BE-NEXT: vstrw.32 q0, [r1]504; CHECK-BE-NEXT: bx lr505entry:506 %z = getelementptr inbounds i8, ptr %x, i32 4507 %c = icmp sgt <4 x i32> %a, zeroinitializer508 %0 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %x, i32 4, <4 x i1> %c, <4 x i32> undef)509 store <4 x i32> %0, ptr %y, align 4510 ret ptr %z511}512 513define arm_aapcs_vfpcc <8 x i16> @masked_v8i16_align4_zero(ptr %dest, <8 x i16> %a) {514; CHECK-LE-LABEL: masked_v8i16_align4_zero:515; CHECK-LE: @ %bb.0: @ %entry516; CHECK-LE-NEXT: vpt.s16 gt, q0, zr517; CHECK-LE-NEXT: vldrht.u16 q0, [r0]518; CHECK-LE-NEXT: bx lr519;520; CHECK-BE-LABEL: masked_v8i16_align4_zero:521; CHECK-BE: @ %bb.0: @ %entry522; CHECK-BE-NEXT: vrev64.16 q1, q0523; CHECK-BE-NEXT: vpt.s16 gt, q1, zr524; CHECK-BE-NEXT: vldrht.u16 q1, [r0]525; CHECK-BE-NEXT: vrev64.16 q0, q1526; CHECK-BE-NEXT: bx lr527entry:528 %c = icmp sgt <8 x i16> %a, zeroinitializer529 %l = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %dest, i32 2, <8 x i1> %c, <8 x i16> zeroinitializer)530 ret <8 x i16> %l531}532 533define arm_aapcs_vfpcc <8 x i16> @masked_v8i16_align2_undef(ptr %dest, <8 x i16> %a) {534; CHECK-LE-LABEL: masked_v8i16_align2_undef:535; CHECK-LE: @ %bb.0: @ %entry536; CHECK-LE-NEXT: vpt.s16 gt, q0, zr537; CHECK-LE-NEXT: vldrht.u16 q0, [r0]538; CHECK-LE-NEXT: bx lr539;540; CHECK-BE-LABEL: masked_v8i16_align2_undef:541; CHECK-BE: @ %bb.0: @ %entry542; CHECK-BE-NEXT: vrev64.16 q1, q0543; CHECK-BE-NEXT: vpt.s16 gt, q1, zr544; CHECK-BE-NEXT: vldrht.u16 q1, [r0]545; CHECK-BE-NEXT: vrev64.16 q0, q1546; CHECK-BE-NEXT: bx lr547entry:548 %c = icmp sgt <8 x i16> %a, zeroinitializer549 %l = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %dest, i32 2, <8 x i1> %c, <8 x i16> undef)550 ret <8 x i16> %l551}552 553define arm_aapcs_vfpcc <8 x i16> @masked_v8i16_align1_undef(ptr %dest, <8 x i16> %a) {554; CHECK-LE-LABEL: masked_v8i16_align1_undef:555; CHECK-LE: @ %bb.0: @ %entry556; CHECK-LE-NEXT: .pad #4557; CHECK-LE-NEXT: sub sp, #4558; CHECK-LE-NEXT: vcmp.s16 gt, q0, zr559; CHECK-LE-NEXT: @ implicit-def: $q0560; CHECK-LE-NEXT: vmrs r1, p0561; CHECK-LE-NEXT: and r2, r1, #1562; CHECK-LE-NEXT: rsbs r3, r2, #0563; CHECK-LE-NEXT: movs r2, #0564; CHECK-LE-NEXT: bfi r2, r3, #0, #1565; CHECK-LE-NEXT: ubfx r3, r1, #2, #1566; CHECK-LE-NEXT: rsbs r3, r3, #0567; CHECK-LE-NEXT: bfi r2, r3, #1, #1568; CHECK-LE-NEXT: ubfx r3, r1, #4, #1569; CHECK-LE-NEXT: rsbs r3, r3, #0570; CHECK-LE-NEXT: bfi r2, r3, #2, #1571; CHECK-LE-NEXT: ubfx r3, r1, #6, #1572; CHECK-LE-NEXT: rsbs r3, r3, #0573; CHECK-LE-NEXT: bfi r2, r3, #3, #1574; CHECK-LE-NEXT: ubfx r3, r1, #8, #1575; CHECK-LE-NEXT: rsbs r3, r3, #0576; CHECK-LE-NEXT: bfi r2, r3, #4, #1577; CHECK-LE-NEXT: ubfx r3, r1, #10, #1578; CHECK-LE-NEXT: rsbs r3, r3, #0579; CHECK-LE-NEXT: bfi r2, r3, #5, #1580; CHECK-LE-NEXT: ubfx r3, r1, #12, #1581; CHECK-LE-NEXT: ubfx r1, r1, #14, #1582; CHECK-LE-NEXT: rsbs r3, r3, #0583; CHECK-LE-NEXT: bfi r2, r3, #6, #1584; CHECK-LE-NEXT: rsbs r1, r1, #0585; CHECK-LE-NEXT: bfi r2, r1, #7, #1586; CHECK-LE-NEXT: uxtb r1, r2587; CHECK-LE-NEXT: lsls r2, r2, #31588; CHECK-LE-NEXT: itt ne589; CHECK-LE-NEXT: ldrhne r2, [r0]590; CHECK-LE-NEXT: vmovne.16 q0[0], r2591; CHECK-LE-NEXT: lsls r2, r1, #30592; CHECK-LE-NEXT: itt mi593; CHECK-LE-NEXT: ldrhmi r2, [r0, #2]594; CHECK-LE-NEXT: vmovmi.16 q0[1], r2595; CHECK-LE-NEXT: lsls r2, r1, #29596; CHECK-LE-NEXT: itt mi597; CHECK-LE-NEXT: ldrhmi r2, [r0, #4]598; CHECK-LE-NEXT: vmovmi.16 q0[2], r2599; CHECK-LE-NEXT: lsls r2, r1, #28600; CHECK-LE-NEXT: itt mi601; CHECK-LE-NEXT: ldrhmi r2, [r0, #6]602; CHECK-LE-NEXT: vmovmi.16 q0[3], r2603; CHECK-LE-NEXT: lsls r2, r1, #27604; CHECK-LE-NEXT: itt mi605; CHECK-LE-NEXT: ldrhmi r2, [r0, #8]606; CHECK-LE-NEXT: vmovmi.16 q0[4], r2607; CHECK-LE-NEXT: lsls r2, r1, #26608; CHECK-LE-NEXT: itt mi609; CHECK-LE-NEXT: ldrhmi r2, [r0, #10]610; CHECK-LE-NEXT: vmovmi.16 q0[5], r2611; CHECK-LE-NEXT: lsls r2, r1, #25612; CHECK-LE-NEXT: itt mi613; CHECK-LE-NEXT: ldrhmi r2, [r0, #12]614; CHECK-LE-NEXT: vmovmi.16 q0[6], r2615; CHECK-LE-NEXT: lsls r1, r1, #24616; CHECK-LE-NEXT: itt mi617; CHECK-LE-NEXT: ldrhmi r0, [r0, #14]618; CHECK-LE-NEXT: vmovmi.16 q0[7], r0619; CHECK-LE-NEXT: add sp, #4620; CHECK-LE-NEXT: bx lr621;622; CHECK-BE-LABEL: masked_v8i16_align1_undef:623; CHECK-BE: @ %bb.0: @ %entry624; CHECK-BE-NEXT: .pad #4625; CHECK-BE-NEXT: sub sp, #4626; CHECK-BE-NEXT: vrev64.16 q1, q0627; CHECK-BE-NEXT: vcmp.s16 gt, q1, zr628; CHECK-BE-NEXT: @ implicit-def: $q1629; CHECK-BE-NEXT: vmrs r1, p0630; CHECK-BE-NEXT: ubfx r2, r1, #14, #1631; CHECK-BE-NEXT: rsbs r3, r2, #0632; CHECK-BE-NEXT: movs r2, #0633; CHECK-BE-NEXT: bfi r2, r3, #0, #1634; CHECK-BE-NEXT: ubfx r3, r1, #12, #1635; CHECK-BE-NEXT: rsbs r3, r3, #0636; CHECK-BE-NEXT: bfi r2, r3, #1, #1637; CHECK-BE-NEXT: ubfx r3, r1, #10, #1638; CHECK-BE-NEXT: rsbs r3, r3, #0639; CHECK-BE-NEXT: bfi r2, r3, #2, #1640; CHECK-BE-NEXT: ubfx r3, r1, #8, #1641; CHECK-BE-NEXT: rsbs r3, r3, #0642; CHECK-BE-NEXT: bfi r2, r3, #3, #1643; CHECK-BE-NEXT: ubfx r3, r1, #6, #1644; CHECK-BE-NEXT: rsbs r3, r3, #0645; CHECK-BE-NEXT: bfi r2, r3, #4, #1646; CHECK-BE-NEXT: ubfx r3, r1, #4, #1647; CHECK-BE-NEXT: rsbs r3, r3, #0648; CHECK-BE-NEXT: bfi r2, r3, #5, #1649; CHECK-BE-NEXT: ubfx r3, r1, #2, #1650; CHECK-BE-NEXT: and r1, r1, #1651; CHECK-BE-NEXT: rsbs r3, r3, #0652; CHECK-BE-NEXT: bfi r2, r3, #6, #1653; CHECK-BE-NEXT: rsbs r1, r1, #0654; CHECK-BE-NEXT: bfi r2, r1, #7, #1655; CHECK-BE-NEXT: uxtb r1, r2656; CHECK-BE-NEXT: lsls r2, r2, #24657; CHECK-BE-NEXT: itt mi658; CHECK-BE-NEXT: ldrhmi r2, [r0]659; CHECK-BE-NEXT: vmovmi.16 q1[0], r2660; CHECK-BE-NEXT: lsls r2, r1, #25661; CHECK-BE-NEXT: itt mi662; CHECK-BE-NEXT: ldrhmi r2, [r0, #2]663; CHECK-BE-NEXT: vmovmi.16 q1[1], r2664; CHECK-BE-NEXT: lsls r2, r1, #26665; CHECK-BE-NEXT: itt mi666; CHECK-BE-NEXT: ldrhmi r2, [r0, #4]667; CHECK-BE-NEXT: vmovmi.16 q1[2], r2668; CHECK-BE-NEXT: lsls r2, r1, #27669; CHECK-BE-NEXT: itt mi670; CHECK-BE-NEXT: ldrhmi r2, [r0, #6]671; CHECK-BE-NEXT: vmovmi.16 q1[3], r2672; CHECK-BE-NEXT: lsls r2, r1, #28673; CHECK-BE-NEXT: itt mi674; CHECK-BE-NEXT: ldrhmi r2, [r0, #8]675; CHECK-BE-NEXT: vmovmi.16 q1[4], r2676; CHECK-BE-NEXT: lsls r2, r1, #29677; CHECK-BE-NEXT: itt mi678; CHECK-BE-NEXT: ldrhmi r2, [r0, #10]679; CHECK-BE-NEXT: vmovmi.16 q1[5], r2680; CHECK-BE-NEXT: lsls r2, r1, #30681; CHECK-BE-NEXT: itt mi682; CHECK-BE-NEXT: ldrhmi r2, [r0, #12]683; CHECK-BE-NEXT: vmovmi.16 q1[6], r2684; CHECK-BE-NEXT: lsls r1, r1, #31685; CHECK-BE-NEXT: itt ne686; CHECK-BE-NEXT: ldrhne r0, [r0, #14]687; CHECK-BE-NEXT: vmovne.16 q1[7], r0688; CHECK-BE-NEXT: vrev64.16 q0, q1689; CHECK-BE-NEXT: add sp, #4690; CHECK-BE-NEXT: bx lr691entry:692 %c = icmp sgt <8 x i16> %a, zeroinitializer693 %l = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %dest, i32 1, <8 x i1> %c, <8 x i16> undef)694 ret <8 x i16> %l695}696 697define arm_aapcs_vfpcc <8 x i16> @masked_v8i16_align4_other(ptr %dest, <8 x i16> %a) {698; CHECK-LE-LABEL: masked_v8i16_align4_other:699; CHECK-LE: @ %bb.0: @ %entry700; CHECK-LE-NEXT: vpt.s16 gt, q0, zr701; CHECK-LE-NEXT: vldrht.u16 q1, [r0]702; CHECK-LE-NEXT: vpsel q0, q1, q0703; CHECK-LE-NEXT: bx lr704;705; CHECK-BE-LABEL: masked_v8i16_align4_other:706; CHECK-BE: @ %bb.0: @ %entry707; CHECK-BE-NEXT: vrev64.16 q1, q0708; CHECK-BE-NEXT: vpt.s16 gt, q1, zr709; CHECK-BE-NEXT: vldrht.u16 q0, [r0]710; CHECK-BE-NEXT: vpsel q1, q0, q1711; CHECK-BE-NEXT: vrev64.16 q0, q1712; CHECK-BE-NEXT: bx lr713entry:714 %c = icmp sgt <8 x i16> %a, zeroinitializer715 %l = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %dest, i32 2, <8 x i1> %c, <8 x i16> %a)716 ret <8 x i16> %l717}718 719define arm_aapcs_vfpcc <8 x i16> @sext8_masked_v8i16_align1_zero(ptr %dest, <8 x i8> %a) {720; CHECK-LE-LABEL: sext8_masked_v8i16_align1_zero:721; CHECK-LE: @ %bb.0: @ %entry722; CHECK-LE-NEXT: vmovlb.s8 q0, q0723; CHECK-LE-NEXT: vpt.s16 gt, q0, zr724; CHECK-LE-NEXT: vldrbt.s16 q0, [r0]725; CHECK-LE-NEXT: bx lr726;727; CHECK-BE-LABEL: sext8_masked_v8i16_align1_zero:728; CHECK-BE: @ %bb.0: @ %entry729; CHECK-BE-NEXT: vrev64.16 q1, q0730; CHECK-BE-NEXT: vmovlb.s8 q0, q1731; CHECK-BE-NEXT: vpt.s16 gt, q0, zr732; CHECK-BE-NEXT: vldrbt.s16 q1, [r0]733; CHECK-BE-NEXT: vrev64.16 q0, q1734; CHECK-BE-NEXT: bx lr735entry:736 %c = icmp sgt <8 x i8> %a, zeroinitializer737 %l = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %dest, i32 1, <8 x i1> %c, <8 x i8> zeroinitializer)738 %ext = sext <8 x i8> %l to <8 x i16>739 ret <8 x i16> %ext740}741 742define arm_aapcs_vfpcc <8 x i16> @sext8_masked_v8i16_align1_undef(ptr %dest, <8 x i8> %a) {743; CHECK-LE-LABEL: sext8_masked_v8i16_align1_undef:744; CHECK-LE: @ %bb.0: @ %entry745; CHECK-LE-NEXT: vmovlb.s8 q0, q0746; CHECK-LE-NEXT: vpt.s16 gt, q0, zr747; CHECK-LE-NEXT: vldrbt.s16 q0, [r0]748; CHECK-LE-NEXT: bx lr749;750; CHECK-BE-LABEL: sext8_masked_v8i16_align1_undef:751; CHECK-BE: @ %bb.0: @ %entry752; CHECK-BE-NEXT: vrev64.16 q1, q0753; CHECK-BE-NEXT: vmovlb.s8 q0, q1754; CHECK-BE-NEXT: vpt.s16 gt, q0, zr755; CHECK-BE-NEXT: vldrbt.s16 q1, [r0]756; CHECK-BE-NEXT: vrev64.16 q0, q1757; CHECK-BE-NEXT: bx lr758entry:759 %c = icmp sgt <8 x i8> %a, zeroinitializer760 %l = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %dest, i32 1, <8 x i1> %c, <8 x i8> undef)761 %ext = sext <8 x i8> %l to <8 x i16>762 ret <8 x i16> %ext763}764 765define arm_aapcs_vfpcc <8 x i16> @sext8_masked_v8i16_align1_other(ptr %dest, <8 x i8> %a) {766; CHECK-LE-LABEL: sext8_masked_v8i16_align1_other:767; CHECK-LE: @ %bb.0: @ %entry768; CHECK-LE-NEXT: vmovlb.s8 q0, q0769; CHECK-LE-NEXT: vpt.s16 gt, q0, zr770; CHECK-LE-NEXT: vldrbt.s16 q1, [r0]771; CHECK-LE-NEXT: vpsel q0, q1, q0772; CHECK-LE-NEXT: bx lr773;774; CHECK-BE-LABEL: sext8_masked_v8i16_align1_other:775; CHECK-BE: @ %bb.0: @ %entry776; CHECK-BE-NEXT: vrev64.16 q1, q0777; CHECK-BE-NEXT: vmovlb.s8 q0, q1778; CHECK-BE-NEXT: vpt.s16 gt, q0, zr779; CHECK-BE-NEXT: vldrbt.s16 q1, [r0]780; CHECK-BE-NEXT: vpsel q1, q1, q0781; CHECK-BE-NEXT: vrev64.16 q0, q1782; CHECK-BE-NEXT: bx lr783entry:784 %c = icmp sgt <8 x i8> %a, zeroinitializer785 %l = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %dest, i32 1, <8 x i1> %c, <8 x i8> %a)786 %ext = sext <8 x i8> %l to <8 x i16>787 ret <8 x i16> %ext788}789 790define arm_aapcs_vfpcc <4 x i32> @sext8_masked_v4i32_align1_zero(ptr %dest, <4 x i8> %a) {791; CHECK-LE-LABEL: sext8_masked_v4i32_align1_zero:792; CHECK-LE: @ %bb.0: @ %entry793; CHECK-LE-NEXT: vmovlb.s8 q0, q0794; CHECK-LE-NEXT: vmovlb.s16 q0, q0795; CHECK-LE-NEXT: vpt.s32 gt, q0, zr796; CHECK-LE-NEXT: vldrbt.s32 q0, [r0]797; CHECK-LE-NEXT: bx lr798;799; CHECK-BE-LABEL: sext8_masked_v4i32_align1_zero:800; CHECK-BE: @ %bb.0: @ %entry801; CHECK-BE-NEXT: vrev64.32 q1, q0802; CHECK-BE-NEXT: vmovlb.s8 q0, q1803; CHECK-BE-NEXT: vmovlb.s16 q0, q0804; CHECK-BE-NEXT: vpt.s32 gt, q0, zr805; CHECK-BE-NEXT: vldrbt.s32 q1, [r0]806; CHECK-BE-NEXT: vrev64.32 q0, q1807; CHECK-BE-NEXT: bx lr808entry:809 %c = icmp sgt <4 x i8> %a, zeroinitializer810 %l = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x i8> zeroinitializer)811 %ext = sext <4 x i8> %l to <4 x i32>812 ret <4 x i32> %ext813}814 815define arm_aapcs_vfpcc <4 x i32> @sext8_masked_v4i32_align1_undef(ptr %dest, <4 x i8> %a) {816; CHECK-LE-LABEL: sext8_masked_v4i32_align1_undef:817; CHECK-LE: @ %bb.0: @ %entry818; CHECK-LE-NEXT: vmovlb.s8 q0, q0819; CHECK-LE-NEXT: vmovlb.s16 q0, q0820; CHECK-LE-NEXT: vpt.s32 gt, q0, zr821; CHECK-LE-NEXT: vldrbt.s32 q0, [r0]822; CHECK-LE-NEXT: bx lr823;824; CHECK-BE-LABEL: sext8_masked_v4i32_align1_undef:825; CHECK-BE: @ %bb.0: @ %entry826; CHECK-BE-NEXT: vrev64.32 q1, q0827; CHECK-BE-NEXT: vmovlb.s8 q0, q1828; CHECK-BE-NEXT: vmovlb.s16 q0, q0829; CHECK-BE-NEXT: vpt.s32 gt, q0, zr830; CHECK-BE-NEXT: vldrbt.s32 q1, [r0]831; CHECK-BE-NEXT: vrev64.32 q0, q1832; CHECK-BE-NEXT: bx lr833entry:834 %c = icmp sgt <4 x i8> %a, zeroinitializer835 %l = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x i8> undef)836 %ext = sext <4 x i8> %l to <4 x i32>837 ret <4 x i32> %ext838}839 840define arm_aapcs_vfpcc <4 x i32> @sext8_masked_v4i32_align1_other(ptr %dest, <4 x i8> %a) {841; CHECK-LE-LABEL: sext8_masked_v4i32_align1_other:842; CHECK-LE: @ %bb.0: @ %entry843; CHECK-LE-NEXT: vmovlb.s8 q0, q0844; CHECK-LE-NEXT: vmovlb.s16 q0, q0845; CHECK-LE-NEXT: vpt.s32 gt, q0, zr846; CHECK-LE-NEXT: vldrbt.s32 q1, [r0]847; CHECK-LE-NEXT: vpsel q0, q1, q0848; CHECK-LE-NEXT: bx lr849;850; CHECK-BE-LABEL: sext8_masked_v4i32_align1_other:851; CHECK-BE: @ %bb.0: @ %entry852; CHECK-BE-NEXT: vrev64.32 q1, q0853; CHECK-BE-NEXT: vmovlb.s8 q0, q1854; CHECK-BE-NEXT: vmovlb.s16 q0, q0855; CHECK-BE-NEXT: vpt.s32 gt, q0, zr856; CHECK-BE-NEXT: vldrbt.s32 q1, [r0]857; CHECK-BE-NEXT: vpsel q1, q1, q0858; CHECK-BE-NEXT: vrev64.32 q0, q1859; CHECK-BE-NEXT: bx lr860entry:861 %c = icmp sgt <4 x i8> %a, zeroinitializer862 %l = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x i8> %a)863 %ext = sext <4 x i8> %l to <4 x i32>864 ret <4 x i32> %ext865}866 867define arm_aapcs_vfpcc <4 x i32> @zext8_masked_v4i32_align1_zero(ptr %dest, <4 x i8> %a) {868; CHECK-LE-LABEL: zext8_masked_v4i32_align1_zero:869; CHECK-LE: @ %bb.0: @ %entry870; CHECK-LE-NEXT: vmovlb.s8 q0, q0871; CHECK-LE-NEXT: vmovlb.s16 q0, q0872; CHECK-LE-NEXT: vpt.s32 gt, q0, zr873; CHECK-LE-NEXT: vldrbt.u32 q0, [r0]874; CHECK-LE-NEXT: bx lr875;876; CHECK-BE-LABEL: zext8_masked_v4i32_align1_zero:877; CHECK-BE: @ %bb.0: @ %entry878; CHECK-BE-NEXT: vrev64.32 q1, q0879; CHECK-BE-NEXT: vmovlb.s8 q0, q1880; CHECK-BE-NEXT: vmovlb.s16 q0, q0881; CHECK-BE-NEXT: vpt.s32 gt, q0, zr882; CHECK-BE-NEXT: vldrbt.u32 q1, [r0]883; CHECK-BE-NEXT: vrev64.32 q0, q1884; CHECK-BE-NEXT: bx lr885entry:886 %c = icmp sgt <4 x i8> %a, zeroinitializer887 %l = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x i8> zeroinitializer)888 %ext = zext <4 x i8> %l to <4 x i32>889 ret <4 x i32> %ext890}891 892define arm_aapcs_vfpcc <4 x i32> @zext8_masked_v4i32_align1_undef(ptr %dest, <4 x i8> %a) {893; CHECK-LE-LABEL: zext8_masked_v4i32_align1_undef:894; CHECK-LE: @ %bb.0: @ %entry895; CHECK-LE-NEXT: vmovlb.s8 q0, q0896; CHECK-LE-NEXT: vmovlb.s16 q0, q0897; CHECK-LE-NEXT: vpt.s32 gt, q0, zr898; CHECK-LE-NEXT: vldrbt.u32 q0, [r0]899; CHECK-LE-NEXT: bx lr900;901; CHECK-BE-LABEL: zext8_masked_v4i32_align1_undef:902; CHECK-BE: @ %bb.0: @ %entry903; CHECK-BE-NEXT: vrev64.32 q1, q0904; CHECK-BE-NEXT: vmovlb.s8 q0, q1905; CHECK-BE-NEXT: vmovlb.s16 q0, q0906; CHECK-BE-NEXT: vpt.s32 gt, q0, zr907; CHECK-BE-NEXT: vldrbt.u32 q1, [r0]908; CHECK-BE-NEXT: vrev64.32 q0, q1909; CHECK-BE-NEXT: bx lr910entry:911 %c = icmp sgt <4 x i8> %a, zeroinitializer912 %l = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x i8> undef)913 %ext = zext <4 x i8> %l to <4 x i32>914 ret <4 x i32> %ext915}916 917define arm_aapcs_vfpcc <4 x i32> @zext8_masked_v4i32_align1_other(ptr %dest, <4 x i8> %a) {918; CHECK-LE-LABEL: zext8_masked_v4i32_align1_other:919; CHECK-LE: @ %bb.0: @ %entry920; CHECK-LE-NEXT: vmov.i32 q1, #0xff921; CHECK-LE-NEXT: vand q1, q0, q1922; CHECK-LE-NEXT: vmovlb.s8 q0, q0923; CHECK-LE-NEXT: vmovlb.s16 q0, q0924; CHECK-LE-NEXT: vpt.s32 gt, q0, zr925; CHECK-LE-NEXT: vldrbt.u32 q0, [r0]926; CHECK-LE-NEXT: vpsel q0, q0, q1927; CHECK-LE-NEXT: bx lr928;929; CHECK-BE-LABEL: zext8_masked_v4i32_align1_other:930; CHECK-BE: @ %bb.0: @ %entry931; CHECK-BE-NEXT: vmov.i32 q1, #0xff932; CHECK-BE-NEXT: vrev64.32 q2, q0933; CHECK-BE-NEXT: vand q0, q2, q1934; CHECK-BE-NEXT: vmovlb.s8 q1, q2935; CHECK-BE-NEXT: vmovlb.s16 q1, q1936; CHECK-BE-NEXT: vpt.s32 gt, q1, zr937; CHECK-BE-NEXT: vldrbt.u32 q1, [r0]938; CHECK-BE-NEXT: vpsel q1, q1, q0939; CHECK-BE-NEXT: vrev64.32 q0, q1940; CHECK-BE-NEXT: bx lr941entry:942 %c = icmp sgt <4 x i8> %a, zeroinitializer943 %l = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x i8> %a)944 %ext = zext <4 x i8> %l to <4 x i32>945 ret <4 x i32> %ext946}947 948define arm_aapcs_vfpcc <8 x i16> @zext8_masked_v8i16_align1_zero(ptr %dest, <8 x i8> %a) {949; CHECK-LE-LABEL: zext8_masked_v8i16_align1_zero:950; CHECK-LE: @ %bb.0: @ %entry951; CHECK-LE-NEXT: vmovlb.s8 q0, q0952; CHECK-LE-NEXT: vpt.s16 gt, q0, zr953; CHECK-LE-NEXT: vldrbt.u16 q0, [r0]954; CHECK-LE-NEXT: bx lr955;956; CHECK-BE-LABEL: zext8_masked_v8i16_align1_zero:957; CHECK-BE: @ %bb.0: @ %entry958; CHECK-BE-NEXT: vrev64.16 q1, q0959; CHECK-BE-NEXT: vmovlb.s8 q0, q1960; CHECK-BE-NEXT: vpt.s16 gt, q0, zr961; CHECK-BE-NEXT: vldrbt.u16 q1, [r0]962; CHECK-BE-NEXT: vrev64.16 q0, q1963; CHECK-BE-NEXT: bx lr964entry:965 %c = icmp sgt <8 x i8> %a, zeroinitializer966 %l = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %dest, i32 1, <8 x i1> %c, <8 x i8> zeroinitializer)967 %ext = zext <8 x i8> %l to <8 x i16>968 ret <8 x i16> %ext969}970 971define arm_aapcs_vfpcc <8 x i16> @zext8_masked_v8i16_align1_undef(ptr %dest, <8 x i8> %a) {972; CHECK-LE-LABEL: zext8_masked_v8i16_align1_undef:973; CHECK-LE: @ %bb.0: @ %entry974; CHECK-LE-NEXT: vmovlb.s8 q0, q0975; CHECK-LE-NEXT: vpt.s16 gt, q0, zr976; CHECK-LE-NEXT: vldrbt.u16 q0, [r0]977; CHECK-LE-NEXT: bx lr978;979; CHECK-BE-LABEL: zext8_masked_v8i16_align1_undef:980; CHECK-BE: @ %bb.0: @ %entry981; CHECK-BE-NEXT: vrev64.16 q1, q0982; CHECK-BE-NEXT: vmovlb.s8 q0, q1983; CHECK-BE-NEXT: vpt.s16 gt, q0, zr984; CHECK-BE-NEXT: vldrbt.u16 q1, [r0]985; CHECK-BE-NEXT: vrev64.16 q0, q1986; CHECK-BE-NEXT: bx lr987entry:988 %c = icmp sgt <8 x i8> %a, zeroinitializer989 %l = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %dest, i32 1, <8 x i1> %c, <8 x i8> undef)990 %ext = zext <8 x i8> %l to <8 x i16>991 ret <8 x i16> %ext992}993 994define arm_aapcs_vfpcc <8 x i16> @zext8_masked_v8i16_align1_other(ptr %dest, <8 x i8> %a) {995; CHECK-LE-LABEL: zext8_masked_v8i16_align1_other:996; CHECK-LE: @ %bb.0: @ %entry997; CHECK-LE-NEXT: vmovlb.u8 q1, q0998; CHECK-LE-NEXT: vmovlb.s8 q0, q0999; CHECK-LE-NEXT: vpt.s16 gt, q0, zr1000; CHECK-LE-NEXT: vldrbt.u16 q0, [r0]1001; CHECK-LE-NEXT: vpsel q0, q0, q11002; CHECK-LE-NEXT: bx lr1003;1004; CHECK-BE-LABEL: zext8_masked_v8i16_align1_other:1005; CHECK-BE: @ %bb.0: @ %entry1006; CHECK-BE-NEXT: vrev64.16 q1, q01007; CHECK-BE-NEXT: vmovlb.u8 q0, q11008; CHECK-BE-NEXT: vmovlb.s8 q1, q11009; CHECK-BE-NEXT: vpt.s16 gt, q1, zr1010; CHECK-BE-NEXT: vldrbt.u16 q1, [r0]1011; CHECK-BE-NEXT: vpsel q1, q1, q01012; CHECK-BE-NEXT: vrev64.16 q0, q11013; CHECK-BE-NEXT: bx lr1014entry:1015 %c = icmp sgt <8 x i8> %a, zeroinitializer1016 %l = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %dest, i32 1, <8 x i1> %c, <8 x i8> %a)1017 %ext = zext <8 x i8> %l to <8 x i16>1018 ret <8 x i16> %ext1019}1020 1021define ptr @masked_v8i16_preinc(ptr %x, ptr %y, <8 x i16> %a) {1022; CHECK-LE-LABEL: masked_v8i16_preinc:1023; CHECK-LE: @ %bb.0: @ %entry1024; CHECK-LE-NEXT: vldr d1, [sp]1025; CHECK-LE-NEXT: vmov d0, r2, r31026; CHECK-LE-NEXT: vpt.s16 gt, q0, zr1027; CHECK-LE-NEXT: vldrht.u16 q0, [r0, #4]!1028; CHECK-LE-NEXT: vstrw.32 q0, [r1]1029; CHECK-LE-NEXT: bx lr1030;1031; CHECK-BE-LABEL: masked_v8i16_preinc:1032; CHECK-BE: @ %bb.0: @ %entry1033; CHECK-BE-NEXT: vldr d1, [sp]1034; CHECK-BE-NEXT: vmov d0, r3, r21035; CHECK-BE-NEXT: vrev64.16 q1, q01036; CHECK-BE-NEXT: vpt.s16 gt, q1, zr1037; CHECK-BE-NEXT: vldrht.u16 q0, [r0, #4]!1038; CHECK-BE-NEXT: vstrh.16 q0, [r1]1039; CHECK-BE-NEXT: bx lr1040entry:1041 %z = getelementptr inbounds i8, ptr %x, i32 41042 %c = icmp sgt <8 x i16> %a, zeroinitializer1043 %0 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %z, i32 4, <8 x i1> %c, <8 x i16> undef)1044 store <8 x i16> %0, ptr %y, align 41045 ret ptr %z1046}1047 1048define arm_aapcs_vfpcc ptr @masked_v8i16_postinc(ptr %x, ptr %y, <8 x i16> %a) {1049; CHECK-LE-LABEL: masked_v8i16_postinc:1050; CHECK-LE: @ %bb.0: @ %entry1051; CHECK-LE-NEXT: vpt.s16 gt, q0, zr1052; CHECK-LE-NEXT: vldrht.u16 q0, [r0], #41053; CHECK-LE-NEXT: vstrw.32 q0, [r1]1054; CHECK-LE-NEXT: bx lr1055;1056; CHECK-BE-LABEL: masked_v8i16_postinc:1057; CHECK-BE: @ %bb.0: @ %entry1058; CHECK-BE-NEXT: vrev64.16 q1, q01059; CHECK-BE-NEXT: vpt.s16 gt, q1, zr1060; CHECK-BE-NEXT: vldrht.u16 q0, [r0], #41061; CHECK-BE-NEXT: vstrh.16 q0, [r1]1062; CHECK-BE-NEXT: bx lr1063entry:1064 %z = getelementptr inbounds i8, ptr %x, i32 41065 %c = icmp sgt <8 x i16> %a, zeroinitializer1066 %0 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %x, i32 4, <8 x i1> %c, <8 x i16> undef)1067 store <8 x i16> %0, ptr %y, align 41068 ret ptr %z1069}1070 1071 1072define arm_aapcs_vfpcc <16 x i8> @masked_v16i8_align4_zero(ptr %dest, <16 x i8> %a) {1073; CHECK-LE-LABEL: masked_v16i8_align4_zero:1074; CHECK-LE: @ %bb.0: @ %entry1075; CHECK-LE-NEXT: vpt.s8 gt, q0, zr1076; CHECK-LE-NEXT: vldrbt.u8 q0, [r0]1077; CHECK-LE-NEXT: bx lr1078;1079; CHECK-BE-LABEL: masked_v16i8_align4_zero:1080; CHECK-BE: @ %bb.0: @ %entry1081; CHECK-BE-NEXT: vrev64.8 q1, q01082; CHECK-BE-NEXT: vpt.s8 gt, q1, zr1083; CHECK-BE-NEXT: vldrbt.u8 q1, [r0]1084; CHECK-BE-NEXT: vrev64.8 q0, q11085; CHECK-BE-NEXT: bx lr1086entry:1087 %c = icmp sgt <16 x i8> %a, zeroinitializer1088 %l = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %dest, i32 1, <16 x i1> %c, <16 x i8> zeroinitializer)1089 ret <16 x i8> %l1090}1091 1092define arm_aapcs_vfpcc <16 x i8> @masked_v16i8_align4_undef(ptr %dest, <16 x i8> %a) {1093; CHECK-LE-LABEL: masked_v16i8_align4_undef:1094; CHECK-LE: @ %bb.0: @ %entry1095; CHECK-LE-NEXT: vpt.s8 gt, q0, zr1096; CHECK-LE-NEXT: vldrbt.u8 q0, [r0]1097; CHECK-LE-NEXT: bx lr1098;1099; CHECK-BE-LABEL: masked_v16i8_align4_undef:1100; CHECK-BE: @ %bb.0: @ %entry1101; CHECK-BE-NEXT: vrev64.8 q1, q01102; CHECK-BE-NEXT: vpt.s8 gt, q1, zr1103; CHECK-BE-NEXT: vldrbt.u8 q1, [r0]1104; CHECK-BE-NEXT: vrev64.8 q0, q11105; CHECK-BE-NEXT: bx lr1106entry:1107 %c = icmp sgt <16 x i8> %a, zeroinitializer1108 %l = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %dest, i32 1, <16 x i1> %c, <16 x i8> undef)1109 ret <16 x i8> %l1110}1111 1112define arm_aapcs_vfpcc <16 x i8> @masked_v16i8_align4_other(ptr %dest, <16 x i8> %a) {1113; CHECK-LE-LABEL: masked_v16i8_align4_other:1114; CHECK-LE: @ %bb.0: @ %entry1115; CHECK-LE-NEXT: vpt.s8 gt, q0, zr1116; CHECK-LE-NEXT: vldrbt.u8 q1, [r0]1117; CHECK-LE-NEXT: vpsel q0, q1, q01118; CHECK-LE-NEXT: bx lr1119;1120; CHECK-BE-LABEL: masked_v16i8_align4_other:1121; CHECK-BE: @ %bb.0: @ %entry1122; CHECK-BE-NEXT: vrev64.8 q1, q01123; CHECK-BE-NEXT: vpt.s8 gt, q1, zr1124; CHECK-BE-NEXT: vldrbt.u8 q0, [r0]1125; CHECK-BE-NEXT: vpsel q1, q0, q11126; CHECK-BE-NEXT: vrev64.8 q0, q11127; CHECK-BE-NEXT: bx lr1128entry:1129 %c = icmp sgt <16 x i8> %a, zeroinitializer1130 %l = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %dest, i32 1, <16 x i1> %c, <16 x i8> %a)1131 ret <16 x i8> %l1132}1133 1134define arm_aapcs_vfpcc ptr @masked_v16i8_preinc(ptr %x, ptr %y, <16 x i8> %a) {1135; CHECK-LE-LABEL: masked_v16i8_preinc:1136; CHECK-LE: @ %bb.0: @ %entry1137; CHECK-LE-NEXT: vpt.s8 gt, q0, zr1138; CHECK-LE-NEXT: vldrbt.u8 q0, [r0, #4]!1139; CHECK-LE-NEXT: vstrw.32 q0, [r1]1140; CHECK-LE-NEXT: bx lr1141;1142; CHECK-BE-LABEL: masked_v16i8_preinc:1143; CHECK-BE: @ %bb.0: @ %entry1144; CHECK-BE-NEXT: vrev64.8 q1, q01145; CHECK-BE-NEXT: vpt.s8 gt, q1, zr1146; CHECK-BE-NEXT: vldrbt.u8 q0, [r0, #4]!1147; CHECK-BE-NEXT: vstrb.8 q0, [r1]1148; CHECK-BE-NEXT: bx lr1149entry:1150 %z = getelementptr inbounds i8, ptr %x, i32 41151 %c = icmp sgt <16 x i8> %a, zeroinitializer1152 %0 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %z, i32 4, <16 x i1> %c, <16 x i8> undef)1153 store <16 x i8> %0, ptr %y, align 41154 ret ptr %z1155}1156 1157define arm_aapcs_vfpcc ptr @masked_v16i8_postinc(ptr %x, ptr %y, <16 x i8> %a) {1158; CHECK-LE-LABEL: masked_v16i8_postinc:1159; CHECK-LE: @ %bb.0: @ %entry1160; CHECK-LE-NEXT: vpt.s8 gt, q0, zr1161; CHECK-LE-NEXT: vldrbt.u8 q0, [r0], #41162; CHECK-LE-NEXT: vstrw.32 q0, [r1]1163; CHECK-LE-NEXT: bx lr1164;1165; CHECK-BE-LABEL: masked_v16i8_postinc:1166; CHECK-BE: @ %bb.0: @ %entry1167; CHECK-BE-NEXT: vrev64.8 q1, q01168; CHECK-BE-NEXT: vpt.s8 gt, q1, zr1169; CHECK-BE-NEXT: vldrbt.u8 q0, [r0], #41170; CHECK-BE-NEXT: vstrb.8 q0, [r1]1171; CHECK-BE-NEXT: bx lr1172entry:1173 %z = getelementptr inbounds i8, ptr %x, i32 41174 %c = icmp sgt <16 x i8> %a, zeroinitializer1175 %0 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %x, i32 4, <16 x i1> %c, <16 x i8> undef)1176 store <16 x i8> %0, ptr %y, align 41177 ret ptr %z1178}1179 1180 1181define arm_aapcs_vfpcc <4 x float> @masked_v4f32_align4_zero(ptr %dest, <4 x i32> %a) {1182; CHECK-LE-LABEL: masked_v4f32_align4_zero:1183; CHECK-LE: @ %bb.0: @ %entry1184; CHECK-LE-NEXT: vpt.s32 gt, q0, zr1185; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]1186; CHECK-LE-NEXT: bx lr1187;1188; CHECK-BE-LABEL: masked_v4f32_align4_zero:1189; CHECK-BE: @ %bb.0: @ %entry1190; CHECK-BE-NEXT: vrev64.32 q1, q01191; CHECK-BE-NEXT: vpt.s32 gt, q1, zr1192; CHECK-BE-NEXT: vldrwt.u32 q1, [r0]1193; CHECK-BE-NEXT: vrev64.32 q0, q11194; CHECK-BE-NEXT: bx lr1195entry:1196 %c = icmp sgt <4 x i32> %a, zeroinitializer1197 %l = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %dest, i32 4, <4 x i1> %c, <4 x float> zeroinitializer)1198 ret <4 x float> %l1199}1200 1201define arm_aapcs_vfpcc <4 x float> @masked_v4f32_align4_undef(ptr %dest, <4 x i32> %a) {1202; CHECK-LE-LABEL: masked_v4f32_align4_undef:1203; CHECK-LE: @ %bb.0: @ %entry1204; CHECK-LE-NEXT: vpt.s32 gt, q0, zr1205; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]1206; CHECK-LE-NEXT: bx lr1207;1208; CHECK-BE-LABEL: masked_v4f32_align4_undef:1209; CHECK-BE: @ %bb.0: @ %entry1210; CHECK-BE-NEXT: vrev64.32 q1, q01211; CHECK-BE-NEXT: vpt.s32 gt, q1, zr1212; CHECK-BE-NEXT: vldrwt.u32 q1, [r0]1213; CHECK-BE-NEXT: vrev64.32 q0, q11214; CHECK-BE-NEXT: bx lr1215entry:1216 %c = icmp sgt <4 x i32> %a, zeroinitializer1217 %l = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %dest, i32 4, <4 x i1> %c, <4 x float> undef)1218 ret <4 x float> %l1219}1220 1221define arm_aapcs_vfpcc <4 x float> @masked_v4f32_align1_undef(ptr %dest, <4 x i32> %a) {1222; CHECK-LE-LABEL: masked_v4f32_align1_undef:1223; CHECK-LE: @ %bb.0: @ %entry1224; CHECK-LE-NEXT: .pad #41225; CHECK-LE-NEXT: sub sp, #41226; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr1227; CHECK-LE-NEXT: @ implicit-def: $q01228; CHECK-LE-NEXT: vmrs r2, p01229; CHECK-LE-NEXT: and r1, r2, #11230; CHECK-LE-NEXT: rsbs r3, r1, #01231; CHECK-LE-NEXT: movs r1, #01232; CHECK-LE-NEXT: bfi r1, r3, #0, #11233; CHECK-LE-NEXT: ubfx r3, r2, #4, #11234; CHECK-LE-NEXT: rsbs r3, r3, #01235; CHECK-LE-NEXT: bfi r1, r3, #1, #11236; CHECK-LE-NEXT: ubfx r3, r2, #8, #11237; CHECK-LE-NEXT: ubfx r2, r2, #12, #11238; CHECK-LE-NEXT: rsbs r3, r3, #01239; CHECK-LE-NEXT: bfi r1, r3, #2, #11240; CHECK-LE-NEXT: rsbs r2, r2, #01241; CHECK-LE-NEXT: bfi r1, r2, #3, #11242; CHECK-LE-NEXT: lsls r2, r1, #311243; CHECK-LE-NEXT: itt ne1244; CHECK-LE-NEXT: ldrne r2, [r0]1245; CHECK-LE-NEXT: vmovne s0, r21246; CHECK-LE-NEXT: lsls r2, r1, #301247; CHECK-LE-NEXT: itt mi1248; CHECK-LE-NEXT: ldrmi r2, [r0, #4]1249; CHECK-LE-NEXT: vmovmi s1, r21250; CHECK-LE-NEXT: lsls r2, r1, #291251; CHECK-LE-NEXT: itt mi1252; CHECK-LE-NEXT: ldrmi r2, [r0, #8]1253; CHECK-LE-NEXT: vmovmi s2, r21254; CHECK-LE-NEXT: lsls r1, r1, #281255; CHECK-LE-NEXT: itt mi1256; CHECK-LE-NEXT: ldrmi r0, [r0, #12]1257; CHECK-LE-NEXT: vmovmi s3, r01258; CHECK-LE-NEXT: add sp, #41259; CHECK-LE-NEXT: bx lr1260;1261; CHECK-BE-LABEL: masked_v4f32_align1_undef:1262; CHECK-BE: @ %bb.0: @ %entry1263; CHECK-BE-NEXT: .pad #41264; CHECK-BE-NEXT: sub sp, #41265; CHECK-BE-NEXT: vrev64.32 q1, q01266; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr1267; CHECK-BE-NEXT: @ implicit-def: $q11268; CHECK-BE-NEXT: vmrs r2, p01269; CHECK-BE-NEXT: ubfx r1, r2, #12, #11270; CHECK-BE-NEXT: rsbs r3, r1, #01271; CHECK-BE-NEXT: movs r1, #01272; CHECK-BE-NEXT: bfi r1, r3, #0, #11273; CHECK-BE-NEXT: ubfx r3, r2, #8, #11274; CHECK-BE-NEXT: rsbs r3, r3, #01275; CHECK-BE-NEXT: bfi r1, r3, #1, #11276; CHECK-BE-NEXT: ubfx r3, r2, #4, #11277; CHECK-BE-NEXT: and r2, r2, #11278; CHECK-BE-NEXT: rsbs r3, r3, #01279; CHECK-BE-NEXT: bfi r1, r3, #2, #11280; CHECK-BE-NEXT: rsbs r2, r2, #01281; CHECK-BE-NEXT: bfi r1, r2, #3, #11282; CHECK-BE-NEXT: lsls r2, r1, #281283; CHECK-BE-NEXT: itt mi1284; CHECK-BE-NEXT: ldrmi r2, [r0]1285; CHECK-BE-NEXT: vmovmi s4, r21286; CHECK-BE-NEXT: lsls r2, r1, #291287; CHECK-BE-NEXT: itt mi1288; CHECK-BE-NEXT: ldrmi r2, [r0, #4]1289; CHECK-BE-NEXT: vmovmi s5, r21290; CHECK-BE-NEXT: lsls r2, r1, #301291; CHECK-BE-NEXT: itt mi1292; CHECK-BE-NEXT: ldrmi r2, [r0, #8]1293; CHECK-BE-NEXT: vmovmi s6, r21294; CHECK-BE-NEXT: lsls r1, r1, #311295; CHECK-BE-NEXT: itt ne1296; CHECK-BE-NEXT: ldrne r0, [r0, #12]1297; CHECK-BE-NEXT: vmovne s7, r01298; CHECK-BE-NEXT: vrev64.32 q0, q11299; CHECK-BE-NEXT: add sp, #41300; CHECK-BE-NEXT: bx lr1301entry:1302 %c = icmp sgt <4 x i32> %a, zeroinitializer1303 %l = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x float> undef)1304 ret <4 x float> %l1305}1306 1307define arm_aapcs_vfpcc <4 x float> @masked_v4f32_align4_other(ptr %dest, <4 x i32> %a, <4 x float> %b) {1308; CHECK-LE-LABEL: masked_v4f32_align4_other:1309; CHECK-LE: @ %bb.0: @ %entry1310; CHECK-LE-NEXT: vpt.s32 gt, q0, zr1311; CHECK-LE-NEXT: vldrwt.u32 q0, [r0]1312; CHECK-LE-NEXT: vpsel q0, q0, q11313; CHECK-LE-NEXT: bx lr1314;1315; CHECK-BE-LABEL: masked_v4f32_align4_other:1316; CHECK-BE: @ %bb.0: @ %entry1317; CHECK-BE-NEXT: vrev64.32 q2, q11318; CHECK-BE-NEXT: vrev64.32 q1, q01319; CHECK-BE-NEXT: vpt.s32 gt, q1, zr1320; CHECK-BE-NEXT: vldrwt.u32 q0, [r0]1321; CHECK-BE-NEXT: vpsel q1, q0, q21322; CHECK-BE-NEXT: vrev64.32 q0, q11323; CHECK-BE-NEXT: bx lr1324entry:1325 %c = icmp sgt <4 x i32> %a, zeroinitializer1326 %l = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %dest, i32 4, <4 x i1> %c, <4 x float> %b)1327 ret <4 x float> %l1328}1329 1330define arm_aapcs_vfpcc ptr @masked_v4f32_preinc(ptr %x, ptr %y, <4 x i32> %a) {1331; CHECK-LE-LABEL: masked_v4f32_preinc:1332; CHECK-LE: @ %bb.0: @ %entry1333; CHECK-LE-NEXT: vpt.s32 gt, q0, zr1334; CHECK-LE-NEXT: vldrwt.u32 q0, [r0, #4]!1335; CHECK-LE-NEXT: vstrw.32 q0, [r1]1336; CHECK-LE-NEXT: bx lr1337;1338; CHECK-BE-LABEL: masked_v4f32_preinc:1339; CHECK-BE: @ %bb.0: @ %entry1340; CHECK-BE-NEXT: vrev64.32 q1, q01341; CHECK-BE-NEXT: vpt.s32 gt, q1, zr1342; CHECK-BE-NEXT: vldrwt.u32 q0, [r0, #4]!1343; CHECK-BE-NEXT: vstrw.32 q0, [r1]1344; CHECK-BE-NEXT: bx lr1345entry:1346 %z = getelementptr inbounds i8, ptr %x, i32 41347 %c = icmp sgt <4 x i32> %a, zeroinitializer1348 %0 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %z, i32 4, <4 x i1> %c, <4 x float> undef)1349 store <4 x float> %0, ptr %y, align 41350 ret ptr %z1351}1352 1353define arm_aapcs_vfpcc ptr @masked_v4f32_postinc(ptr %x, ptr %y, <4 x i32> %a) {1354; CHECK-LE-LABEL: masked_v4f32_postinc:1355; CHECK-LE: @ %bb.0: @ %entry1356; CHECK-LE-NEXT: vpt.s32 gt, q0, zr1357; CHECK-LE-NEXT: vldrwt.u32 q0, [r0], #41358; CHECK-LE-NEXT: vstrw.32 q0, [r1]1359; CHECK-LE-NEXT: bx lr1360;1361; CHECK-BE-LABEL: masked_v4f32_postinc:1362; CHECK-BE: @ %bb.0: @ %entry1363; CHECK-BE-NEXT: vrev64.32 q1, q01364; CHECK-BE-NEXT: vpt.s32 gt, q1, zr1365; CHECK-BE-NEXT: vldrwt.u32 q0, [r0], #41366; CHECK-BE-NEXT: vstrw.32 q0, [r1]1367; CHECK-BE-NEXT: bx lr1368entry:1369 %z = getelementptr inbounds i8, ptr %x, i32 41370 %c = icmp sgt <4 x i32> %a, zeroinitializer1371 %0 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %x, i32 4, <4 x i1> %c, <4 x float> undef)1372 store <4 x float> %0, ptr %y, align 41373 ret ptr %z1374}1375 1376 1377define arm_aapcs_vfpcc <8 x half> @masked_v8f16_align4_zero(ptr %dest, <8 x i16> %a) {1378; CHECK-LE-LABEL: masked_v8f16_align4_zero:1379; CHECK-LE: @ %bb.0: @ %entry1380; CHECK-LE-NEXT: vpt.s16 gt, q0, zr1381; CHECK-LE-NEXT: vldrht.u16 q0, [r0]1382; CHECK-LE-NEXT: bx lr1383;1384; CHECK-BE-LABEL: masked_v8f16_align4_zero:1385; CHECK-BE: @ %bb.0: @ %entry1386; CHECK-BE-NEXT: vrev64.16 q1, q01387; CHECK-BE-NEXT: vpt.s16 gt, q1, zr1388; CHECK-BE-NEXT: vldrht.u16 q1, [r0]1389; CHECK-BE-NEXT: vrev64.16 q0, q11390; CHECK-BE-NEXT: bx lr1391entry:1392 %c = icmp sgt <8 x i16> %a, zeroinitializer1393 %l = call <8 x half> @llvm.masked.load.v8f16.p0(ptr %dest, i32 2, <8 x i1> %c, <8 x half> zeroinitializer)1394 ret <8 x half> %l1395}1396 1397define arm_aapcs_vfpcc <8 x half> @masked_v8f16_align4_undef(ptr %dest, <8 x i16> %a) {1398; CHECK-LE-LABEL: masked_v8f16_align4_undef:1399; CHECK-LE: @ %bb.0: @ %entry1400; CHECK-LE-NEXT: vpt.s16 gt, q0, zr1401; CHECK-LE-NEXT: vldrht.u16 q0, [r0]1402; CHECK-LE-NEXT: bx lr1403;1404; CHECK-BE-LABEL: masked_v8f16_align4_undef:1405; CHECK-BE: @ %bb.0: @ %entry1406; CHECK-BE-NEXT: vrev64.16 q1, q01407; CHECK-BE-NEXT: vpt.s16 gt, q1, zr1408; CHECK-BE-NEXT: vldrht.u16 q1, [r0]1409; CHECK-BE-NEXT: vrev64.16 q0, q11410; CHECK-BE-NEXT: bx lr1411entry:1412 %c = icmp sgt <8 x i16> %a, zeroinitializer1413 %l = call <8 x half> @llvm.masked.load.v8f16.p0(ptr %dest, i32 2, <8 x i1> %c, <8 x half> undef)1414 ret <8 x half> %l1415}1416 1417define arm_aapcs_vfpcc <8 x half> @masked_v8f16_align1_undef(ptr %dest, <8 x i16> %a) {1418; CHECK-LE-LABEL: masked_v8f16_align1_undef:1419; CHECK-LE: @ %bb.0: @ %entry1420; CHECK-LE-NEXT: .pad #361421; CHECK-LE-NEXT: sub sp, #361422; CHECK-LE-NEXT: vcmp.s16 gt, q0, zr1423; CHECK-LE-NEXT: @ implicit-def: $q01424; CHECK-LE-NEXT: vmrs r1, p01425; CHECK-LE-NEXT: and r2, r1, #11426; CHECK-LE-NEXT: rsbs r3, r2, #01427; CHECK-LE-NEXT: movs r2, #01428; CHECK-LE-NEXT: bfi r2, r3, #0, #11429; CHECK-LE-NEXT: ubfx r3, r1, #2, #11430; CHECK-LE-NEXT: rsbs r3, r3, #01431; CHECK-LE-NEXT: bfi r2, r3, #1, #11432; CHECK-LE-NEXT: ubfx r3, r1, #4, #11433; CHECK-LE-NEXT: rsbs r3, r3, #01434; CHECK-LE-NEXT: bfi r2, r3, #2, #11435; CHECK-LE-NEXT: ubfx r3, r1, #6, #11436; CHECK-LE-NEXT: rsbs r3, r3, #01437; CHECK-LE-NEXT: bfi r2, r3, #3, #11438; CHECK-LE-NEXT: ubfx r3, r1, #8, #11439; CHECK-LE-NEXT: rsbs r3, r3, #01440; CHECK-LE-NEXT: bfi r2, r3, #4, #11441; CHECK-LE-NEXT: ubfx r3, r1, #10, #11442; CHECK-LE-NEXT: rsbs r3, r3, #01443; CHECK-LE-NEXT: bfi r2, r3, #5, #11444; CHECK-LE-NEXT: ubfx r3, r1, #12, #11445; CHECK-LE-NEXT: ubfx r1, r1, #14, #11446; CHECK-LE-NEXT: rsbs r3, r3, #01447; CHECK-LE-NEXT: bfi r2, r3, #6, #11448; CHECK-LE-NEXT: rsbs r1, r1, #01449; CHECK-LE-NEXT: bfi r2, r1, #7, #11450; CHECK-LE-NEXT: uxtb r1, r21451; CHECK-LE-NEXT: lsls r2, r2, #311452; CHECK-LE-NEXT: bne .LBB45_91453; CHECK-LE-NEXT: @ %bb.1: @ %else1454; CHECK-LE-NEXT: lsls r2, r1, #301455; CHECK-LE-NEXT: bmi .LBB45_101456; CHECK-LE-NEXT: .LBB45_2: @ %else21457; CHECK-LE-NEXT: lsls r2, r1, #291458; CHECK-LE-NEXT: bmi .LBB45_111459; CHECK-LE-NEXT: .LBB45_3: @ %else51460; CHECK-LE-NEXT: lsls r2, r1, #281461; CHECK-LE-NEXT: bmi .LBB45_121462; CHECK-LE-NEXT: .LBB45_4: @ %else81463; CHECK-LE-NEXT: lsls r2, r1, #271464; CHECK-LE-NEXT: bmi .LBB45_131465; CHECK-LE-NEXT: .LBB45_5: @ %else111466; CHECK-LE-NEXT: lsls r2, r1, #261467; CHECK-LE-NEXT: bmi .LBB45_141468; CHECK-LE-NEXT: .LBB45_6: @ %else141469; CHECK-LE-NEXT: lsls r2, r1, #251470; CHECK-LE-NEXT: bmi .LBB45_151471; CHECK-LE-NEXT: .LBB45_7: @ %else171472; CHECK-LE-NEXT: lsls r1, r1, #241473; CHECK-LE-NEXT: bmi .LBB45_161474; CHECK-LE-NEXT: .LBB45_8: @ %else201475; CHECK-LE-NEXT: add sp, #361476; CHECK-LE-NEXT: bx lr1477; CHECK-LE-NEXT: .LBB45_9: @ %cond.load1478; CHECK-LE-NEXT: ldrh r2, [r0]1479; CHECK-LE-NEXT: strh.w r2, [sp, #28]1480; CHECK-LE-NEXT: vldr.16 s0, [sp, #28]1481; CHECK-LE-NEXT: lsls r2, r1, #301482; CHECK-LE-NEXT: bpl .LBB45_21483; CHECK-LE-NEXT: .LBB45_10: @ %cond.load11484; CHECK-LE-NEXT: ldrh r2, [r0, #2]1485; CHECK-LE-NEXT: strh.w r2, [sp, #24]1486; CHECK-LE-NEXT: vldr.16 s4, [sp, #24]1487; CHECK-LE-NEXT: vins.f16 s0, s41488; CHECK-LE-NEXT: lsls r2, r1, #291489; CHECK-LE-NEXT: bpl .LBB45_31490; CHECK-LE-NEXT: .LBB45_11: @ %cond.load41491; CHECK-LE-NEXT: ldrh r2, [r0, #4]1492; CHECK-LE-NEXT: strh.w r2, [sp, #20]1493; CHECK-LE-NEXT: vldr.16 s4, [sp, #20]1494; CHECK-LE-NEXT: vmov r2, s41495; CHECK-LE-NEXT: vmov.16 q0[2], r21496; CHECK-LE-NEXT: lsls r2, r1, #281497; CHECK-LE-NEXT: bpl .LBB45_41498; CHECK-LE-NEXT: .LBB45_12: @ %cond.load71499; CHECK-LE-NEXT: ldrh r2, [r0, #6]1500; CHECK-LE-NEXT: strh.w r2, [sp, #16]1501; CHECK-LE-NEXT: vldr.16 s4, [sp, #16]1502; CHECK-LE-NEXT: vins.f16 s1, s41503; CHECK-LE-NEXT: lsls r2, r1, #271504; CHECK-LE-NEXT: bpl .LBB45_51505; CHECK-LE-NEXT: .LBB45_13: @ %cond.load101506; CHECK-LE-NEXT: ldrh r2, [r0, #8]1507; CHECK-LE-NEXT: strh.w r2, [sp, #12]1508; CHECK-LE-NEXT: vldr.16 s4, [sp, #12]1509; CHECK-LE-NEXT: vmov r2, s41510; CHECK-LE-NEXT: vmov.16 q0[4], r21511; CHECK-LE-NEXT: lsls r2, r1, #261512; CHECK-LE-NEXT: bpl .LBB45_61513; CHECK-LE-NEXT: .LBB45_14: @ %cond.load131514; CHECK-LE-NEXT: ldrh r2, [r0, #10]1515; CHECK-LE-NEXT: strh.w r2, [sp, #8]1516; CHECK-LE-NEXT: vldr.16 s4, [sp, #8]1517; CHECK-LE-NEXT: vins.f16 s2, s41518; CHECK-LE-NEXT: lsls r2, r1, #251519; CHECK-LE-NEXT: bpl .LBB45_71520; CHECK-LE-NEXT: .LBB45_15: @ %cond.load161521; CHECK-LE-NEXT: ldrh r2, [r0, #12]1522; CHECK-LE-NEXT: strh.w r2, [sp, #4]1523; CHECK-LE-NEXT: vldr.16 s4, [sp, #4]1524; CHECK-LE-NEXT: vmov r2, s41525; CHECK-LE-NEXT: vmov.16 q0[6], r21526; CHECK-LE-NEXT: lsls r1, r1, #241527; CHECK-LE-NEXT: bpl .LBB45_81528; CHECK-LE-NEXT: .LBB45_16: @ %cond.load191529; CHECK-LE-NEXT: ldrh r0, [r0, #14]1530; CHECK-LE-NEXT: strh.w r0, [sp]1531; CHECK-LE-NEXT: vldr.16 s4, [sp]1532; CHECK-LE-NEXT: vins.f16 s3, s41533; CHECK-LE-NEXT: add sp, #361534; CHECK-LE-NEXT: bx lr1535;1536; CHECK-BE-LABEL: masked_v8f16_align1_undef:1537; CHECK-BE: @ %bb.0: @ %entry1538; CHECK-BE-NEXT: .pad #361539; CHECK-BE-NEXT: sub sp, #361540; CHECK-BE-NEXT: vrev64.16 q1, q01541; CHECK-BE-NEXT: vcmp.s16 gt, q1, zr1542; CHECK-BE-NEXT: @ implicit-def: $q11543; CHECK-BE-NEXT: vmrs r1, p01544; CHECK-BE-NEXT: ubfx r2, r1, #14, #11545; CHECK-BE-NEXT: rsbs r3, r2, #01546; CHECK-BE-NEXT: movs r2, #01547; CHECK-BE-NEXT: bfi r2, r3, #0, #11548; CHECK-BE-NEXT: ubfx r3, r1, #12, #11549; CHECK-BE-NEXT: rsbs r3, r3, #01550; CHECK-BE-NEXT: bfi r2, r3, #1, #11551; CHECK-BE-NEXT: ubfx r3, r1, #10, #11552; CHECK-BE-NEXT: rsbs r3, r3, #01553; CHECK-BE-NEXT: bfi r2, r3, #2, #11554; CHECK-BE-NEXT: ubfx r3, r1, #8, #11555; CHECK-BE-NEXT: rsbs r3, r3, #01556; CHECK-BE-NEXT: bfi r2, r3, #3, #11557; CHECK-BE-NEXT: ubfx r3, r1, #6, #11558; CHECK-BE-NEXT: rsbs r3, r3, #01559; CHECK-BE-NEXT: bfi r2, r3, #4, #11560; CHECK-BE-NEXT: ubfx r3, r1, #4, #11561; CHECK-BE-NEXT: rsbs r3, r3, #01562; CHECK-BE-NEXT: bfi r2, r3, #5, #11563; CHECK-BE-NEXT: ubfx r3, r1, #2, #11564; CHECK-BE-NEXT: and r1, r1, #11565; CHECK-BE-NEXT: rsbs r3, r3, #01566; CHECK-BE-NEXT: bfi r2, r3, #6, #11567; CHECK-BE-NEXT: rsbs r1, r1, #01568; CHECK-BE-NEXT: bfi r2, r1, #7, #11569; CHECK-BE-NEXT: uxtb r1, r21570; CHECK-BE-NEXT: lsls r2, r2, #241571; CHECK-BE-NEXT: bmi .LBB45_101572; CHECK-BE-NEXT: @ %bb.1: @ %else1573; CHECK-BE-NEXT: lsls r2, r1, #251574; CHECK-BE-NEXT: bmi .LBB45_111575; CHECK-BE-NEXT: .LBB45_2: @ %else21576; CHECK-BE-NEXT: lsls r2, r1, #261577; CHECK-BE-NEXT: bmi .LBB45_121578; CHECK-BE-NEXT: .LBB45_3: @ %else51579; CHECK-BE-NEXT: lsls r2, r1, #271580; CHECK-BE-NEXT: bmi .LBB45_131581; CHECK-BE-NEXT: .LBB45_4: @ %else81582; CHECK-BE-NEXT: lsls r2, r1, #281583; CHECK-BE-NEXT: bmi .LBB45_141584; CHECK-BE-NEXT: .LBB45_5: @ %else111585; CHECK-BE-NEXT: lsls r2, r1, #291586; CHECK-BE-NEXT: bmi .LBB45_151587; CHECK-BE-NEXT: .LBB45_6: @ %else141588; CHECK-BE-NEXT: lsls r2, r1, #301589; CHECK-BE-NEXT: bmi .LBB45_161590; CHECK-BE-NEXT: .LBB45_7: @ %else171591; CHECK-BE-NEXT: lsls r1, r1, #311592; CHECK-BE-NEXT: beq .LBB45_91593; CHECK-BE-NEXT: .LBB45_8: @ %cond.load191594; CHECK-BE-NEXT: ldrh r0, [r0, #14]1595; CHECK-BE-NEXT: strh.w r0, [sp]1596; CHECK-BE-NEXT: vldr.16 s0, [sp]1597; CHECK-BE-NEXT: vins.f16 s7, s01598; CHECK-BE-NEXT: .LBB45_9: @ %else201599; CHECK-BE-NEXT: vrev64.16 q0, q11600; CHECK-BE-NEXT: add sp, #361601; CHECK-BE-NEXT: bx lr1602; CHECK-BE-NEXT: .LBB45_10: @ %cond.load1603; CHECK-BE-NEXT: ldrh r2, [r0]1604; CHECK-BE-NEXT: strh.w r2, [sp, #28]1605; CHECK-BE-NEXT: vldr.16 s4, [sp, #28]1606; CHECK-BE-NEXT: lsls r2, r1, #251607; CHECK-BE-NEXT: bpl .LBB45_21608; CHECK-BE-NEXT: .LBB45_11: @ %cond.load11609; CHECK-BE-NEXT: ldrh r2, [r0, #2]1610; CHECK-BE-NEXT: strh.w r2, [sp, #24]1611; CHECK-BE-NEXT: vldr.16 s0, [sp, #24]1612; CHECK-BE-NEXT: vins.f16 s4, s01613; CHECK-BE-NEXT: lsls r2, r1, #261614; CHECK-BE-NEXT: bpl .LBB45_31615; CHECK-BE-NEXT: .LBB45_12: @ %cond.load41616; CHECK-BE-NEXT: ldrh r2, [r0, #4]1617; CHECK-BE-NEXT: strh.w r2, [sp, #20]1618; CHECK-BE-NEXT: vldr.16 s0, [sp, #20]1619; CHECK-BE-NEXT: vmov r2, s01620; CHECK-BE-NEXT: vmov.16 q1[2], r21621; CHECK-BE-NEXT: lsls r2, r1, #271622; CHECK-BE-NEXT: bpl .LBB45_41623; CHECK-BE-NEXT: .LBB45_13: @ %cond.load71624; CHECK-BE-NEXT: ldrh r2, [r0, #6]1625; CHECK-BE-NEXT: strh.w r2, [sp, #16]1626; CHECK-BE-NEXT: vldr.16 s0, [sp, #16]1627; CHECK-BE-NEXT: vins.f16 s5, s01628; CHECK-BE-NEXT: lsls r2, r1, #281629; CHECK-BE-NEXT: bpl .LBB45_51630; CHECK-BE-NEXT: .LBB45_14: @ %cond.load101631; CHECK-BE-NEXT: ldrh r2, [r0, #8]1632; CHECK-BE-NEXT: strh.w r2, [sp, #12]1633; CHECK-BE-NEXT: vldr.16 s0, [sp, #12]1634; CHECK-BE-NEXT: vmov r2, s01635; CHECK-BE-NEXT: vmov.16 q1[4], r21636; CHECK-BE-NEXT: lsls r2, r1, #291637; CHECK-BE-NEXT: bpl .LBB45_61638; CHECK-BE-NEXT: .LBB45_15: @ %cond.load131639; CHECK-BE-NEXT: ldrh r2, [r0, #10]1640; CHECK-BE-NEXT: strh.w r2, [sp, #8]1641; CHECK-BE-NEXT: vldr.16 s0, [sp, #8]1642; CHECK-BE-NEXT: vins.f16 s6, s01643; CHECK-BE-NEXT: lsls r2, r1, #301644; CHECK-BE-NEXT: bpl .LBB45_71645; CHECK-BE-NEXT: .LBB45_16: @ %cond.load161646; CHECK-BE-NEXT: ldrh r2, [r0, #12]1647; CHECK-BE-NEXT: strh.w r2, [sp, #4]1648; CHECK-BE-NEXT: vldr.16 s0, [sp, #4]1649; CHECK-BE-NEXT: vmov r2, s01650; CHECK-BE-NEXT: vmov.16 q1[6], r21651; CHECK-BE-NEXT: lsls r1, r1, #311652; CHECK-BE-NEXT: bne .LBB45_81653; CHECK-BE-NEXT: b .LBB45_91654entry:1655 %c = icmp sgt <8 x i16> %a, zeroinitializer1656 %l = call <8 x half> @llvm.masked.load.v8f16.p0(ptr %dest, i32 1, <8 x i1> %c, <8 x half> undef)1657 ret <8 x half> %l1658}1659 1660define arm_aapcs_vfpcc <8 x half> @masked_v8f16_align4_other(ptr %dest, <8 x i16> %a, <8 x half> %b) {1661; CHECK-LE-LABEL: masked_v8f16_align4_other:1662; CHECK-LE: @ %bb.0: @ %entry1663; CHECK-LE-NEXT: vpt.s16 gt, q0, zr1664; CHECK-LE-NEXT: vldrht.u16 q0, [r0]1665; CHECK-LE-NEXT: vpsel q0, q0, q11666; CHECK-LE-NEXT: bx lr1667;1668; CHECK-BE-LABEL: masked_v8f16_align4_other:1669; CHECK-BE: @ %bb.0: @ %entry1670; CHECK-BE-NEXT: vrev64.16 q2, q11671; CHECK-BE-NEXT: vrev64.16 q1, q01672; CHECK-BE-NEXT: vpt.s16 gt, q1, zr1673; CHECK-BE-NEXT: vldrht.u16 q0, [r0]1674; CHECK-BE-NEXT: vpsel q1, q0, q21675; CHECK-BE-NEXT: vrev64.16 q0, q11676; CHECK-BE-NEXT: bx lr1677entry:1678 %c = icmp sgt <8 x i16> %a, zeroinitializer1679 %l = call <8 x half> @llvm.masked.load.v8f16.p0(ptr %dest, i32 2, <8 x i1> %c, <8 x half> %b)1680 ret <8 x half> %l1681}1682 1683define arm_aapcs_vfpcc ptr @masked_v8f16_preinc(ptr %x, ptr %y, <8 x i16> %a) {1684; CHECK-LE-LABEL: masked_v8f16_preinc:1685; CHECK-LE: @ %bb.0: @ %entry1686; CHECK-LE-NEXT: vpt.s16 gt, q0, zr1687; CHECK-LE-NEXT: vldrht.u16 q0, [r0, #4]!1688; CHECK-LE-NEXT: vstrw.32 q0, [r1]1689; CHECK-LE-NEXT: bx lr1690;1691; CHECK-BE-LABEL: masked_v8f16_preinc:1692; CHECK-BE: @ %bb.0: @ %entry1693; CHECK-BE-NEXT: vrev64.16 q1, q01694; CHECK-BE-NEXT: vpt.s16 gt, q1, zr1695; CHECK-BE-NEXT: vldrht.u16 q0, [r0, #4]!1696; CHECK-BE-NEXT: vstrh.16 q0, [r1]1697; CHECK-BE-NEXT: bx lr1698entry:1699 %z = getelementptr inbounds i8, ptr %x, i32 41700 %c = icmp sgt <8 x i16> %a, zeroinitializer1701 %0 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr %z, i32 4, <8 x i1> %c, <8 x half> undef)1702 store <8 x half> %0, ptr %y, align 41703 ret ptr %z1704}1705 1706define arm_aapcs_vfpcc ptr @masked_v8f16_postinc(ptr %x, ptr %y, <8 x i16> %a) {1707; CHECK-LE-LABEL: masked_v8f16_postinc:1708; CHECK-LE: @ %bb.0: @ %entry1709; CHECK-LE-NEXT: vpt.s16 gt, q0, zr1710; CHECK-LE-NEXT: vldrht.u16 q0, [r0], #41711; CHECK-LE-NEXT: vstrw.32 q0, [r1]1712; CHECK-LE-NEXT: bx lr1713;1714; CHECK-BE-LABEL: masked_v8f16_postinc:1715; CHECK-BE: @ %bb.0: @ %entry1716; CHECK-BE-NEXT: vrev64.16 q1, q01717; CHECK-BE-NEXT: vpt.s16 gt, q1, zr1718; CHECK-BE-NEXT: vldrht.u16 q0, [r0], #41719; CHECK-BE-NEXT: vstrh.16 q0, [r1]1720; CHECK-BE-NEXT: bx lr1721entry:1722 %z = getelementptr inbounds i8, ptr %x, i32 41723 %c = icmp sgt <8 x i16> %a, zeroinitializer1724 %0 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr %x, i32 4, <8 x i1> %c, <8 x half> undef)1725 store <8 x half> %0, ptr %y, align 41726 ret ptr %z1727}1728 1729 1730define arm_aapcs_vfpcc <2 x i64> @masked_v2i64_align4_zero(ptr %dest, <2 x i64> %a) {1731; CHECK-LE-LABEL: masked_v2i64_align4_zero:1732; CHECK-LE: @ %bb.0: @ %entry1733; CHECK-LE-NEXT: .save {r7, lr}1734; CHECK-LE-NEXT: push {r7, lr}1735; CHECK-LE-NEXT: .pad #41736; CHECK-LE-NEXT: sub sp, #41737; CHECK-LE-NEXT: vmov r2, r3, d01738; CHECK-LE-NEXT: movs r1, #01739; CHECK-LE-NEXT: vmov r12, lr, d11740; CHECK-LE-NEXT: rsbs r2, r2, #01741; CHECK-LE-NEXT: sbcs.w r2, r1, r31742; CHECK-LE-NEXT: csetm r2, lt1743; CHECK-LE-NEXT: rsbs.w r3, r12, #01744; CHECK-LE-NEXT: sbcs.w r3, r1, lr1745; CHECK-LE-NEXT: bfi r1, r2, #0, #11746; CHECK-LE-NEXT: csetm r2, lt1747; CHECK-LE-NEXT: bfi r1, r2, #1, #11748; CHECK-LE-NEXT: lsls r2, r1, #311749; CHECK-LE-NEXT: beq .LBB49_21750; CHECK-LE-NEXT: @ %bb.1: @ %cond.load1751; CHECK-LE-NEXT: vldr d1, .LCPI49_01752; CHECK-LE-NEXT: vldr d0, [r0]1753; CHECK-LE-NEXT: b .LBB49_31754; CHECK-LE-NEXT: .LBB49_2:1755; CHECK-LE-NEXT: vmov.i32 q0, #0x01756; CHECK-LE-NEXT: .LBB49_3: @ %else1757; CHECK-LE-NEXT: lsls r1, r1, #301758; CHECK-LE-NEXT: it mi1759; CHECK-LE-NEXT: vldrmi d1, [r0, #8]1760; CHECK-LE-NEXT: add sp, #41761; CHECK-LE-NEXT: pop {r7, pc}1762; CHECK-LE-NEXT: .p2align 31763; CHECK-LE-NEXT: @ %bb.4:1764; CHECK-LE-NEXT: .LCPI49_0:1765; CHECK-LE-NEXT: .long 0 @ double 01766; CHECK-LE-NEXT: .long 01767;1768; CHECK-BE-LABEL: masked_v2i64_align4_zero:1769; CHECK-BE: @ %bb.0: @ %entry1770; CHECK-BE-NEXT: .save {r7, lr}1771; CHECK-BE-NEXT: push {r7, lr}1772; CHECK-BE-NEXT: .pad #41773; CHECK-BE-NEXT: sub sp, #41774; CHECK-BE-NEXT: vrev64.32 q1, q01775; CHECK-BE-NEXT: movs r1, #01776; CHECK-BE-NEXT: vmov r2, r3, d31777; CHECK-BE-NEXT: vmov r12, lr, d21778; CHECK-BE-NEXT: rsbs r3, r3, #01779; CHECK-BE-NEXT: sbcs.w r2, r1, r21780; CHECK-BE-NEXT: csetm r2, lt1781; CHECK-BE-NEXT: rsbs.w r3, lr, #01782; CHECK-BE-NEXT: sbcs.w r3, r1, r121783; CHECK-BE-NEXT: bfi r1, r2, #0, #11784; CHECK-BE-NEXT: csetm r2, lt1785; CHECK-BE-NEXT: bfi r1, r2, #1, #11786; CHECK-BE-NEXT: lsls r2, r1, #301787; CHECK-BE-NEXT: bpl .LBB49_21788; CHECK-BE-NEXT: @ %bb.1: @ %cond.load1789; CHECK-BE-NEXT: vldr d1, .LCPI49_01790; CHECK-BE-NEXT: vldr d0, [r0]1791; CHECK-BE-NEXT: b .LBB49_31792; CHECK-BE-NEXT: .LBB49_2:1793; CHECK-BE-NEXT: vmov.i32 q0, #0x01794; CHECK-BE-NEXT: .LBB49_3: @ %else1795; CHECK-BE-NEXT: lsls r1, r1, #311796; CHECK-BE-NEXT: it ne1797; CHECK-BE-NEXT: vldrne d1, [r0, #8]1798; CHECK-BE-NEXT: add sp, #41799; CHECK-BE-NEXT: pop {r7, pc}1800; CHECK-BE-NEXT: .p2align 31801; CHECK-BE-NEXT: @ %bb.4:1802; CHECK-BE-NEXT: .LCPI49_0:1803; CHECK-BE-NEXT: .long 0 @ double 01804; CHECK-BE-NEXT: .long 01805entry:1806 %c = icmp sgt <2 x i64> %a, zeroinitializer1807 %l = call <2 x i64> @llvm.masked.load.v2i64.p0(ptr %dest, i32 8, <2 x i1> %c, <2 x i64> zeroinitializer)1808 ret <2 x i64> %l1809}1810 1811define arm_aapcs_vfpcc <2 x double> @masked_v2f64_align4_zero(ptr %dest, <2 x double> %a, <2 x i64> %b) {1812; CHECK-LE-LABEL: masked_v2f64_align4_zero:1813; CHECK-LE: @ %bb.0: @ %entry1814; CHECK-LE-NEXT: .save {r7, lr}1815; CHECK-LE-NEXT: push {r7, lr}1816; CHECK-LE-NEXT: .pad #41817; CHECK-LE-NEXT: sub sp, #41818; CHECK-LE-NEXT: vmov r2, r3, d21819; CHECK-LE-NEXT: movs r1, #01820; CHECK-LE-NEXT: vmov r12, lr, d31821; CHECK-LE-NEXT: rsbs r2, r2, #01822; CHECK-LE-NEXT: sbcs.w r2, r1, r31823; CHECK-LE-NEXT: csetm r2, lt1824; CHECK-LE-NEXT: rsbs.w r3, r12, #01825; CHECK-LE-NEXT: sbcs.w r3, r1, lr1826; CHECK-LE-NEXT: bfi r1, r2, #0, #11827; CHECK-LE-NEXT: csetm r2, lt1828; CHECK-LE-NEXT: bfi r1, r2, #1, #11829; CHECK-LE-NEXT: lsls r2, r1, #311830; CHECK-LE-NEXT: beq .LBB50_21831; CHECK-LE-NEXT: @ %bb.1: @ %cond.load1832; CHECK-LE-NEXT: vldr d1, .LCPI50_01833; CHECK-LE-NEXT: vldr d0, [r0]1834; CHECK-LE-NEXT: b .LBB50_31835; CHECK-LE-NEXT: .LBB50_2:1836; CHECK-LE-NEXT: vmov.i32 q0, #0x01837; CHECK-LE-NEXT: .LBB50_3: @ %else1838; CHECK-LE-NEXT: lsls r1, r1, #301839; CHECK-LE-NEXT: it mi1840; CHECK-LE-NEXT: vldrmi d1, [r0, #8]1841; CHECK-LE-NEXT: add sp, #41842; CHECK-LE-NEXT: pop {r7, pc}1843; CHECK-LE-NEXT: .p2align 31844; CHECK-LE-NEXT: @ %bb.4:1845; CHECK-LE-NEXT: .LCPI50_0:1846; CHECK-LE-NEXT: .long 0 @ double 01847; CHECK-LE-NEXT: .long 01848;1849; CHECK-BE-LABEL: masked_v2f64_align4_zero:1850; CHECK-BE: @ %bb.0: @ %entry1851; CHECK-BE-NEXT: .save {r7, lr}1852; CHECK-BE-NEXT: push {r7, lr}1853; CHECK-BE-NEXT: .pad #41854; CHECK-BE-NEXT: sub sp, #41855; CHECK-BE-NEXT: vrev64.32 q0, q11856; CHECK-BE-NEXT: movs r1, #01857; CHECK-BE-NEXT: vmov r2, r3, d11858; CHECK-BE-NEXT: vmov r12, lr, d01859; CHECK-BE-NEXT: rsbs r3, r3, #01860; CHECK-BE-NEXT: sbcs.w r2, r1, r21861; CHECK-BE-NEXT: csetm r2, lt1862; CHECK-BE-NEXT: rsbs.w r3, lr, #01863; CHECK-BE-NEXT: sbcs.w r3, r1, r121864; CHECK-BE-NEXT: bfi r1, r2, #0, #11865; CHECK-BE-NEXT: csetm r2, lt1866; CHECK-BE-NEXT: bfi r1, r2, #1, #11867; CHECK-BE-NEXT: lsls r2, r1, #301868; CHECK-BE-NEXT: bpl .LBB50_21869; CHECK-BE-NEXT: @ %bb.1: @ %cond.load1870; CHECK-BE-NEXT: vldr d1, .LCPI50_01871; CHECK-BE-NEXT: vldr d0, [r0]1872; CHECK-BE-NEXT: b .LBB50_31873; CHECK-BE-NEXT: .LBB50_2:1874; CHECK-BE-NEXT: vmov.i32 q0, #0x01875; CHECK-BE-NEXT: .LBB50_3: @ %else1876; CHECK-BE-NEXT: lsls r1, r1, #311877; CHECK-BE-NEXT: it ne1878; CHECK-BE-NEXT: vldrne d1, [r0, #8]1879; CHECK-BE-NEXT: add sp, #41880; CHECK-BE-NEXT: pop {r7, pc}1881; CHECK-BE-NEXT: .p2align 31882; CHECK-BE-NEXT: @ %bb.4:1883; CHECK-BE-NEXT: .LCPI50_0:1884; CHECK-BE-NEXT: .long 0 @ double 01885; CHECK-BE-NEXT: .long 01886entry:1887 %c = icmp sgt <2 x i64> %b, zeroinitializer1888 %l = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %dest, i32 8, <2 x i1> %c, <2 x double> zeroinitializer)1889 ret <2 x double> %l1890}1891 1892define arm_aapcs_vfpcc <4 x i16> @anyext_v4i16(ptr %dest, <4 x i32> %a) {1893; CHECK-LE-LABEL: anyext_v4i16:1894; CHECK-LE: @ %bb.0: @ %entry1895; CHECK-LE-NEXT: vpt.s32 gt, q0, zr1896; CHECK-LE-NEXT: vldrht.u32 q0, [r0]1897; CHECK-LE-NEXT: bx lr1898;1899; CHECK-BE-LABEL: anyext_v4i16:1900; CHECK-BE: @ %bb.0: @ %entry1901; CHECK-BE-NEXT: vrev64.32 q1, q01902; CHECK-BE-NEXT: vpt.s32 gt, q1, zr1903; CHECK-BE-NEXT: vldrht.u32 q1, [r0]1904; CHECK-BE-NEXT: vrev64.32 q0, q11905; CHECK-BE-NEXT: bx lr1906entry:1907 %c = icmp sgt <4 x i32> %a, zeroinitializer1908 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 2, <4 x i1> %c, <4 x i16> zeroinitializer)1909 ret <4 x i16> %l1910}1911 1912define arm_aapcs_vfpcc <4 x i16> @anyext_v4i16_align1(ptr %dest, <4 x i32> %a) {1913; CHECK-LE-LABEL: anyext_v4i16_align1:1914; CHECK-LE: @ %bb.0: @ %entry1915; CHECK-LE-NEXT: .pad #41916; CHECK-LE-NEXT: sub sp, #41917; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr1918; CHECK-LE-NEXT: mov.w r12, #01919; CHECK-LE-NEXT: vmrs r3, p01920; CHECK-LE-NEXT: and r1, r3, #11921; CHECK-LE-NEXT: rsbs r2, r1, #01922; CHECK-LE-NEXT: movs r1, #01923; CHECK-LE-NEXT: bfi r1, r2, #0, #11924; CHECK-LE-NEXT: ubfx r2, r3, #4, #11925; CHECK-LE-NEXT: rsbs r2, r2, #01926; CHECK-LE-NEXT: bfi r1, r2, #1, #11927; CHECK-LE-NEXT: ubfx r2, r3, #8, #11928; CHECK-LE-NEXT: rsbs r2, r2, #01929; CHECK-LE-NEXT: bfi r1, r2, #2, #11930; CHECK-LE-NEXT: ubfx r2, r3, #12, #11931; CHECK-LE-NEXT: rsbs r2, r2, #01932; CHECK-LE-NEXT: bfi r1, r2, #3, #11933; CHECK-LE-NEXT: lsls r2, r1, #311934; CHECK-LE-NEXT: beq .LBB52_21935; CHECK-LE-NEXT: @ %bb.1: @ %cond.load1936; CHECK-LE-NEXT: ldrh r2, [r0]1937; CHECK-LE-NEXT: vdup.32 q0, r121938; CHECK-LE-NEXT: vmov.32 q0[0], r21939; CHECK-LE-NEXT: b .LBB52_31940; CHECK-LE-NEXT: .LBB52_2:1941; CHECK-LE-NEXT: vmov.i32 q0, #0x01942; CHECK-LE-NEXT: .LBB52_3: @ %else1943; CHECK-LE-NEXT: lsls r2, r1, #301944; CHECK-LE-NEXT: itt mi1945; CHECK-LE-NEXT: ldrhmi r2, [r0, #2]1946; CHECK-LE-NEXT: vmovmi.32 q0[1], r21947; CHECK-LE-NEXT: lsls r2, r1, #291948; CHECK-LE-NEXT: itt mi1949; CHECK-LE-NEXT: ldrhmi r2, [r0, #4]1950; CHECK-LE-NEXT: vmovmi.32 q0[2], r21951; CHECK-LE-NEXT: lsls r1, r1, #281952; CHECK-LE-NEXT: itt mi1953; CHECK-LE-NEXT: ldrhmi r0, [r0, #6]1954; CHECK-LE-NEXT: vmovmi.32 q0[3], r01955; CHECK-LE-NEXT: add sp, #41956; CHECK-LE-NEXT: bx lr1957;1958; CHECK-BE-LABEL: anyext_v4i16_align1:1959; CHECK-BE: @ %bb.0: @ %entry1960; CHECK-BE-NEXT: .pad #41961; CHECK-BE-NEXT: sub sp, #41962; CHECK-BE-NEXT: vrev64.32 q1, q01963; CHECK-BE-NEXT: mov.w r12, #01964; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr1965; CHECK-BE-NEXT: vmrs r3, p01966; CHECK-BE-NEXT: ubfx r1, r3, #12, #11967; CHECK-BE-NEXT: rsbs r2, r1, #01968; CHECK-BE-NEXT: movs r1, #01969; CHECK-BE-NEXT: bfi r1, r2, #0, #11970; CHECK-BE-NEXT: ubfx r2, r3, #8, #11971; CHECK-BE-NEXT: rsbs r2, r2, #01972; CHECK-BE-NEXT: bfi r1, r2, #1, #11973; CHECK-BE-NEXT: ubfx r2, r3, #4, #11974; CHECK-BE-NEXT: rsbs r2, r2, #01975; CHECK-BE-NEXT: bfi r1, r2, #2, #11976; CHECK-BE-NEXT: and r2, r3, #11977; CHECK-BE-NEXT: rsbs r2, r2, #01978; CHECK-BE-NEXT: bfi r1, r2, #3, #11979; CHECK-BE-NEXT: lsls r2, r1, #281980; CHECK-BE-NEXT: bpl .LBB52_21981; CHECK-BE-NEXT: @ %bb.1: @ %cond.load1982; CHECK-BE-NEXT: ldrh r2, [r0]1983; CHECK-BE-NEXT: vdup.32 q1, r121984; CHECK-BE-NEXT: vmov.32 q1[0], r21985; CHECK-BE-NEXT: b .LBB52_31986; CHECK-BE-NEXT: .LBB52_2:1987; CHECK-BE-NEXT: vmov.i32 q1, #0x01988; CHECK-BE-NEXT: .LBB52_3: @ %else1989; CHECK-BE-NEXT: lsls r2, r1, #291990; CHECK-BE-NEXT: itt mi1991; CHECK-BE-NEXT: ldrhmi r2, [r0, #2]1992; CHECK-BE-NEXT: vmovmi.32 q1[1], r21993; CHECK-BE-NEXT: lsls r2, r1, #301994; CHECK-BE-NEXT: itt mi1995; CHECK-BE-NEXT: ldrhmi r2, [r0, #4]1996; CHECK-BE-NEXT: vmovmi.32 q1[2], r21997; CHECK-BE-NEXT: lsls r1, r1, #311998; CHECK-BE-NEXT: itt ne1999; CHECK-BE-NEXT: ldrhne r0, [r0, #6]2000; CHECK-BE-NEXT: vmovne.32 q1[3], r02001; CHECK-BE-NEXT: vrev64.32 q0, q12002; CHECK-BE-NEXT: add sp, #42003; CHECK-BE-NEXT: bx lr2004entry:2005 %c = icmp sgt <4 x i32> %a, zeroinitializer2006 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x i16> zeroinitializer)2007 ret <4 x i16> %l2008}2009 2010define arm_aapcs_vfpcc <4 x i8> @anyext_v4i8(ptr %dest, <4 x i32> %a) {2011; CHECK-LE-LABEL: anyext_v4i8:2012; CHECK-LE: @ %bb.0: @ %entry2013; CHECK-LE-NEXT: vpt.s32 gt, q0, zr2014; CHECK-LE-NEXT: vldrbt.u32 q0, [r0]2015; CHECK-LE-NEXT: bx lr2016;2017; CHECK-BE-LABEL: anyext_v4i8:2018; CHECK-BE: @ %bb.0: @ %entry2019; CHECK-BE-NEXT: vrev64.32 q1, q02020; CHECK-BE-NEXT: vpt.s32 gt, q1, zr2021; CHECK-BE-NEXT: vldrbt.u32 q1, [r0]2022; CHECK-BE-NEXT: vrev64.32 q0, q12023; CHECK-BE-NEXT: bx lr2024entry:2025 %c = icmp sgt <4 x i32> %a, zeroinitializer2026 %l = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %dest, i32 1, <4 x i1> %c, <4 x i8> zeroinitializer)2027 ret <4 x i8> %l2028}2029 2030define arm_aapcs_vfpcc <8 x i8> @anyext_v8i8(ptr %dest, <8 x i16> %a) {2031; CHECK-LE-LABEL: anyext_v8i8:2032; CHECK-LE: @ %bb.0: @ %entry2033; CHECK-LE-NEXT: vpt.s16 gt, q0, zr2034; CHECK-LE-NEXT: vldrbt.u16 q0, [r0]2035; CHECK-LE-NEXT: bx lr2036;2037; CHECK-BE-LABEL: anyext_v8i8:2038; CHECK-BE: @ %bb.0: @ %entry2039; CHECK-BE-NEXT: vrev64.16 q1, q02040; CHECK-BE-NEXT: vpt.s16 gt, q1, zr2041; CHECK-BE-NEXT: vldrbt.u16 q1, [r0]2042; CHECK-BE-NEXT: vrev64.16 q0, q12043; CHECK-BE-NEXT: bx lr2044entry:2045 %c = icmp sgt <8 x i16> %a, zeroinitializer2046 %l = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %dest, i32 1, <8 x i1> %c, <8 x i8> zeroinitializer)2047 ret <8 x i8> %l2048}2049 2050define arm_aapcs_vfpcc <4 x i32> @multi_user_zext(ptr %dest, <4 x i32> %a) {2051; CHECK-LE-LABEL: multi_user_zext:2052; CHECK-LE: @ %bb.0: @ %entry2053; CHECK-LE-NEXT: .save {r7, lr}2054; CHECK-LE-NEXT: push {r7, lr}2055; CHECK-LE-NEXT: .vsave {d8, d9}2056; CHECK-LE-NEXT: vpush {d8, d9}2057; CHECK-LE-NEXT: vpt.s32 gt, q0, zr2058; CHECK-LE-NEXT: vldrht.u32 q4, [r0]2059; CHECK-LE-NEXT: vmov r0, r1, d82060; CHECK-LE-NEXT: vmov r2, r3, d92061; CHECK-LE-NEXT: bl foo2062; CHECK-LE-NEXT: vmov q0, q42063; CHECK-LE-NEXT: vpop {d8, d9}2064; CHECK-LE-NEXT: pop {r7, pc}2065;2066; CHECK-BE-LABEL: multi_user_zext:2067; CHECK-BE: @ %bb.0: @ %entry2068; CHECK-BE-NEXT: .save {r7, lr}2069; CHECK-BE-NEXT: push {r7, lr}2070; CHECK-BE-NEXT: .vsave {d8, d9}2071; CHECK-BE-NEXT: vpush {d8, d9}2072; CHECK-BE-NEXT: vrev64.32 q1, q02073; CHECK-BE-NEXT: vpt.s32 gt, q1, zr2074; CHECK-BE-NEXT: vldrht.u32 q0, [r0]2075; CHECK-BE-NEXT: vrev64.32 q4, q02076; CHECK-BE-NEXT: vmov r1, r0, d82077; CHECK-BE-NEXT: vmov r3, r2, d92078; CHECK-BE-NEXT: bl foo2079; CHECK-BE-NEXT: vmov q0, q42080; CHECK-BE-NEXT: vpop {d8, d9}2081; CHECK-BE-NEXT: pop {r7, pc}2082entry:2083 %c = icmp sgt <4 x i32> %a, zeroinitializer2084 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 2, <4 x i1> %c, <4 x i16> zeroinitializer)2085 call void @foo(<4 x i16> %l)2086 %ext = zext <4 x i16> %l to <4 x i32>2087 ret <4 x i32> %ext2088}2089 2090define arm_aapcs_vfpcc <4 x i32> @multi_user_sext(ptr %dest, <4 x i32> %a) {2091; CHECK-LE-LABEL: multi_user_sext:2092; CHECK-LE: @ %bb.0: @ %entry2093; CHECK-LE-NEXT: .save {r7, lr}2094; CHECK-LE-NEXT: push {r7, lr}2095; CHECK-LE-NEXT: .vsave {d8, d9}2096; CHECK-LE-NEXT: vpush {d8, d9}2097; CHECK-LE-NEXT: vpt.s32 gt, q0, zr2098; CHECK-LE-NEXT: vldrht.u32 q4, [r0]2099; CHECK-LE-NEXT: vmov r0, r1, d82100; CHECK-LE-NEXT: vmov r2, r3, d92101; CHECK-LE-NEXT: bl foo2102; CHECK-LE-NEXT: vmovlb.s16 q0, q42103; CHECK-LE-NEXT: vpop {d8, d9}2104; CHECK-LE-NEXT: pop {r7, pc}2105;2106; CHECK-BE-LABEL: multi_user_sext:2107; CHECK-BE: @ %bb.0: @ %entry2108; CHECK-BE-NEXT: .save {r7, lr}2109; CHECK-BE-NEXT: push {r7, lr}2110; CHECK-BE-NEXT: .vsave {d8, d9}2111; CHECK-BE-NEXT: vpush {d8, d9}2112; CHECK-BE-NEXT: vrev64.32 q1, q02113; CHECK-BE-NEXT: vpt.s32 gt, q1, zr2114; CHECK-BE-NEXT: vldrht.u32 q4, [r0]2115; CHECK-BE-NEXT: vrev64.32 q0, q42116; CHECK-BE-NEXT: vmov r1, r0, d02117; CHECK-BE-NEXT: vmov r3, r2, d12118; CHECK-BE-NEXT: bl foo2119; CHECK-BE-NEXT: vmovlb.s16 q1, q42120; CHECK-BE-NEXT: vrev64.32 q0, q12121; CHECK-BE-NEXT: vpop {d8, d9}2122; CHECK-BE-NEXT: pop {r7, pc}2123entry:2124 %c = icmp sgt <4 x i32> %a, zeroinitializer2125 %l = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %dest, i32 2, <4 x i1> %c, <4 x i16> zeroinitializer)2126 call void @foo(<4 x i16> %l)2127 %ext = sext <4 x i16> %l to <4 x i32>2128 ret <4 x i32> %ext2129}2130 2131declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32, <4 x i1>, <4 x i16>)2132declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32, <4 x i1>, <4 x i32>)2133declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32, <8 x i1>, <8 x i16>)2134declare <4 x i8> @llvm.masked.load.v4i8.p0(ptr, i32, <4 x i1>, <4 x i8>)2135declare <8 x i8> @llvm.masked.load.v8i8.p0(ptr, i32, <8 x i1>, <8 x i8>)2136declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr, i32, <16 x i1>, <16 x i8>)2137declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32, <4 x i1>, <4 x float>)2138declare <8 x half> @llvm.masked.load.v8f16.p0(ptr, i32, <8 x i1>, <8 x half>)2139declare <2 x i64> @llvm.masked.load.v2i64.p0(ptr, i32, <2 x i1>, <2 x i64>)2140declare <2 x double> @llvm.masked.load.v2f64.p0(ptr, i32, <2 x i1>, <2 x double>)2141declare void @foo(<4 x i16>)2142