1576 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-LE3; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-BE4 5define arm_aapcs_vfpcc void @masked_v4i32(ptr %dest, <4 x i32> %a) {6; CHECK-LE-LABEL: masked_v4i32:7; CHECK-LE: @ %bb.0: @ %entry8; CHECK-LE-NEXT: vpt.s32 gt, q0, zr9; CHECK-LE-NEXT: vstrwt.32 q0, [r0]10; CHECK-LE-NEXT: bx lr11;12; CHECK-BE-LABEL: masked_v4i32:13; CHECK-BE: @ %bb.0: @ %entry14; CHECK-BE-NEXT: vrev64.32 q1, q015; CHECK-BE-NEXT: vpt.s32 gt, q1, zr16; CHECK-BE-NEXT: vstrwt.32 q1, [r0]17; CHECK-BE-NEXT: bx lr18entry:19 %c = icmp sgt <4 x i32> %a, zeroinitializer20 call void @llvm.masked.store.v4i32.p0(<4 x i32> %a, ptr %dest, i32 4, <4 x i1> %c)21 ret void22}23 24define arm_aapcs_vfpcc void @masked_v4i32_align1(ptr %dest, <4 x i32> %a) {25; CHECK-LE-LABEL: masked_v4i32_align1:26; CHECK-LE: @ %bb.0: @ %entry27; CHECK-LE-NEXT: .pad #428; CHECK-LE-NEXT: sub sp, #429; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr30; CHECK-LE-NEXT: vmrs r2, p031; CHECK-LE-NEXT: and r1, r2, #132; CHECK-LE-NEXT: rsbs r3, r1, #033; CHECK-LE-NEXT: movs r1, #034; CHECK-LE-NEXT: bfi r1, r3, #0, #135; CHECK-LE-NEXT: ubfx r3, r2, #4, #136; CHECK-LE-NEXT: rsbs r3, r3, #037; CHECK-LE-NEXT: bfi r1, r3, #1, #138; CHECK-LE-NEXT: ubfx r3, r2, #8, #139; CHECK-LE-NEXT: ubfx r2, r2, #12, #140; CHECK-LE-NEXT: rsbs r3, r3, #041; CHECK-LE-NEXT: bfi r1, r3, #2, #142; CHECK-LE-NEXT: rsbs r2, r2, #043; CHECK-LE-NEXT: bfi r1, r2, #3, #144; CHECK-LE-NEXT: lsls r2, r1, #3145; CHECK-LE-NEXT: itt ne46; CHECK-LE-NEXT: vmovne r2, s047; CHECK-LE-NEXT: strne r2, [r0]48; CHECK-LE-NEXT: lsls r2, r1, #3049; CHECK-LE-NEXT: itt mi50; CHECK-LE-NEXT: vmovmi r2, s151; CHECK-LE-NEXT: strmi r2, [r0, #4]52; CHECK-LE-NEXT: lsls r2, r1, #2953; CHECK-LE-NEXT: itt mi54; CHECK-LE-NEXT: vmovmi r2, s255; CHECK-LE-NEXT: strmi r2, [r0, #8]56; CHECK-LE-NEXT: lsls r1, r1, #2857; CHECK-LE-NEXT: itt mi58; CHECK-LE-NEXT: vmovmi r1, s359; CHECK-LE-NEXT: strmi r1, [r0, #12]60; CHECK-LE-NEXT: add sp, #461; CHECK-LE-NEXT: bx lr62;63; CHECK-BE-LABEL: masked_v4i32_align1:64; CHECK-BE: @ %bb.0: @ %entry65; CHECK-BE-NEXT: .pad #466; CHECK-BE-NEXT: sub sp, #467; CHECK-BE-NEXT: vrev64.32 q1, q068; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr69; CHECK-BE-NEXT: vmrs r2, p070; CHECK-BE-NEXT: ubfx r1, r2, #12, #171; CHECK-BE-NEXT: rsbs r3, r1, #072; CHECK-BE-NEXT: movs r1, #073; CHECK-BE-NEXT: bfi r1, r3, #0, #174; CHECK-BE-NEXT: ubfx r3, r2, #8, #175; CHECK-BE-NEXT: rsbs r3, r3, #076; CHECK-BE-NEXT: bfi r1, r3, #1, #177; CHECK-BE-NEXT: ubfx r3, r2, #4, #178; CHECK-BE-NEXT: and r2, r2, #179; CHECK-BE-NEXT: rsbs r3, r3, #080; CHECK-BE-NEXT: bfi r1, r3, #2, #181; CHECK-BE-NEXT: rsbs r2, r2, #082; CHECK-BE-NEXT: bfi r1, r2, #3, #183; CHECK-BE-NEXT: lsls r2, r1, #2884; CHECK-BE-NEXT: itt mi85; CHECK-BE-NEXT: vmovmi r2, s486; CHECK-BE-NEXT: strmi r2, [r0]87; CHECK-BE-NEXT: lsls r2, r1, #2988; CHECK-BE-NEXT: itt mi89; CHECK-BE-NEXT: vmovmi r2, s590; CHECK-BE-NEXT: strmi r2, [r0, #4]91; CHECK-BE-NEXT: lsls r2, r1, #3092; CHECK-BE-NEXT: itt mi93; CHECK-BE-NEXT: vmovmi r2, s694; CHECK-BE-NEXT: strmi r2, [r0, #8]95; CHECK-BE-NEXT: lsls r1, r1, #3196; CHECK-BE-NEXT: itt ne97; CHECK-BE-NEXT: vmovne r1, s798; CHECK-BE-NEXT: strne r1, [r0, #12]99; CHECK-BE-NEXT: add sp, #4100; CHECK-BE-NEXT: bx lr101entry:102 %c = icmp sgt <4 x i32> %a, zeroinitializer103 call void @llvm.masked.store.v4i32.p0(<4 x i32> %a, ptr %dest, i32 1, <4 x i1> %c)104 ret void105}106 107define ptr @masked_v4i32_pre(ptr %y, ptr %x, <4 x i32> %a) {108; CHECK-LE-LABEL: masked_v4i32_pre:109; CHECK-LE: @ %bb.0: @ %entry110; CHECK-LE-NEXT: vldr d1, [sp]111; CHECK-LE-NEXT: vmov d0, r2, r3112; CHECK-LE-NEXT: vldrw.u32 q1, [r1]113; CHECK-LE-NEXT: vpt.s32 gt, q0, zr114; CHECK-LE-NEXT: vstrwt.32 q1, [r0, #4]!115; CHECK-LE-NEXT: bx lr116;117; CHECK-BE-LABEL: masked_v4i32_pre:118; CHECK-BE: @ %bb.0: @ %entry119; CHECK-BE-NEXT: vldr d1, [sp]120; CHECK-BE-NEXT: vmov d0, r3, r2121; CHECK-BE-NEXT: vldrw.u32 q1, [r1]122; CHECK-BE-NEXT: vrev64.32 q2, q0123; CHECK-BE-NEXT: vpt.s32 gt, q2, zr124; CHECK-BE-NEXT: vstrwt.32 q1, [r0, #4]!125; CHECK-BE-NEXT: bx lr126entry:127 %z = getelementptr inbounds i8, ptr %y, i32 4128 %0 = load <4 x i32>, ptr %x, align 4129 %c = icmp sgt <4 x i32> %a, zeroinitializer130 call void @llvm.masked.store.v4i32.p0(<4 x i32> %0, ptr %z, i32 4, <4 x i1> %c)131 ret ptr %z132}133 134define ptr @masked_v4i32_post(ptr %y, ptr %x, <4 x i32> %a) {135; CHECK-LE-LABEL: masked_v4i32_post:136; CHECK-LE: @ %bb.0: @ %entry137; CHECK-LE-NEXT: vldr d1, [sp]138; CHECK-LE-NEXT: vmov d0, r2, r3139; CHECK-LE-NEXT: vldrw.u32 q1, [r1]140; CHECK-LE-NEXT: vpt.s32 gt, q0, zr141; CHECK-LE-NEXT: vstrwt.32 q1, [r0], #4142; CHECK-LE-NEXT: bx lr143;144; CHECK-BE-LABEL: masked_v4i32_post:145; CHECK-BE: @ %bb.0: @ %entry146; CHECK-BE-NEXT: vldr d1, [sp]147; CHECK-BE-NEXT: vmov d0, r3, r2148; CHECK-BE-NEXT: vldrw.u32 q1, [r1]149; CHECK-BE-NEXT: vrev64.32 q2, q0150; CHECK-BE-NEXT: vpt.s32 gt, q2, zr151; CHECK-BE-NEXT: vstrwt.32 q1, [r0], #4152; CHECK-BE-NEXT: bx lr153entry:154 %z = getelementptr inbounds i8, ptr %y, i32 4155 %0 = load <4 x i32>, ptr %x, align 4156 %c = icmp sgt <4 x i32> %a, zeroinitializer157 call void @llvm.masked.store.v4i32.p0(<4 x i32> %0, ptr %y, i32 4, <4 x i1> %c)158 ret ptr %z159}160 161 162define arm_aapcs_vfpcc void @masked_v8i16(ptr %dest, <8 x i16> %a) {163; CHECK-LE-LABEL: masked_v8i16:164; CHECK-LE: @ %bb.0: @ %entry165; CHECK-LE-NEXT: vpt.s16 gt, q0, zr166; CHECK-LE-NEXT: vstrht.16 q0, [r0]167; CHECK-LE-NEXT: bx lr168;169; CHECK-BE-LABEL: masked_v8i16:170; CHECK-BE: @ %bb.0: @ %entry171; CHECK-BE-NEXT: vrev64.16 q1, q0172; CHECK-BE-NEXT: vpt.s16 gt, q1, zr173; CHECK-BE-NEXT: vstrht.16 q1, [r0]174; CHECK-BE-NEXT: bx lr175entry:176 %c = icmp sgt <8 x i16> %a, zeroinitializer177 call void @llvm.masked.store.v8i16.p0(<8 x i16> %a, ptr %dest, i32 2, <8 x i1> %c)178 ret void179}180 181define arm_aapcs_vfpcc void @masked_v8i16_align1(ptr %dest, <8 x i16> %a) {182; CHECK-LE-LABEL: masked_v8i16_align1:183; CHECK-LE: @ %bb.0: @ %entry184; CHECK-LE-NEXT: .pad #4185; CHECK-LE-NEXT: sub sp, #4186; CHECK-LE-NEXT: vcmp.s16 gt, q0, zr187; CHECK-LE-NEXT: vmrs r1, p0188; CHECK-LE-NEXT: and r2, r1, #1189; CHECK-LE-NEXT: rsbs r3, r2, #0190; CHECK-LE-NEXT: movs r2, #0191; CHECK-LE-NEXT: bfi r2, r3, #0, #1192; CHECK-LE-NEXT: ubfx r3, r1, #2, #1193; CHECK-LE-NEXT: rsbs r3, r3, #0194; CHECK-LE-NEXT: bfi r2, r3, #1, #1195; CHECK-LE-NEXT: ubfx r3, r1, #4, #1196; CHECK-LE-NEXT: rsbs r3, r3, #0197; CHECK-LE-NEXT: bfi r2, r3, #2, #1198; CHECK-LE-NEXT: ubfx r3, r1, #6, #1199; CHECK-LE-NEXT: rsbs r3, r3, #0200; CHECK-LE-NEXT: bfi r2, r3, #3, #1201; CHECK-LE-NEXT: ubfx r3, r1, #8, #1202; CHECK-LE-NEXT: rsbs r3, r3, #0203; CHECK-LE-NEXT: bfi r2, r3, #4, #1204; CHECK-LE-NEXT: ubfx r3, r1, #10, #1205; CHECK-LE-NEXT: rsbs r3, r3, #0206; CHECK-LE-NEXT: bfi r2, r3, #5, #1207; CHECK-LE-NEXT: ubfx r3, r1, #12, #1208; CHECK-LE-NEXT: ubfx r1, r1, #14, #1209; CHECK-LE-NEXT: rsbs r3, r3, #0210; CHECK-LE-NEXT: bfi r2, r3, #6, #1211; CHECK-LE-NEXT: rsbs r1, r1, #0212; CHECK-LE-NEXT: bfi r2, r1, #7, #1213; CHECK-LE-NEXT: uxtb r1, r2214; CHECK-LE-NEXT: lsls r2, r2, #31215; CHECK-LE-NEXT: itt ne216; CHECK-LE-NEXT: vmovne.u16 r2, q0[0]217; CHECK-LE-NEXT: strhne r2, [r0]218; CHECK-LE-NEXT: lsls r2, r1, #30219; CHECK-LE-NEXT: itt mi220; CHECK-LE-NEXT: vmovmi.u16 r2, q0[1]221; CHECK-LE-NEXT: strhmi r2, [r0, #2]222; CHECK-LE-NEXT: lsls r2, r1, #29223; CHECK-LE-NEXT: itt mi224; CHECK-LE-NEXT: vmovmi.u16 r2, q0[2]225; CHECK-LE-NEXT: strhmi r2, [r0, #4]226; CHECK-LE-NEXT: lsls r2, r1, #28227; CHECK-LE-NEXT: itt mi228; CHECK-LE-NEXT: vmovmi.u16 r2, q0[3]229; CHECK-LE-NEXT: strhmi r2, [r0, #6]230; CHECK-LE-NEXT: lsls r2, r1, #27231; CHECK-LE-NEXT: itt mi232; CHECK-LE-NEXT: vmovmi.u16 r2, q0[4]233; CHECK-LE-NEXT: strhmi r2, [r0, #8]234; CHECK-LE-NEXT: lsls r2, r1, #26235; CHECK-LE-NEXT: itt mi236; CHECK-LE-NEXT: vmovmi.u16 r2, q0[5]237; CHECK-LE-NEXT: strhmi r2, [r0, #10]238; CHECK-LE-NEXT: lsls r2, r1, #25239; CHECK-LE-NEXT: itt mi240; CHECK-LE-NEXT: vmovmi.u16 r2, q0[6]241; CHECK-LE-NEXT: strhmi r2, [r0, #12]242; CHECK-LE-NEXT: lsls r1, r1, #24243; CHECK-LE-NEXT: itt mi244; CHECK-LE-NEXT: vmovmi.u16 r1, q0[7]245; CHECK-LE-NEXT: strhmi r1, [r0, #14]246; CHECK-LE-NEXT: add sp, #4247; CHECK-LE-NEXT: bx lr248;249; CHECK-BE-LABEL: masked_v8i16_align1:250; CHECK-BE: @ %bb.0: @ %entry251; CHECK-BE-NEXT: .pad #4252; CHECK-BE-NEXT: sub sp, #4253; CHECK-BE-NEXT: vrev64.16 q1, q0254; CHECK-BE-NEXT: vcmp.s16 gt, q1, zr255; CHECK-BE-NEXT: vmrs r1, p0256; CHECK-BE-NEXT: ubfx r2, r1, #14, #1257; CHECK-BE-NEXT: rsbs r3, r2, #0258; CHECK-BE-NEXT: movs r2, #0259; CHECK-BE-NEXT: bfi r2, r3, #0, #1260; CHECK-BE-NEXT: ubfx r3, r1, #12, #1261; CHECK-BE-NEXT: rsbs r3, r3, #0262; CHECK-BE-NEXT: bfi r2, r3, #1, #1263; CHECK-BE-NEXT: ubfx r3, r1, #10, #1264; CHECK-BE-NEXT: rsbs r3, r3, #0265; CHECK-BE-NEXT: bfi r2, r3, #2, #1266; CHECK-BE-NEXT: ubfx r3, r1, #8, #1267; CHECK-BE-NEXT: rsbs r3, r3, #0268; CHECK-BE-NEXT: bfi r2, r3, #3, #1269; CHECK-BE-NEXT: ubfx r3, r1, #6, #1270; CHECK-BE-NEXT: rsbs r3, r3, #0271; CHECK-BE-NEXT: bfi r2, r3, #4, #1272; CHECK-BE-NEXT: ubfx r3, r1, #4, #1273; CHECK-BE-NEXT: rsbs r3, r3, #0274; CHECK-BE-NEXT: bfi r2, r3, #5, #1275; CHECK-BE-NEXT: ubfx r3, r1, #2, #1276; CHECK-BE-NEXT: and r1, r1, #1277; CHECK-BE-NEXT: rsbs r3, r3, #0278; CHECK-BE-NEXT: bfi r2, r3, #6, #1279; CHECK-BE-NEXT: rsbs r1, r1, #0280; CHECK-BE-NEXT: bfi r2, r1, #7, #1281; CHECK-BE-NEXT: uxtb r1, r2282; CHECK-BE-NEXT: lsls r2, r2, #24283; CHECK-BE-NEXT: itt mi284; CHECK-BE-NEXT: vmovmi.u16 r2, q1[0]285; CHECK-BE-NEXT: strhmi r2, [r0]286; CHECK-BE-NEXT: lsls r2, r1, #25287; CHECK-BE-NEXT: itt mi288; CHECK-BE-NEXT: vmovmi.u16 r2, q1[1]289; CHECK-BE-NEXT: strhmi r2, [r0, #2]290; CHECK-BE-NEXT: lsls r2, r1, #26291; CHECK-BE-NEXT: itt mi292; CHECK-BE-NEXT: vmovmi.u16 r2, q1[2]293; CHECK-BE-NEXT: strhmi r2, [r0, #4]294; CHECK-BE-NEXT: lsls r2, r1, #27295; CHECK-BE-NEXT: itt mi296; CHECK-BE-NEXT: vmovmi.u16 r2, q1[3]297; CHECK-BE-NEXT: strhmi r2, [r0, #6]298; CHECK-BE-NEXT: lsls r2, r1, #28299; CHECK-BE-NEXT: itt mi300; CHECK-BE-NEXT: vmovmi.u16 r2, q1[4]301; CHECK-BE-NEXT: strhmi r2, [r0, #8]302; CHECK-BE-NEXT: lsls r2, r1, #29303; CHECK-BE-NEXT: itt mi304; CHECK-BE-NEXT: vmovmi.u16 r2, q1[5]305; CHECK-BE-NEXT: strhmi r2, [r0, #10]306; CHECK-BE-NEXT: lsls r2, r1, #30307; CHECK-BE-NEXT: itt mi308; CHECK-BE-NEXT: vmovmi.u16 r2, q1[6]309; CHECK-BE-NEXT: strhmi r2, [r0, #12]310; CHECK-BE-NEXT: lsls r1, r1, #31311; CHECK-BE-NEXT: itt ne312; CHECK-BE-NEXT: vmovne.u16 r1, q1[7]313; CHECK-BE-NEXT: strhne r1, [r0, #14]314; CHECK-BE-NEXT: add sp, #4315; CHECK-BE-NEXT: bx lr316entry:317 %c = icmp sgt <8 x i16> %a, zeroinitializer318 call void @llvm.masked.store.v8i16.p0(<8 x i16> %a, ptr %dest, i32 1, <8 x i1> %c)319 ret void320}321 322define ptr @masked_v8i16_pre(ptr %y, ptr %x, <8 x i16> %a) {323; CHECK-LE-LABEL: masked_v8i16_pre:324; CHECK-LE: @ %bb.0: @ %entry325; CHECK-LE-NEXT: vldr d1, [sp]326; CHECK-LE-NEXT: vmov d0, r2, r3327; CHECK-LE-NEXT: vldrw.u32 q1, [r1]328; CHECK-LE-NEXT: vpt.s16 gt, q0, zr329; CHECK-LE-NEXT: vstrht.16 q1, [r0, #4]!330; CHECK-LE-NEXT: bx lr331;332; CHECK-BE-LABEL: masked_v8i16_pre:333; CHECK-BE: @ %bb.0: @ %entry334; CHECK-BE-NEXT: vldr d1, [sp]335; CHECK-BE-NEXT: vmov d0, r3, r2336; CHECK-BE-NEXT: vldrh.u16 q1, [r1]337; CHECK-BE-NEXT: vrev64.16 q2, q0338; CHECK-BE-NEXT: vpt.s16 gt, q2, zr339; CHECK-BE-NEXT: vstrht.16 q1, [r0, #4]!340; CHECK-BE-NEXT: bx lr341entry:342 %z = getelementptr inbounds i8, ptr %y, i32 4343 %0 = load <8 x i16>, ptr %x, align 4344 %c = icmp sgt <8 x i16> %a, zeroinitializer345 call void @llvm.masked.store.v8i16.p0(<8 x i16> %0, ptr %z, i32 2, <8 x i1> %c)346 ret ptr %z347}348 349define ptr @masked_v8i16_post(ptr %y, ptr %x, <8 x i16> %a) {350; CHECK-LE-LABEL: masked_v8i16_post:351; CHECK-LE: @ %bb.0: @ %entry352; CHECK-LE-NEXT: vldr d1, [sp]353; CHECK-LE-NEXT: vmov d0, r2, r3354; CHECK-LE-NEXT: vldrw.u32 q1, [r1]355; CHECK-LE-NEXT: vpt.s16 gt, q0, zr356; CHECK-LE-NEXT: vstrht.16 q1, [r0], #4357; CHECK-LE-NEXT: bx lr358;359; CHECK-BE-LABEL: masked_v8i16_post:360; CHECK-BE: @ %bb.0: @ %entry361; CHECK-BE-NEXT: vldr d1, [sp]362; CHECK-BE-NEXT: vmov d0, r3, r2363; CHECK-BE-NEXT: vldrh.u16 q1, [r1]364; CHECK-BE-NEXT: vrev64.16 q2, q0365; CHECK-BE-NEXT: vpt.s16 gt, q2, zr366; CHECK-BE-NEXT: vstrht.16 q1, [r0], #4367; CHECK-BE-NEXT: bx lr368entry:369 %z = getelementptr inbounds i8, ptr %y, i32 4370 %0 = load <8 x i16>, ptr %x, align 4371 %c = icmp sgt <8 x i16> %a, zeroinitializer372 call void @llvm.masked.store.v8i16.p0(<8 x i16> %0, ptr %y, i32 2, <8 x i1> %c)373 ret ptr %z374}375 376 377define arm_aapcs_vfpcc void @masked_v16i8(ptr %dest, <16 x i8> %a) {378; CHECK-LE-LABEL: masked_v16i8:379; CHECK-LE: @ %bb.0: @ %entry380; CHECK-LE-NEXT: vpt.s8 gt, q0, zr381; CHECK-LE-NEXT: vstrbt.8 q0, [r0]382; CHECK-LE-NEXT: bx lr383;384; CHECK-BE-LABEL: masked_v16i8:385; CHECK-BE: @ %bb.0: @ %entry386; CHECK-BE-NEXT: vrev64.8 q1, q0387; CHECK-BE-NEXT: vpt.s8 gt, q1, zr388; CHECK-BE-NEXT: vstrbt.8 q1, [r0]389; CHECK-BE-NEXT: bx lr390entry:391 %c = icmp sgt <16 x i8> %a, zeroinitializer392 call void @llvm.masked.store.v16i8.p0(<16 x i8> %a, ptr %dest, i32 1, <16 x i1> %c)393 ret void394}395 396define ptr @masked_v16i8_pre(ptr %y, ptr %x, <16 x i8> %a) {397; CHECK-LE-LABEL: masked_v16i8_pre:398; CHECK-LE: @ %bb.0: @ %entry399; CHECK-LE-NEXT: vldr d1, [sp]400; CHECK-LE-NEXT: vmov d0, r2, r3401; CHECK-LE-NEXT: vldrw.u32 q1, [r1]402; CHECK-LE-NEXT: vpt.s8 gt, q0, zr403; CHECK-LE-NEXT: vstrbt.8 q1, [r0, #4]!404; CHECK-LE-NEXT: bx lr405;406; CHECK-BE-LABEL: masked_v16i8_pre:407; CHECK-BE: @ %bb.0: @ %entry408; CHECK-BE-NEXT: vldr d1, [sp]409; CHECK-BE-NEXT: vmov d0, r3, r2410; CHECK-BE-NEXT: vldrb.u8 q1, [r1]411; CHECK-BE-NEXT: vrev64.8 q2, q0412; CHECK-BE-NEXT: vpt.s8 gt, q2, zr413; CHECK-BE-NEXT: vstrbt.8 q1, [r0, #4]!414; CHECK-BE-NEXT: bx lr415entry:416 %z = getelementptr inbounds i8, ptr %y, i32 4417 %0 = load <16 x i8>, ptr %x, align 4418 %c = icmp sgt <16 x i8> %a, zeroinitializer419 call void @llvm.masked.store.v16i8.p0(<16 x i8> %0, ptr %z, i32 1, <16 x i1> %c)420 ret ptr %z421}422 423define ptr @masked_v16i8_post(ptr %y, ptr %x, <16 x i8> %a) {424; CHECK-LE-LABEL: masked_v16i8_post:425; CHECK-LE: @ %bb.0: @ %entry426; CHECK-LE-NEXT: vldr d1, [sp]427; CHECK-LE-NEXT: vmov d0, r2, r3428; CHECK-LE-NEXT: vldrw.u32 q1, [r1]429; CHECK-LE-NEXT: vpt.s8 gt, q0, zr430; CHECK-LE-NEXT: vstrbt.8 q1, [r0], #4431; CHECK-LE-NEXT: bx lr432;433; CHECK-BE-LABEL: masked_v16i8_post:434; CHECK-BE: @ %bb.0: @ %entry435; CHECK-BE-NEXT: vldr d1, [sp]436; CHECK-BE-NEXT: vmov d0, r3, r2437; CHECK-BE-NEXT: vldrb.u8 q1, [r1]438; CHECK-BE-NEXT: vrev64.8 q2, q0439; CHECK-BE-NEXT: vpt.s8 gt, q2, zr440; CHECK-BE-NEXT: vstrbt.8 q1, [r0], #4441; CHECK-BE-NEXT: bx lr442entry:443 %z = getelementptr inbounds i8, ptr %y, i32 4444 %0 = load <16 x i8>, ptr %x, align 4445 %c = icmp sgt <16 x i8> %a, zeroinitializer446 call void @llvm.masked.store.v16i8.p0(<16 x i8> %0, ptr %y, i32 1, <16 x i1> %c)447 ret ptr %z448}449 450 451define arm_aapcs_vfpcc void @masked_v4f32(ptr %dest, <4 x float> %a, <4 x i32> %b) {452; CHECK-LE-LABEL: masked_v4f32:453; CHECK-LE: @ %bb.0: @ %entry454; CHECK-LE-NEXT: vpt.i32 ne, q1, zr455; CHECK-LE-NEXT: vstrwt.32 q0, [r0]456; CHECK-LE-NEXT: bx lr457;458; CHECK-BE-LABEL: masked_v4f32:459; CHECK-BE: @ %bb.0: @ %entry460; CHECK-BE-NEXT: vrev64.32 q2, q1461; CHECK-BE-NEXT: vrev64.32 q1, q0462; CHECK-BE-NEXT: vpt.i32 ne, q2, zr463; CHECK-BE-NEXT: vstrwt.32 q1, [r0]464; CHECK-BE-NEXT: bx lr465entry:466 %c = icmp ugt <4 x i32> %b, zeroinitializer467 call void @llvm.masked.store.v4f32.p0(<4 x float> %a, ptr %dest, i32 4, <4 x i1> %c)468 ret void469}470 471define arm_aapcs_vfpcc void @masked_v4f32_align1(ptr %dest, <4 x float> %a, <4 x i32> %b) {472; CHECK-LE-LABEL: masked_v4f32_align1:473; CHECK-LE: @ %bb.0: @ %entry474; CHECK-LE-NEXT: .pad #4475; CHECK-LE-NEXT: sub sp, #4476; CHECK-LE-NEXT: vcmp.i32 ne, q1, zr477; CHECK-LE-NEXT: movs r1, #0478; CHECK-LE-NEXT: vmrs r2, p0479; CHECK-LE-NEXT: and r3, r2, #1480; CHECK-LE-NEXT: rsbs r3, r3, #0481; CHECK-LE-NEXT: bfi r1, r3, #0, #1482; CHECK-LE-NEXT: ubfx r3, r2, #4, #1483; CHECK-LE-NEXT: rsbs r3, r3, #0484; CHECK-LE-NEXT: bfi r1, r3, #1, #1485; CHECK-LE-NEXT: ubfx r3, r2, #8, #1486; CHECK-LE-NEXT: ubfx r2, r2, #12, #1487; CHECK-LE-NEXT: rsbs r3, r3, #0488; CHECK-LE-NEXT: bfi r1, r3, #2, #1489; CHECK-LE-NEXT: rsbs r2, r2, #0490; CHECK-LE-NEXT: bfi r1, r2, #3, #1491; CHECK-LE-NEXT: lsls r2, r1, #31492; CHECK-LE-NEXT: itt ne493; CHECK-LE-NEXT: vmovne r2, s0494; CHECK-LE-NEXT: strne r2, [r0]495; CHECK-LE-NEXT: lsls r2, r1, #30496; CHECK-LE-NEXT: itt mi497; CHECK-LE-NEXT: vmovmi r2, s1498; CHECK-LE-NEXT: strmi r2, [r0, #4]499; CHECK-LE-NEXT: lsls r2, r1, #29500; CHECK-LE-NEXT: itt mi501; CHECK-LE-NEXT: vmovmi r2, s2502; CHECK-LE-NEXT: strmi r2, [r0, #8]503; CHECK-LE-NEXT: lsls r1, r1, #28504; CHECK-LE-NEXT: itt mi505; CHECK-LE-NEXT: vmovmi r1, s3506; CHECK-LE-NEXT: strmi r1, [r0, #12]507; CHECK-LE-NEXT: add sp, #4508; CHECK-LE-NEXT: bx lr509;510; CHECK-BE-LABEL: masked_v4f32_align1:511; CHECK-BE: @ %bb.0: @ %entry512; CHECK-BE-NEXT: .pad #4513; CHECK-BE-NEXT: sub sp, #4514; CHECK-BE-NEXT: vrev64.32 q2, q1515; CHECK-BE-NEXT: movs r1, #0516; CHECK-BE-NEXT: vcmp.i32 ne, q2, zr517; CHECK-BE-NEXT: vrev64.32 q1, q0518; CHECK-BE-NEXT: vmrs r2, p0519; CHECK-BE-NEXT: ubfx r3, r2, #12, #1520; CHECK-BE-NEXT: rsbs r3, r3, #0521; CHECK-BE-NEXT: bfi r1, r3, #0, #1522; CHECK-BE-NEXT: ubfx r3, r2, #8, #1523; CHECK-BE-NEXT: rsbs r3, r3, #0524; CHECK-BE-NEXT: bfi r1, r3, #1, #1525; CHECK-BE-NEXT: ubfx r3, r2, #4, #1526; CHECK-BE-NEXT: and r2, r2, #1527; CHECK-BE-NEXT: rsbs r3, r3, #0528; CHECK-BE-NEXT: bfi r1, r3, #2, #1529; CHECK-BE-NEXT: rsbs r2, r2, #0530; CHECK-BE-NEXT: bfi r1, r2, #3, #1531; CHECK-BE-NEXT: lsls r2, r1, #28532; CHECK-BE-NEXT: itt mi533; CHECK-BE-NEXT: vmovmi r2, s4534; CHECK-BE-NEXT: strmi r2, [r0]535; CHECK-BE-NEXT: lsls r2, r1, #29536; CHECK-BE-NEXT: itt mi537; CHECK-BE-NEXT: vmovmi r2, s5538; CHECK-BE-NEXT: strmi r2, [r0, #4]539; CHECK-BE-NEXT: lsls r2, r1, #30540; CHECK-BE-NEXT: itt mi541; CHECK-BE-NEXT: vmovmi r2, s6542; CHECK-BE-NEXT: strmi r2, [r0, #8]543; CHECK-BE-NEXT: lsls r1, r1, #31544; CHECK-BE-NEXT: itt ne545; CHECK-BE-NEXT: vmovne r1, s7546; CHECK-BE-NEXT: strne r1, [r0, #12]547; CHECK-BE-NEXT: add sp, #4548; CHECK-BE-NEXT: bx lr549entry:550 %c = icmp ugt <4 x i32> %b, zeroinitializer551 call void @llvm.masked.store.v4f32.p0(<4 x float> %a, ptr %dest, i32 1, <4 x i1> %c)552 ret void553}554 555define ptr @masked_v4f32_pre(ptr %y, ptr %x, <4 x i32> %a) {556; CHECK-LE-LABEL: masked_v4f32_pre:557; CHECK-LE: @ %bb.0: @ %entry558; CHECK-LE-NEXT: vldr d1, [sp]559; CHECK-LE-NEXT: vmov d0, r2, r3560; CHECK-LE-NEXT: vldrw.u32 q1, [r1]561; CHECK-LE-NEXT: vpt.s32 gt, q0, zr562; CHECK-LE-NEXT: vstrwt.32 q1, [r0, #4]!563; CHECK-LE-NEXT: bx lr564;565; CHECK-BE-LABEL: masked_v4f32_pre:566; CHECK-BE: @ %bb.0: @ %entry567; CHECK-BE-NEXT: vldr d1, [sp]568; CHECK-BE-NEXT: vmov d0, r3, r2569; CHECK-BE-NEXT: vldrw.u32 q1, [r1]570; CHECK-BE-NEXT: vrev64.32 q2, q0571; CHECK-BE-NEXT: vpt.s32 gt, q2, zr572; CHECK-BE-NEXT: vstrwt.32 q1, [r0, #4]!573; CHECK-BE-NEXT: bx lr574entry:575 %z = getelementptr inbounds i8, ptr %y, i32 4576 %0 = load <4 x float>, ptr %x, align 4577 %c = icmp sgt <4 x i32> %a, zeroinitializer578 call void @llvm.masked.store.v4f32.p0(<4 x float> %0, ptr %z, i32 4, <4 x i1> %c)579 ret ptr %z580}581 582define ptr @masked_v4f32_post(ptr %y, ptr %x, <4 x i32> %a) {583; CHECK-LE-LABEL: masked_v4f32_post:584; CHECK-LE: @ %bb.0: @ %entry585; CHECK-LE-NEXT: vldr d1, [sp]586; CHECK-LE-NEXT: vmov d0, r2, r3587; CHECK-LE-NEXT: vldrw.u32 q1, [r1]588; CHECK-LE-NEXT: vpt.s32 gt, q0, zr589; CHECK-LE-NEXT: vstrwt.32 q1, [r0], #4590; CHECK-LE-NEXT: bx lr591;592; CHECK-BE-LABEL: masked_v4f32_post:593; CHECK-BE: @ %bb.0: @ %entry594; CHECK-BE-NEXT: vldr d1, [sp]595; CHECK-BE-NEXT: vmov d0, r3, r2596; CHECK-BE-NEXT: vldrw.u32 q1, [r1]597; CHECK-BE-NEXT: vrev64.32 q2, q0598; CHECK-BE-NEXT: vpt.s32 gt, q2, zr599; CHECK-BE-NEXT: vstrwt.32 q1, [r0], #4600; CHECK-BE-NEXT: bx lr601entry:602 %z = getelementptr inbounds i8, ptr %y, i32 4603 %0 = load <4 x float>, ptr %x, align 4604 %c = icmp sgt <4 x i32> %a, zeroinitializer605 call void @llvm.masked.store.v4f32.p0(<4 x float> %0, ptr %y, i32 4, <4 x i1> %c)606 ret ptr %z607}608 609 610define arm_aapcs_vfpcc void @masked_v8f16(ptr %dest, <8 x half> %a, <8 x i16> %b) {611; CHECK-LE-LABEL: masked_v8f16:612; CHECK-LE: @ %bb.0: @ %entry613; CHECK-LE-NEXT: vpt.i16 ne, q1, zr614; CHECK-LE-NEXT: vstrht.16 q0, [r0]615; CHECK-LE-NEXT: bx lr616;617; CHECK-BE-LABEL: masked_v8f16:618; CHECK-BE: @ %bb.0: @ %entry619; CHECK-BE-NEXT: vrev64.16 q2, q1620; CHECK-BE-NEXT: vrev64.16 q1, q0621; CHECK-BE-NEXT: vpt.i16 ne, q2, zr622; CHECK-BE-NEXT: vstrht.16 q1, [r0]623; CHECK-BE-NEXT: bx lr624entry:625 %c = icmp ugt <8 x i16> %b, zeroinitializer626 call void @llvm.masked.store.v8f16.p0(<8 x half> %a, ptr %dest, i32 2, <8 x i1> %c)627 ret void628}629 630define arm_aapcs_vfpcc void @masked_v8f16_align1(ptr %dest, <8 x half> %a, <8 x i16> %b) {631; CHECK-LE-LABEL: masked_v8f16_align1:632; CHECK-LE: @ %bb.0: @ %entry633; CHECK-LE-NEXT: .pad #36634; CHECK-LE-NEXT: sub sp, #36635; CHECK-LE-NEXT: vcmp.i16 ne, q1, zr636; CHECK-LE-NEXT: movs r2, #0637; CHECK-LE-NEXT: vmrs r1, p0638; CHECK-LE-NEXT: and r3, r1, #1639; CHECK-LE-NEXT: rsbs r3, r3, #0640; CHECK-LE-NEXT: bfi r2, r3, #0, #1641; CHECK-LE-NEXT: ubfx r3, r1, #2, #1642; CHECK-LE-NEXT: rsbs r3, r3, #0643; CHECK-LE-NEXT: bfi r2, r3, #1, #1644; CHECK-LE-NEXT: ubfx r3, r1, #4, #1645; CHECK-LE-NEXT: rsbs r3, r3, #0646; CHECK-LE-NEXT: bfi r2, r3, #2, #1647; CHECK-LE-NEXT: ubfx r3, r1, #6, #1648; CHECK-LE-NEXT: rsbs r3, r3, #0649; CHECK-LE-NEXT: bfi r2, r3, #3, #1650; CHECK-LE-NEXT: ubfx r3, r1, #8, #1651; CHECK-LE-NEXT: rsbs r3, r3, #0652; CHECK-LE-NEXT: bfi r2, r3, #4, #1653; CHECK-LE-NEXT: ubfx r3, r1, #10, #1654; CHECK-LE-NEXT: rsbs r3, r3, #0655; CHECK-LE-NEXT: bfi r2, r3, #5, #1656; CHECK-LE-NEXT: ubfx r3, r1, #12, #1657; CHECK-LE-NEXT: ubfx r1, r1, #14, #1658; CHECK-LE-NEXT: rsbs r3, r3, #0659; CHECK-LE-NEXT: bfi r2, r3, #6, #1660; CHECK-LE-NEXT: rsbs r1, r1, #0661; CHECK-LE-NEXT: bfi r2, r1, #7, #1662; CHECK-LE-NEXT: uxtb r1, r2663; CHECK-LE-NEXT: lsls r2, r2, #31664; CHECK-LE-NEXT: bne .LBB16_9665; CHECK-LE-NEXT: @ %bb.1: @ %else666; CHECK-LE-NEXT: lsls r2, r1, #30667; CHECK-LE-NEXT: bmi .LBB16_10668; CHECK-LE-NEXT: .LBB16_2: @ %else2669; CHECK-LE-NEXT: lsls r2, r1, #29670; CHECK-LE-NEXT: bmi .LBB16_11671; CHECK-LE-NEXT: .LBB16_3: @ %else4672; CHECK-LE-NEXT: lsls r2, r1, #28673; CHECK-LE-NEXT: bmi .LBB16_12674; CHECK-LE-NEXT: .LBB16_4: @ %else6675; CHECK-LE-NEXT: lsls r2, r1, #27676; CHECK-LE-NEXT: bmi .LBB16_13677; CHECK-LE-NEXT: .LBB16_5: @ %else8678; CHECK-LE-NEXT: lsls r2, r1, #26679; CHECK-LE-NEXT: bmi .LBB16_14680; CHECK-LE-NEXT: .LBB16_6: @ %else10681; CHECK-LE-NEXT: lsls r2, r1, #25682; CHECK-LE-NEXT: bmi .LBB16_15683; CHECK-LE-NEXT: .LBB16_7: @ %else12684; CHECK-LE-NEXT: lsls r1, r1, #24685; CHECK-LE-NEXT: bmi .LBB16_16686; CHECK-LE-NEXT: .LBB16_8: @ %else14687; CHECK-LE-NEXT: add sp, #36688; CHECK-LE-NEXT: bx lr689; CHECK-LE-NEXT: .LBB16_9: @ %cond.store690; CHECK-LE-NEXT: vstr.16 s0, [sp, #28]691; CHECK-LE-NEXT: ldrh.w r2, [sp, #28]692; CHECK-LE-NEXT: strh r2, [r0]693; CHECK-LE-NEXT: lsls r2, r1, #30694; CHECK-LE-NEXT: bpl .LBB16_2695; CHECK-LE-NEXT: .LBB16_10: @ %cond.store1696; CHECK-LE-NEXT: vmovx.f16 s0, s0697; CHECK-LE-NEXT: vstr.16 s0, [sp, #24]698; CHECK-LE-NEXT: ldrh.w r2, [sp, #24]699; CHECK-LE-NEXT: strh r2, [r0, #2]700; CHECK-LE-NEXT: lsls r2, r1, #29701; CHECK-LE-NEXT: bpl .LBB16_3702; CHECK-LE-NEXT: .LBB16_11: @ %cond.store3703; CHECK-LE-NEXT: vstr.16 s1, [sp, #20]704; CHECK-LE-NEXT: ldrh.w r2, [sp, #20]705; CHECK-LE-NEXT: strh r2, [r0, #4]706; CHECK-LE-NEXT: lsls r2, r1, #28707; CHECK-LE-NEXT: bpl .LBB16_4708; CHECK-LE-NEXT: .LBB16_12: @ %cond.store5709; CHECK-LE-NEXT: vmovx.f16 s0, s1710; CHECK-LE-NEXT: vstr.16 s0, [sp, #16]711; CHECK-LE-NEXT: ldrh.w r2, [sp, #16]712; CHECK-LE-NEXT: strh r2, [r0, #6]713; CHECK-LE-NEXT: lsls r2, r1, #27714; CHECK-LE-NEXT: bpl .LBB16_5715; CHECK-LE-NEXT: .LBB16_13: @ %cond.store7716; CHECK-LE-NEXT: vstr.16 s2, [sp, #12]717; CHECK-LE-NEXT: ldrh.w r2, [sp, #12]718; CHECK-LE-NEXT: strh r2, [r0, #8]719; CHECK-LE-NEXT: lsls r2, r1, #26720; CHECK-LE-NEXT: bpl .LBB16_6721; CHECK-LE-NEXT: .LBB16_14: @ %cond.store9722; CHECK-LE-NEXT: vmovx.f16 s0, s2723; CHECK-LE-NEXT: vstr.16 s0, [sp, #8]724; CHECK-LE-NEXT: ldrh.w r2, [sp, #8]725; CHECK-LE-NEXT: strh r2, [r0, #10]726; CHECK-LE-NEXT: lsls r2, r1, #25727; CHECK-LE-NEXT: bpl .LBB16_7728; CHECK-LE-NEXT: .LBB16_15: @ %cond.store11729; CHECK-LE-NEXT: vstr.16 s3, [sp, #4]730; CHECK-LE-NEXT: ldrh.w r2, [sp, #4]731; CHECK-LE-NEXT: strh r2, [r0, #12]732; CHECK-LE-NEXT: lsls r1, r1, #24733; CHECK-LE-NEXT: bpl .LBB16_8734; CHECK-LE-NEXT: .LBB16_16: @ %cond.store13735; CHECK-LE-NEXT: vmovx.f16 s0, s3736; CHECK-LE-NEXT: vstr.16 s0, [sp]737; CHECK-LE-NEXT: ldrh.w r1, [sp]738; CHECK-LE-NEXT: strh r1, [r0, #14]739; CHECK-LE-NEXT: add sp, #36740; CHECK-LE-NEXT: bx lr741;742; CHECK-BE-LABEL: masked_v8f16_align1:743; CHECK-BE: @ %bb.0: @ %entry744; CHECK-BE-NEXT: .pad #36745; CHECK-BE-NEXT: sub sp, #36746; CHECK-BE-NEXT: vrev64.16 q2, q1747; CHECK-BE-NEXT: vrev64.16 q1, q0748; CHECK-BE-NEXT: vcmp.i16 ne, q2, zr749; CHECK-BE-NEXT: vmrs r1, p0750; CHECK-BE-NEXT: ubfx r2, r1, #14, #1751; CHECK-BE-NEXT: rsbs r3, r2, #0752; CHECK-BE-NEXT: movs r2, #0753; CHECK-BE-NEXT: bfi r2, r3, #0, #1754; CHECK-BE-NEXT: ubfx r3, r1, #12, #1755; CHECK-BE-NEXT: rsbs r3, r3, #0756; CHECK-BE-NEXT: bfi r2, r3, #1, #1757; CHECK-BE-NEXT: ubfx r3, r1, #10, #1758; CHECK-BE-NEXT: rsbs r3, r3, #0759; CHECK-BE-NEXT: bfi r2, r3, #2, #1760; CHECK-BE-NEXT: ubfx r3, r1, #8, #1761; CHECK-BE-NEXT: rsbs r3, r3, #0762; CHECK-BE-NEXT: bfi r2, r3, #3, #1763; CHECK-BE-NEXT: ubfx r3, r1, #6, #1764; CHECK-BE-NEXT: rsbs r3, r3, #0765; CHECK-BE-NEXT: bfi r2, r3, #4, #1766; CHECK-BE-NEXT: ubfx r3, r1, #4, #1767; CHECK-BE-NEXT: rsbs r3, r3, #0768; CHECK-BE-NEXT: bfi r2, r3, #5, #1769; CHECK-BE-NEXT: ubfx r3, r1, #2, #1770; CHECK-BE-NEXT: and r1, r1, #1771; CHECK-BE-NEXT: rsbs r3, r3, #0772; CHECK-BE-NEXT: bfi r2, r3, #6, #1773; CHECK-BE-NEXT: rsbs r1, r1, #0774; CHECK-BE-NEXT: bfi r2, r1, #7, #1775; CHECK-BE-NEXT: uxtb r1, r2776; CHECK-BE-NEXT: lsls r2, r2, #24777; CHECK-BE-NEXT: bmi .LBB16_9778; CHECK-BE-NEXT: @ %bb.1: @ %else779; CHECK-BE-NEXT: lsls r2, r1, #25780; CHECK-BE-NEXT: bmi .LBB16_10781; CHECK-BE-NEXT: .LBB16_2: @ %else2782; CHECK-BE-NEXT: lsls r2, r1, #26783; CHECK-BE-NEXT: bmi .LBB16_11784; CHECK-BE-NEXT: .LBB16_3: @ %else4785; CHECK-BE-NEXT: lsls r2, r1, #27786; CHECK-BE-NEXT: bmi .LBB16_12787; CHECK-BE-NEXT: .LBB16_4: @ %else6788; CHECK-BE-NEXT: lsls r2, r1, #28789; CHECK-BE-NEXT: bmi .LBB16_13790; CHECK-BE-NEXT: .LBB16_5: @ %else8791; CHECK-BE-NEXT: lsls r2, r1, #29792; CHECK-BE-NEXT: bmi .LBB16_14793; CHECK-BE-NEXT: .LBB16_6: @ %else10794; CHECK-BE-NEXT: lsls r2, r1, #30795; CHECK-BE-NEXT: bmi .LBB16_15796; CHECK-BE-NEXT: .LBB16_7: @ %else12797; CHECK-BE-NEXT: lsls r1, r1, #31798; CHECK-BE-NEXT: bne .LBB16_16799; CHECK-BE-NEXT: .LBB16_8: @ %else14800; CHECK-BE-NEXT: add sp, #36801; CHECK-BE-NEXT: bx lr802; CHECK-BE-NEXT: .LBB16_9: @ %cond.store803; CHECK-BE-NEXT: vstr.16 s4, [sp, #28]804; CHECK-BE-NEXT: ldrh.w r2, [sp, #28]805; CHECK-BE-NEXT: strh r2, [r0]806; CHECK-BE-NEXT: lsls r2, r1, #25807; CHECK-BE-NEXT: bpl .LBB16_2808; CHECK-BE-NEXT: .LBB16_10: @ %cond.store1809; CHECK-BE-NEXT: vmovx.f16 s0, s4810; CHECK-BE-NEXT: vstr.16 s0, [sp, #24]811; CHECK-BE-NEXT: ldrh.w r2, [sp, #24]812; CHECK-BE-NEXT: strh r2, [r0, #2]813; CHECK-BE-NEXT: lsls r2, r1, #26814; CHECK-BE-NEXT: bpl .LBB16_3815; CHECK-BE-NEXT: .LBB16_11: @ %cond.store3816; CHECK-BE-NEXT: vstr.16 s5, [sp, #20]817; CHECK-BE-NEXT: ldrh.w r2, [sp, #20]818; CHECK-BE-NEXT: strh r2, [r0, #4]819; CHECK-BE-NEXT: lsls r2, r1, #27820; CHECK-BE-NEXT: bpl .LBB16_4821; CHECK-BE-NEXT: .LBB16_12: @ %cond.store5822; CHECK-BE-NEXT: vmovx.f16 s0, s5823; CHECK-BE-NEXT: vstr.16 s0, [sp, #16]824; CHECK-BE-NEXT: ldrh.w r2, [sp, #16]825; CHECK-BE-NEXT: strh r2, [r0, #6]826; CHECK-BE-NEXT: lsls r2, r1, #28827; CHECK-BE-NEXT: bpl .LBB16_5828; CHECK-BE-NEXT: .LBB16_13: @ %cond.store7829; CHECK-BE-NEXT: vstr.16 s6, [sp, #12]830; CHECK-BE-NEXT: ldrh.w r2, [sp, #12]831; CHECK-BE-NEXT: strh r2, [r0, #8]832; CHECK-BE-NEXT: lsls r2, r1, #29833; CHECK-BE-NEXT: bpl .LBB16_6834; CHECK-BE-NEXT: .LBB16_14: @ %cond.store9835; CHECK-BE-NEXT: vmovx.f16 s0, s6836; CHECK-BE-NEXT: vstr.16 s0, [sp, #8]837; CHECK-BE-NEXT: ldrh.w r2, [sp, #8]838; CHECK-BE-NEXT: strh r2, [r0, #10]839; CHECK-BE-NEXT: lsls r2, r1, #30840; CHECK-BE-NEXT: bpl .LBB16_7841; CHECK-BE-NEXT: .LBB16_15: @ %cond.store11842; CHECK-BE-NEXT: vstr.16 s7, [sp, #4]843; CHECK-BE-NEXT: ldrh.w r2, [sp, #4]844; CHECK-BE-NEXT: strh r2, [r0, #12]845; CHECK-BE-NEXT: lsls r1, r1, #31846; CHECK-BE-NEXT: beq .LBB16_8847; CHECK-BE-NEXT: .LBB16_16: @ %cond.store13848; CHECK-BE-NEXT: vmovx.f16 s0, s7849; CHECK-BE-NEXT: vstr.16 s0, [sp]850; CHECK-BE-NEXT: ldrh.w r1, [sp]851; CHECK-BE-NEXT: strh r1, [r0, #14]852; CHECK-BE-NEXT: add sp, #36853; CHECK-BE-NEXT: bx lr854entry:855 %c = icmp ugt <8 x i16> %b, zeroinitializer856 call void @llvm.masked.store.v8f16.p0(<8 x half> %a, ptr %dest, i32 1, <8 x i1> %c)857 ret void858}859 860define ptr @masked_v8f16_pre(ptr %y, ptr %x, <8 x i16> %a) {861; CHECK-LE-LABEL: masked_v8f16_pre:862; CHECK-LE: @ %bb.0: @ %entry863; CHECK-LE-NEXT: vldr d1, [sp]864; CHECK-LE-NEXT: vmov d0, r2, r3865; CHECK-LE-NEXT: vldrw.u32 q1, [r1]866; CHECK-LE-NEXT: vpt.s16 gt, q0, zr867; CHECK-LE-NEXT: vstrht.16 q1, [r0, #4]!868; CHECK-LE-NEXT: bx lr869;870; CHECK-BE-LABEL: masked_v8f16_pre:871; CHECK-BE: @ %bb.0: @ %entry872; CHECK-BE-NEXT: vldr d1, [sp]873; CHECK-BE-NEXT: vmov d0, r3, r2874; CHECK-BE-NEXT: vldrh.u16 q1, [r1]875; CHECK-BE-NEXT: vrev64.16 q2, q0876; CHECK-BE-NEXT: vpt.s16 gt, q2, zr877; CHECK-BE-NEXT: vstrht.16 q1, [r0, #4]!878; CHECK-BE-NEXT: bx lr879entry:880 %z = getelementptr inbounds i8, ptr %y, i32 4881 %0 = load <8 x half>, ptr %x, align 4882 %c = icmp sgt <8 x i16> %a, zeroinitializer883 call void @llvm.masked.store.v8f16.p0(<8 x half> %0, ptr %z, i32 2, <8 x i1> %c)884 ret ptr %z885}886 887define ptr @masked_v8f16_post(ptr %y, ptr %x, <8 x i16> %a) {888; CHECK-LE-LABEL: masked_v8f16_post:889; CHECK-LE: @ %bb.0: @ %entry890; CHECK-LE-NEXT: vldr d1, [sp]891; CHECK-LE-NEXT: vmov d0, r2, r3892; CHECK-LE-NEXT: vldrw.u32 q1, [r1]893; CHECK-LE-NEXT: vpt.s16 gt, q0, zr894; CHECK-LE-NEXT: vstrht.16 q1, [r0], #4895; CHECK-LE-NEXT: bx lr896;897; CHECK-BE-LABEL: masked_v8f16_post:898; CHECK-BE: @ %bb.0: @ %entry899; CHECK-BE-NEXT: vldr d1, [sp]900; CHECK-BE-NEXT: vmov d0, r3, r2901; CHECK-BE-NEXT: vldrh.u16 q1, [r1]902; CHECK-BE-NEXT: vrev64.16 q2, q0903; CHECK-BE-NEXT: vpt.s16 gt, q2, zr904; CHECK-BE-NEXT: vstrht.16 q1, [r0], #4905; CHECK-BE-NEXT: bx lr906entry:907 %z = getelementptr inbounds i8, ptr %y, i32 4908 %0 = load <8 x half>, ptr %x, align 4909 %c = icmp sgt <8 x i16> %a, zeroinitializer910 call void @llvm.masked.store.v8f16.p0(<8 x half> %0, ptr %y, i32 2, <8 x i1> %c)911 ret ptr %z912}913 914 915define arm_aapcs_vfpcc void @masked_v2i64(ptr %dest, <2 x i64> %a) {916; CHECK-LE-LABEL: masked_v2i64:917; CHECK-LE: @ %bb.0: @ %entry918; CHECK-LE-NEXT: .save {r7, lr}919; CHECK-LE-NEXT: push {r7, lr}920; CHECK-LE-NEXT: .pad #4921; CHECK-LE-NEXT: sub sp, #4922; CHECK-LE-NEXT: vmov r2, r3, d0923; CHECK-LE-NEXT: movs r1, #0924; CHECK-LE-NEXT: vmov r12, lr, d1925; CHECK-LE-NEXT: rsbs r2, r2, #0926; CHECK-LE-NEXT: sbcs.w r2, r1, r3927; CHECK-LE-NEXT: csetm r2, lt928; CHECK-LE-NEXT: rsbs.w r3, r12, #0929; CHECK-LE-NEXT: sbcs.w r3, r1, lr930; CHECK-LE-NEXT: bfi r1, r2, #0, #1931; CHECK-LE-NEXT: csetm r2, lt932; CHECK-LE-NEXT: bfi r1, r2, #1, #1933; CHECK-LE-NEXT: lsls r2, r1, #31934; CHECK-LE-NEXT: it ne935; CHECK-LE-NEXT: vstrne d0, [r0]936; CHECK-LE-NEXT: lsls r1, r1, #30937; CHECK-LE-NEXT: it mi938; CHECK-LE-NEXT: vstrmi d1, [r0, #8]939; CHECK-LE-NEXT: add sp, #4940; CHECK-LE-NEXT: pop {r7, pc}941;942; CHECK-BE-LABEL: masked_v2i64:943; CHECK-BE: @ %bb.0: @ %entry944; CHECK-BE-NEXT: .save {r7, lr}945; CHECK-BE-NEXT: push {r7, lr}946; CHECK-BE-NEXT: .pad #4947; CHECK-BE-NEXT: sub sp, #4948; CHECK-BE-NEXT: vrev64.32 q1, q0949; CHECK-BE-NEXT: movs r1, #0950; CHECK-BE-NEXT: vmov r2, r3, d3951; CHECK-BE-NEXT: vmov r12, lr, d2952; CHECK-BE-NEXT: rsbs r3, r3, #0953; CHECK-BE-NEXT: sbcs.w r2, r1, r2954; CHECK-BE-NEXT: csetm r2, lt955; CHECK-BE-NEXT: rsbs.w r3, lr, #0956; CHECK-BE-NEXT: sbcs.w r3, r1, r12957; CHECK-BE-NEXT: bfi r1, r2, #0, #1958; CHECK-BE-NEXT: csetm r2, lt959; CHECK-BE-NEXT: bfi r1, r2, #1, #1960; CHECK-BE-NEXT: lsls r2, r1, #30961; CHECK-BE-NEXT: it mi962; CHECK-BE-NEXT: vstrmi d0, [r0]963; CHECK-BE-NEXT: lsls r1, r1, #31964; CHECK-BE-NEXT: it ne965; CHECK-BE-NEXT: vstrne d1, [r0, #8]966; CHECK-BE-NEXT: add sp, #4967; CHECK-BE-NEXT: pop {r7, pc}968entry:969 %c = icmp sgt <2 x i64> %a, zeroinitializer970 call void @llvm.masked.store.v2i64.p0(<2 x i64> %a, ptr %dest, i32 8, <2 x i1> %c)971 ret void972}973 974define arm_aapcs_vfpcc void @masked_v2f64(ptr %dest, <2 x double> %a, <2 x i64> %b) {975; CHECK-LE-LABEL: masked_v2f64:976; CHECK-LE: @ %bb.0: @ %entry977; CHECK-LE-NEXT: .save {r7, lr}978; CHECK-LE-NEXT: push {r7, lr}979; CHECK-LE-NEXT: .pad #4980; CHECK-LE-NEXT: sub sp, #4981; CHECK-LE-NEXT: vmov r2, r3, d2982; CHECK-LE-NEXT: movs r1, #0983; CHECK-LE-NEXT: vmov r12, lr, d3984; CHECK-LE-NEXT: rsbs r2, r2, #0985; CHECK-LE-NEXT: sbcs.w r2, r1, r3986; CHECK-LE-NEXT: csetm r2, lt987; CHECK-LE-NEXT: rsbs.w r3, r12, #0988; CHECK-LE-NEXT: sbcs.w r3, r1, lr989; CHECK-LE-NEXT: bfi r1, r2, #0, #1990; CHECK-LE-NEXT: csetm r2, lt991; CHECK-LE-NEXT: bfi r1, r2, #1, #1992; CHECK-LE-NEXT: lsls r2, r1, #31993; CHECK-LE-NEXT: it ne994; CHECK-LE-NEXT: vstrne d0, [r0]995; CHECK-LE-NEXT: lsls r1, r1, #30996; CHECK-LE-NEXT: it mi997; CHECK-LE-NEXT: vstrmi d1, [r0, #8]998; CHECK-LE-NEXT: add sp, #4999; CHECK-LE-NEXT: pop {r7, pc}1000;1001; CHECK-BE-LABEL: masked_v2f64:1002; CHECK-BE: @ %bb.0: @ %entry1003; CHECK-BE-NEXT: .save {r7, lr}1004; CHECK-BE-NEXT: push {r7, lr}1005; CHECK-BE-NEXT: .pad #41006; CHECK-BE-NEXT: sub sp, #41007; CHECK-BE-NEXT: vrev64.32 q2, q11008; CHECK-BE-NEXT: movs r1, #01009; CHECK-BE-NEXT: vmov r2, r3, d51010; CHECK-BE-NEXT: vmov r12, lr, d41011; CHECK-BE-NEXT: rsbs r3, r3, #01012; CHECK-BE-NEXT: sbcs.w r2, r1, r21013; CHECK-BE-NEXT: csetm r2, lt1014; CHECK-BE-NEXT: rsbs.w r3, lr, #01015; CHECK-BE-NEXT: sbcs.w r3, r1, r121016; CHECK-BE-NEXT: bfi r1, r2, #0, #11017; CHECK-BE-NEXT: csetm r2, lt1018; CHECK-BE-NEXT: bfi r1, r2, #1, #11019; CHECK-BE-NEXT: lsls r2, r1, #301020; CHECK-BE-NEXT: it mi1021; CHECK-BE-NEXT: vstrmi d0, [r0]1022; CHECK-BE-NEXT: lsls r1, r1, #311023; CHECK-BE-NEXT: it ne1024; CHECK-BE-NEXT: vstrne d1, [r0, #8]1025; CHECK-BE-NEXT: add sp, #41026; CHECK-BE-NEXT: pop {r7, pc}1027entry:1028 %c = icmp sgt <2 x i64> %b, zeroinitializer1029 call void @llvm.masked.store.v2f64.p0(<2 x double> %a, ptr %dest, i32 8, <2 x i1> %c)1030 ret void1031}1032 1033define arm_aapcs_vfpcc void @masked_v4i16(ptr %dest, <4 x i32> %a) {1034; CHECK-LE-LABEL: masked_v4i16:1035; CHECK-LE: @ %bb.0: @ %entry1036; CHECK-LE-NEXT: vpt.s32 gt, q0, zr1037; CHECK-LE-NEXT: vstrht.32 q0, [r0]1038; CHECK-LE-NEXT: bx lr1039;1040; CHECK-BE-LABEL: masked_v4i16:1041; CHECK-BE: @ %bb.0: @ %entry1042; CHECK-BE-NEXT: vrev64.32 q1, q01043; CHECK-BE-NEXT: vpt.s32 gt, q1, zr1044; CHECK-BE-NEXT: vstrht.32 q1, [r0]1045; CHECK-BE-NEXT: bx lr1046entry:1047 %c = icmp sgt <4 x i32> %a, zeroinitializer1048 %trunc = trunc <4 x i32> %a to <4 x i16>1049 call void @llvm.masked.store.v4i16.p0(<4 x i16> %trunc, ptr %dest, i32 2, <4 x i1> %c)1050 ret void1051}1052 1053define arm_aapcs_vfpcc void @masked_v4i8(ptr %dest, <4 x i32> %a) {1054; CHECK-LE-LABEL: masked_v4i8:1055; CHECK-LE: @ %bb.0: @ %entry1056; CHECK-LE-NEXT: vpt.s32 gt, q0, zr1057; CHECK-LE-NEXT: vstrbt.32 q0, [r0]1058; CHECK-LE-NEXT: bx lr1059;1060; CHECK-BE-LABEL: masked_v4i8:1061; CHECK-BE: @ %bb.0: @ %entry1062; CHECK-BE-NEXT: vrev64.32 q1, q01063; CHECK-BE-NEXT: vpt.s32 gt, q1, zr1064; CHECK-BE-NEXT: vstrbt.32 q1, [r0]1065; CHECK-BE-NEXT: bx lr1066entry:1067 %c = icmp sgt <4 x i32> %a, zeroinitializer1068 %trunc = trunc <4 x i32> %a to <4 x i8>1069 call void @llvm.masked.store.v4i8.p0(<4 x i8> %trunc, ptr %dest, i32 1, <4 x i1> %c)1070 ret void1071}1072 1073define arm_aapcs_vfpcc void @masked_v8i8(ptr %dest, <8 x i16> %a) {1074; CHECK-LE-LABEL: masked_v8i8:1075; CHECK-LE: @ %bb.0: @ %entry1076; CHECK-LE-NEXT: vpt.s16 gt, q0, zr1077; CHECK-LE-NEXT: vstrbt.16 q0, [r0]1078; CHECK-LE-NEXT: bx lr1079;1080; CHECK-BE-LABEL: masked_v8i8:1081; CHECK-BE: @ %bb.0: @ %entry1082; CHECK-BE-NEXT: vrev64.16 q1, q01083; CHECK-BE-NEXT: vpt.s16 gt, q1, zr1084; CHECK-BE-NEXT: vstrbt.16 q1, [r0]1085; CHECK-BE-NEXT: bx lr1086entry:1087 %c = icmp sgt <8 x i16> %a, zeroinitializer1088 %trunc = trunc <8 x i16> %a to <8 x i8>1089 call void @llvm.masked.store.v8i8.p0(<8 x i8> %trunc, ptr %dest, i32 1, <8 x i1> %c)1090 ret void1091}1092 1093define arm_aapcs_vfpcc void @masked_v4i16_align1(ptr %dest, <4 x i32> %a) {1094; CHECK-LE-LABEL: masked_v4i16_align1:1095; CHECK-LE: @ %bb.0: @ %entry1096; CHECK-LE-NEXT: .pad #41097; CHECK-LE-NEXT: sub sp, #41098; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr1099; CHECK-LE-NEXT: vmrs r2, p01100; CHECK-LE-NEXT: and r1, r2, #11101; CHECK-LE-NEXT: rsbs r3, r1, #01102; CHECK-LE-NEXT: movs r1, #01103; CHECK-LE-NEXT: bfi r1, r3, #0, #11104; CHECK-LE-NEXT: ubfx r3, r2, #4, #11105; CHECK-LE-NEXT: rsbs r3, r3, #01106; CHECK-LE-NEXT: bfi r1, r3, #1, #11107; CHECK-LE-NEXT: ubfx r3, r2, #8, #11108; CHECK-LE-NEXT: ubfx r2, r2, #12, #11109; CHECK-LE-NEXT: rsbs r3, r3, #01110; CHECK-LE-NEXT: bfi r1, r3, #2, #11111; CHECK-LE-NEXT: rsbs r2, r2, #01112; CHECK-LE-NEXT: bfi r1, r2, #3, #11113; CHECK-LE-NEXT: lsls r2, r1, #311114; CHECK-LE-NEXT: itt ne1115; CHECK-LE-NEXT: vmovne r2, s01116; CHECK-LE-NEXT: strhne r2, [r0]1117; CHECK-LE-NEXT: lsls r2, r1, #301118; CHECK-LE-NEXT: itt mi1119; CHECK-LE-NEXT: vmovmi r2, s11120; CHECK-LE-NEXT: strhmi r2, [r0, #2]1121; CHECK-LE-NEXT: lsls r2, r1, #291122; CHECK-LE-NEXT: itt mi1123; CHECK-LE-NEXT: vmovmi r2, s21124; CHECK-LE-NEXT: strhmi r2, [r0, #4]1125; CHECK-LE-NEXT: lsls r1, r1, #281126; CHECK-LE-NEXT: itt mi1127; CHECK-LE-NEXT: vmovmi r1, s31128; CHECK-LE-NEXT: strhmi r1, [r0, #6]1129; CHECK-LE-NEXT: add sp, #41130; CHECK-LE-NEXT: bx lr1131;1132; CHECK-BE-LABEL: masked_v4i16_align1:1133; CHECK-BE: @ %bb.0: @ %entry1134; CHECK-BE-NEXT: .pad #41135; CHECK-BE-NEXT: sub sp, #41136; CHECK-BE-NEXT: vrev64.32 q1, q01137; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr1138; CHECK-BE-NEXT: vmrs r2, p01139; CHECK-BE-NEXT: ubfx r1, r2, #12, #11140; CHECK-BE-NEXT: rsbs r3, r1, #01141; CHECK-BE-NEXT: movs r1, #01142; CHECK-BE-NEXT: bfi r1, r3, #0, #11143; CHECK-BE-NEXT: ubfx r3, r2, #8, #11144; CHECK-BE-NEXT: rsbs r3, r3, #01145; CHECK-BE-NEXT: bfi r1, r3, #1, #11146; CHECK-BE-NEXT: ubfx r3, r2, #4, #11147; CHECK-BE-NEXT: and r2, r2, #11148; CHECK-BE-NEXT: rsbs r3, r3, #01149; CHECK-BE-NEXT: bfi r1, r3, #2, #11150; CHECK-BE-NEXT: rsbs r2, r2, #01151; CHECK-BE-NEXT: bfi r1, r2, #3, #11152; CHECK-BE-NEXT: lsls r2, r1, #281153; CHECK-BE-NEXT: itt mi1154; CHECK-BE-NEXT: vmovmi r2, s41155; CHECK-BE-NEXT: strhmi r2, [r0]1156; CHECK-BE-NEXT: lsls r2, r1, #291157; CHECK-BE-NEXT: itt mi1158; CHECK-BE-NEXT: vmovmi r2, s51159; CHECK-BE-NEXT: strhmi r2, [r0, #2]1160; CHECK-BE-NEXT: lsls r2, r1, #301161; CHECK-BE-NEXT: itt mi1162; CHECK-BE-NEXT: vmovmi r2, s61163; CHECK-BE-NEXT: strhmi r2, [r0, #4]1164; CHECK-BE-NEXT: lsls r1, r1, #311165; CHECK-BE-NEXT: itt ne1166; CHECK-BE-NEXT: vmovne r1, s71167; CHECK-BE-NEXT: strhne r1, [r0, #6]1168; CHECK-BE-NEXT: add sp, #41169; CHECK-BE-NEXT: bx lr1170entry:1171 %c = icmp sgt <4 x i32> %a, zeroinitializer1172 %trunc = trunc <4 x i32> %a to <4 x i16>1173 call void @llvm.masked.store.v4i16.p0(<4 x i16> %trunc, ptr %dest, i32 1, <4 x i1> %c)1174 ret void1175}1176 1177define arm_aapcs_vfpcc void @masked_v4f16_align4(ptr %dest, <4 x float> %a) {1178; CHECK-LE-LABEL: masked_v4f16_align4:1179; CHECK-LE: @ %bb.0: @ %entry1180; CHECK-LE-NEXT: .pad #41181; CHECK-LE-NEXT: sub sp, #41182; CHECK-LE-NEXT: vcmp.f32 s0, #01183; CHECK-LE-NEXT: movs r1, #01184; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1185; CHECK-LE-NEXT: vcmp.f32 s1, #01186; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s01187; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s21188; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s11189; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s31190; CHECK-LE-NEXT: csetm r2, gt1191; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1192; CHECK-LE-NEXT: vcmp.f32 s2, #01193; CHECK-LE-NEXT: bfi r1, r2, #0, #11194; CHECK-LE-NEXT: csetm r2, gt1195; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1196; CHECK-LE-NEXT: vcmp.f32 s3, #01197; CHECK-LE-NEXT: bfi r1, r2, #1, #11198; CHECK-LE-NEXT: csetm r2, gt1199; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1200; CHECK-LE-NEXT: bfi r1, r2, #2, #11201; CHECK-LE-NEXT: csetm r2, gt1202; CHECK-LE-NEXT: bfi r1, r2, #3, #11203; CHECK-LE-NEXT: lsls r2, r1, #311204; CHECK-LE-NEXT: bne .LBB25_51205; CHECK-LE-NEXT: @ %bb.1: @ %else1206; CHECK-LE-NEXT: lsls r2, r1, #301207; CHECK-LE-NEXT: bmi .LBB25_61208; CHECK-LE-NEXT: .LBB25_2: @ %else21209; CHECK-LE-NEXT: lsls r2, r1, #291210; CHECK-LE-NEXT: bmi .LBB25_71211; CHECK-LE-NEXT: .LBB25_3: @ %else41212; CHECK-LE-NEXT: lsls r1, r1, #281213; CHECK-LE-NEXT: bmi .LBB25_81214; CHECK-LE-NEXT: .LBB25_4: @ %else61215; CHECK-LE-NEXT: add sp, #41216; CHECK-LE-NEXT: bx lr1217; CHECK-LE-NEXT: .LBB25_5: @ %cond.store1218; CHECK-LE-NEXT: vstr.16 s4, [r0]1219; CHECK-LE-NEXT: lsls r2, r1, #301220; CHECK-LE-NEXT: bpl .LBB25_21221; CHECK-LE-NEXT: .LBB25_6: @ %cond.store11222; CHECK-LE-NEXT: vmovx.f16 s0, s41223; CHECK-LE-NEXT: vstr.16 s0, [r0, #2]1224; CHECK-LE-NEXT: lsls r2, r1, #291225; CHECK-LE-NEXT: bpl .LBB25_31226; CHECK-LE-NEXT: .LBB25_7: @ %cond.store31227; CHECK-LE-NEXT: vstr.16 s5, [r0, #4]1228; CHECK-LE-NEXT: lsls r1, r1, #281229; CHECK-LE-NEXT: bpl .LBB25_41230; CHECK-LE-NEXT: .LBB25_8: @ %cond.store51231; CHECK-LE-NEXT: vmovx.f16 s0, s51232; CHECK-LE-NEXT: vstr.16 s0, [r0, #6]1233; CHECK-LE-NEXT: add sp, #41234; CHECK-LE-NEXT: bx lr1235;1236; CHECK-BE-LABEL: masked_v4f16_align4:1237; CHECK-BE: @ %bb.0: @ %entry1238; CHECK-BE-NEXT: .pad #41239; CHECK-BE-NEXT: sub sp, #41240; CHECK-BE-NEXT: vrev64.32 q1, q01241; CHECK-BE-NEXT: movs r1, #01242; CHECK-BE-NEXT: vcmp.f32 s7, #01243; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s41244; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1245; CHECK-BE-NEXT: vcmp.f32 s6, #01246; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s61247; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s51248; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s71249; CHECK-BE-NEXT: csetm r2, gt1250; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1251; CHECK-BE-NEXT: vcmp.f32 s5, #01252; CHECK-BE-NEXT: bfi r1, r2, #0, #11253; CHECK-BE-NEXT: csetm r2, gt1254; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1255; CHECK-BE-NEXT: vcmp.f32 s4, #01256; CHECK-BE-NEXT: bfi r1, r2, #1, #11257; CHECK-BE-NEXT: csetm r2, gt1258; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1259; CHECK-BE-NEXT: bfi r1, r2, #2, #11260; CHECK-BE-NEXT: csetm r2, gt1261; CHECK-BE-NEXT: bfi r1, r2, #3, #11262; CHECK-BE-NEXT: lsls r2, r1, #281263; CHECK-BE-NEXT: bmi .LBB25_51264; CHECK-BE-NEXT: @ %bb.1: @ %else1265; CHECK-BE-NEXT: lsls r2, r1, #291266; CHECK-BE-NEXT: bmi .LBB25_61267; CHECK-BE-NEXT: .LBB25_2: @ %else21268; CHECK-BE-NEXT: lsls r2, r1, #301269; CHECK-BE-NEXT: bmi .LBB25_71270; CHECK-BE-NEXT: .LBB25_3: @ %else41271; CHECK-BE-NEXT: lsls r1, r1, #311272; CHECK-BE-NEXT: bne .LBB25_81273; CHECK-BE-NEXT: .LBB25_4: @ %else61274; CHECK-BE-NEXT: add sp, #41275; CHECK-BE-NEXT: bx lr1276; CHECK-BE-NEXT: .LBB25_5: @ %cond.store1277; CHECK-BE-NEXT: vstr.16 s0, [r0]1278; CHECK-BE-NEXT: lsls r2, r1, #291279; CHECK-BE-NEXT: bpl .LBB25_21280; CHECK-BE-NEXT: .LBB25_6: @ %cond.store11281; CHECK-BE-NEXT: vmovx.f16 s0, s01282; CHECK-BE-NEXT: vstr.16 s0, [r0, #2]1283; CHECK-BE-NEXT: lsls r2, r1, #301284; CHECK-BE-NEXT: bpl .LBB25_31285; CHECK-BE-NEXT: .LBB25_7: @ %cond.store31286; CHECK-BE-NEXT: vstr.16 s1, [r0, #4]1287; CHECK-BE-NEXT: lsls r1, r1, #311288; CHECK-BE-NEXT: beq .LBB25_41289; CHECK-BE-NEXT: .LBB25_8: @ %cond.store51290; CHECK-BE-NEXT: vmovx.f16 s0, s11291; CHECK-BE-NEXT: vstr.16 s0, [r0, #6]1292; CHECK-BE-NEXT: add sp, #41293; CHECK-BE-NEXT: bx lr1294entry:1295 %c = fcmp ogt <4 x float> %a, zeroinitializer1296 %trunc = fptrunc <4 x float> %a to <4 x half>1297 call void @llvm.masked.store.v4f16.p0(<4 x half> %trunc, ptr %dest, i32 4, <4 x i1> %c)1298 ret void1299}1300 1301define arm_aapcs_vfpcc void @masked_v4f16_align2(ptr %dest, <4 x float> %a) {1302; CHECK-LE-LABEL: masked_v4f16_align2:1303; CHECK-LE: @ %bb.0: @ %entry1304; CHECK-LE-NEXT: .pad #41305; CHECK-LE-NEXT: sub sp, #41306; CHECK-LE-NEXT: vcmp.f32 s0, #01307; CHECK-LE-NEXT: movs r1, #01308; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1309; CHECK-LE-NEXT: vcmp.f32 s1, #01310; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s01311; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s21312; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s11313; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s31314; CHECK-LE-NEXT: csetm r2, gt1315; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1316; CHECK-LE-NEXT: vcmp.f32 s2, #01317; CHECK-LE-NEXT: bfi r1, r2, #0, #11318; CHECK-LE-NEXT: csetm r2, gt1319; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1320; CHECK-LE-NEXT: vcmp.f32 s3, #01321; CHECK-LE-NEXT: bfi r1, r2, #1, #11322; CHECK-LE-NEXT: csetm r2, gt1323; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1324; CHECK-LE-NEXT: bfi r1, r2, #2, #11325; CHECK-LE-NEXT: csetm r2, gt1326; CHECK-LE-NEXT: bfi r1, r2, #3, #11327; CHECK-LE-NEXT: lsls r2, r1, #311328; CHECK-LE-NEXT: bne .LBB26_51329; CHECK-LE-NEXT: @ %bb.1: @ %else1330; CHECK-LE-NEXT: lsls r2, r1, #301331; CHECK-LE-NEXT: bmi .LBB26_61332; CHECK-LE-NEXT: .LBB26_2: @ %else21333; CHECK-LE-NEXT: lsls r2, r1, #291334; CHECK-LE-NEXT: bmi .LBB26_71335; CHECK-LE-NEXT: .LBB26_3: @ %else41336; CHECK-LE-NEXT: lsls r1, r1, #281337; CHECK-LE-NEXT: bmi .LBB26_81338; CHECK-LE-NEXT: .LBB26_4: @ %else61339; CHECK-LE-NEXT: add sp, #41340; CHECK-LE-NEXT: bx lr1341; CHECK-LE-NEXT: .LBB26_5: @ %cond.store1342; CHECK-LE-NEXT: vstr.16 s4, [r0]1343; CHECK-LE-NEXT: lsls r2, r1, #301344; CHECK-LE-NEXT: bpl .LBB26_21345; CHECK-LE-NEXT: .LBB26_6: @ %cond.store11346; CHECK-LE-NEXT: vmovx.f16 s0, s41347; CHECK-LE-NEXT: vstr.16 s0, [r0, #2]1348; CHECK-LE-NEXT: lsls r2, r1, #291349; CHECK-LE-NEXT: bpl .LBB26_31350; CHECK-LE-NEXT: .LBB26_7: @ %cond.store31351; CHECK-LE-NEXT: vstr.16 s5, [r0, #4]1352; CHECK-LE-NEXT: lsls r1, r1, #281353; CHECK-LE-NEXT: bpl .LBB26_41354; CHECK-LE-NEXT: .LBB26_8: @ %cond.store51355; CHECK-LE-NEXT: vmovx.f16 s0, s51356; CHECK-LE-NEXT: vstr.16 s0, [r0, #6]1357; CHECK-LE-NEXT: add sp, #41358; CHECK-LE-NEXT: bx lr1359;1360; CHECK-BE-LABEL: masked_v4f16_align2:1361; CHECK-BE: @ %bb.0: @ %entry1362; CHECK-BE-NEXT: .pad #41363; CHECK-BE-NEXT: sub sp, #41364; CHECK-BE-NEXT: vrev64.32 q1, q01365; CHECK-BE-NEXT: movs r1, #01366; CHECK-BE-NEXT: vcmp.f32 s7, #01367; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s41368; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1369; CHECK-BE-NEXT: vcmp.f32 s6, #01370; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s61371; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s51372; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s71373; CHECK-BE-NEXT: csetm r2, gt1374; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1375; CHECK-BE-NEXT: vcmp.f32 s5, #01376; CHECK-BE-NEXT: bfi r1, r2, #0, #11377; CHECK-BE-NEXT: csetm r2, gt1378; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1379; CHECK-BE-NEXT: vcmp.f32 s4, #01380; CHECK-BE-NEXT: bfi r1, r2, #1, #11381; CHECK-BE-NEXT: csetm r2, gt1382; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1383; CHECK-BE-NEXT: bfi r1, r2, #2, #11384; CHECK-BE-NEXT: csetm r2, gt1385; CHECK-BE-NEXT: bfi r1, r2, #3, #11386; CHECK-BE-NEXT: lsls r2, r1, #281387; CHECK-BE-NEXT: bmi .LBB26_51388; CHECK-BE-NEXT: @ %bb.1: @ %else1389; CHECK-BE-NEXT: lsls r2, r1, #291390; CHECK-BE-NEXT: bmi .LBB26_61391; CHECK-BE-NEXT: .LBB26_2: @ %else21392; CHECK-BE-NEXT: lsls r2, r1, #301393; CHECK-BE-NEXT: bmi .LBB26_71394; CHECK-BE-NEXT: .LBB26_3: @ %else41395; CHECK-BE-NEXT: lsls r1, r1, #311396; CHECK-BE-NEXT: bne .LBB26_81397; CHECK-BE-NEXT: .LBB26_4: @ %else61398; CHECK-BE-NEXT: add sp, #41399; CHECK-BE-NEXT: bx lr1400; CHECK-BE-NEXT: .LBB26_5: @ %cond.store1401; CHECK-BE-NEXT: vstr.16 s0, [r0]1402; CHECK-BE-NEXT: lsls r2, r1, #291403; CHECK-BE-NEXT: bpl .LBB26_21404; CHECK-BE-NEXT: .LBB26_6: @ %cond.store11405; CHECK-BE-NEXT: vmovx.f16 s0, s01406; CHECK-BE-NEXT: vstr.16 s0, [r0, #2]1407; CHECK-BE-NEXT: lsls r2, r1, #301408; CHECK-BE-NEXT: bpl .LBB26_31409; CHECK-BE-NEXT: .LBB26_7: @ %cond.store31410; CHECK-BE-NEXT: vstr.16 s1, [r0, #4]1411; CHECK-BE-NEXT: lsls r1, r1, #311412; CHECK-BE-NEXT: beq .LBB26_41413; CHECK-BE-NEXT: .LBB26_8: @ %cond.store51414; CHECK-BE-NEXT: vmovx.f16 s0, s11415; CHECK-BE-NEXT: vstr.16 s0, [r0, #6]1416; CHECK-BE-NEXT: add sp, #41417; CHECK-BE-NEXT: bx lr1418entry:1419 %c = fcmp ogt <4 x float> %a, zeroinitializer1420 %trunc = fptrunc <4 x float> %a to <4 x half>1421 call void @llvm.masked.store.v4f16.p0(<4 x half> %trunc, ptr %dest, i32 2, <4 x i1> %c)1422 ret void1423}1424 1425define arm_aapcs_vfpcc void @masked_v4f16_align1(ptr %dest, <4 x float> %a) {1426; CHECK-LE-LABEL: masked_v4f16_align1:1427; CHECK-LE: @ %bb.0: @ %entry1428; CHECK-LE-NEXT: .pad #201429; CHECK-LE-NEXT: sub sp, #201430; CHECK-LE-NEXT: vcmp.f32 s0, #01431; CHECK-LE-NEXT: movs r1, #01432; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1433; CHECK-LE-NEXT: vcmp.f32 s1, #01434; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s01435; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s21436; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s11437; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s31438; CHECK-LE-NEXT: csetm r2, gt1439; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1440; CHECK-LE-NEXT: vcmp.f32 s2, #01441; CHECK-LE-NEXT: bfi r1, r2, #0, #11442; CHECK-LE-NEXT: csetm r2, gt1443; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1444; CHECK-LE-NEXT: vcmp.f32 s3, #01445; CHECK-LE-NEXT: bfi r1, r2, #1, #11446; CHECK-LE-NEXT: csetm r2, gt1447; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr1448; CHECK-LE-NEXT: bfi r1, r2, #2, #11449; CHECK-LE-NEXT: csetm r2, gt1450; CHECK-LE-NEXT: bfi r1, r2, #3, #11451; CHECK-LE-NEXT: lsls r2, r1, #311452; CHECK-LE-NEXT: bne .LBB27_51453; CHECK-LE-NEXT: @ %bb.1: @ %else1454; CHECK-LE-NEXT: lsls r2, r1, #301455; CHECK-LE-NEXT: bmi .LBB27_61456; CHECK-LE-NEXT: .LBB27_2: @ %else21457; CHECK-LE-NEXT: lsls r2, r1, #291458; CHECK-LE-NEXT: bmi .LBB27_71459; CHECK-LE-NEXT: .LBB27_3: @ %else41460; CHECK-LE-NEXT: lsls r1, r1, #281461; CHECK-LE-NEXT: bmi .LBB27_81462; CHECK-LE-NEXT: .LBB27_4: @ %else61463; CHECK-LE-NEXT: add sp, #201464; CHECK-LE-NEXT: bx lr1465; CHECK-LE-NEXT: .LBB27_5: @ %cond.store1466; CHECK-LE-NEXT: vstr.16 s4, [sp, #12]1467; CHECK-LE-NEXT: ldrh.w r2, [sp, #12]1468; CHECK-LE-NEXT: strh r2, [r0]1469; CHECK-LE-NEXT: lsls r2, r1, #301470; CHECK-LE-NEXT: bpl .LBB27_21471; CHECK-LE-NEXT: .LBB27_6: @ %cond.store11472; CHECK-LE-NEXT: vmovx.f16 s0, s41473; CHECK-LE-NEXT: vstr.16 s0, [sp, #8]1474; CHECK-LE-NEXT: ldrh.w r2, [sp, #8]1475; CHECK-LE-NEXT: strh r2, [r0, #2]1476; CHECK-LE-NEXT: lsls r2, r1, #291477; CHECK-LE-NEXT: bpl .LBB27_31478; CHECK-LE-NEXT: .LBB27_7: @ %cond.store31479; CHECK-LE-NEXT: vstr.16 s5, [sp, #4]1480; CHECK-LE-NEXT: ldrh.w r2, [sp, #4]1481; CHECK-LE-NEXT: strh r2, [r0, #4]1482; CHECK-LE-NEXT: lsls r1, r1, #281483; CHECK-LE-NEXT: bpl .LBB27_41484; CHECK-LE-NEXT: .LBB27_8: @ %cond.store51485; CHECK-LE-NEXT: vmovx.f16 s0, s51486; CHECK-LE-NEXT: vstr.16 s0, [sp]1487; CHECK-LE-NEXT: ldrh.w r1, [sp]1488; CHECK-LE-NEXT: strh r1, [r0, #6]1489; CHECK-LE-NEXT: add sp, #201490; CHECK-LE-NEXT: bx lr1491;1492; CHECK-BE-LABEL: masked_v4f16_align1:1493; CHECK-BE: @ %bb.0: @ %entry1494; CHECK-BE-NEXT: .pad #201495; CHECK-BE-NEXT: sub sp, #201496; CHECK-BE-NEXT: vrev64.32 q1, q01497; CHECK-BE-NEXT: movs r1, #01498; CHECK-BE-NEXT: vcmp.f32 s7, #01499; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s41500; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1501; CHECK-BE-NEXT: vcmp.f32 s6, #01502; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s61503; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s51504; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s71505; CHECK-BE-NEXT: csetm r2, gt1506; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1507; CHECK-BE-NEXT: vcmp.f32 s5, #01508; CHECK-BE-NEXT: bfi r1, r2, #0, #11509; CHECK-BE-NEXT: csetm r2, gt1510; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1511; CHECK-BE-NEXT: vcmp.f32 s4, #01512; CHECK-BE-NEXT: bfi r1, r2, #1, #11513; CHECK-BE-NEXT: csetm r2, gt1514; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr1515; CHECK-BE-NEXT: bfi r1, r2, #2, #11516; CHECK-BE-NEXT: csetm r2, gt1517; CHECK-BE-NEXT: bfi r1, r2, #3, #11518; CHECK-BE-NEXT: lsls r2, r1, #281519; CHECK-BE-NEXT: bmi .LBB27_51520; CHECK-BE-NEXT: @ %bb.1: @ %else1521; CHECK-BE-NEXT: lsls r2, r1, #291522; CHECK-BE-NEXT: bmi .LBB27_61523; CHECK-BE-NEXT: .LBB27_2: @ %else21524; CHECK-BE-NEXT: lsls r2, r1, #301525; CHECK-BE-NEXT: bmi .LBB27_71526; CHECK-BE-NEXT: .LBB27_3: @ %else41527; CHECK-BE-NEXT: lsls r1, r1, #311528; CHECK-BE-NEXT: bne .LBB27_81529; CHECK-BE-NEXT: .LBB27_4: @ %else61530; CHECK-BE-NEXT: add sp, #201531; CHECK-BE-NEXT: bx lr1532; CHECK-BE-NEXT: .LBB27_5: @ %cond.store1533; CHECK-BE-NEXT: vstr.16 s0, [sp, #12]1534; CHECK-BE-NEXT: ldrh.w r2, [sp, #12]1535; CHECK-BE-NEXT: strh r2, [r0]1536; CHECK-BE-NEXT: lsls r2, r1, #291537; CHECK-BE-NEXT: bpl .LBB27_21538; CHECK-BE-NEXT: .LBB27_6: @ %cond.store11539; CHECK-BE-NEXT: vmovx.f16 s0, s01540; CHECK-BE-NEXT: vstr.16 s0, [sp, #8]1541; CHECK-BE-NEXT: ldrh.w r2, [sp, #8]1542; CHECK-BE-NEXT: strh r2, [r0, #2]1543; CHECK-BE-NEXT: lsls r2, r1, #301544; CHECK-BE-NEXT: bpl .LBB27_31545; CHECK-BE-NEXT: .LBB27_7: @ %cond.store31546; CHECK-BE-NEXT: vstr.16 s1, [sp, #4]1547; CHECK-BE-NEXT: ldrh.w r2, [sp, #4]1548; CHECK-BE-NEXT: strh r2, [r0, #4]1549; CHECK-BE-NEXT: lsls r1, r1, #311550; CHECK-BE-NEXT: beq .LBB27_41551; CHECK-BE-NEXT: .LBB27_8: @ %cond.store51552; CHECK-BE-NEXT: vmovx.f16 s0, s11553; CHECK-BE-NEXT: vstr.16 s0, [sp]1554; CHECK-BE-NEXT: ldrh.w r1, [sp]1555; CHECK-BE-NEXT: strh r1, [r0, #6]1556; CHECK-BE-NEXT: add sp, #201557; CHECK-BE-NEXT: bx lr1558entry:1559 %c = fcmp ogt <4 x float> %a, zeroinitializer1560 %trunc = fptrunc <4 x float> %a to <4 x half>1561 call void @llvm.masked.store.v4f16.p0(<4 x half> %trunc, ptr %dest, i32 1, <4 x i1> %c)1562 ret void1563}1564 1565declare void @llvm.masked.store.v4i8.p0(<4 x i8>, ptr, i32, <4 x i1>)1566declare void @llvm.masked.store.v8i8.p0(<8 x i8>, ptr, i32, <8 x i1>)1567declare void @llvm.masked.store.v4i16.p0(<4 x i16>, ptr, i32, <4 x i1>)1568declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32, <4 x i1>)1569declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32, <8 x i1>)1570declare void @llvm.masked.store.v16i8.p0(<16 x i8>, ptr, i32, <16 x i1>)1571declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32, <4 x i1>)1572declare void @llvm.masked.store.v4f16.p0(<4 x half>, ptr, i32, <4 x i1>)1573declare void @llvm.masked.store.v8f16.p0(<8 x half>, ptr, i32, <8 x i1>)1574declare void @llvm.masked.store.v2i64.p0(<2 x i64>, ptr, i32, <2 x i1>)1575declare void @llvm.masked.store.v2f64.p0(<2 x double>, ptr, i32, <2 x i1>)1576