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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP4 5define arm_aapcs_vfpcc <16 x i8> @smin_v16i8(<16 x i8> %s1, <16 x i8> %s2) {6; CHECK-LABEL: smin_v16i8:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vmin.s8 q0, q0, q19; CHECK-NEXT: bx lr10entry:11 %0 = icmp slt <16 x i8> %s1, %s212 %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s213 ret <16 x i8> %114}15 16define arm_aapcs_vfpcc <8 x i16> @smin_v8i16(<8 x i16> %s1, <8 x i16> %s2) {17; CHECK-LABEL: smin_v8i16:18; CHECK: @ %bb.0: @ %entry19; CHECK-NEXT: vmin.s16 q0, q0, q120; CHECK-NEXT: bx lr21entry:22 %0 = icmp slt <8 x i16> %s1, %s223 %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s224 ret <8 x i16> %125}26 27define arm_aapcs_vfpcc <4 x i32> @smin_v4i32(<4 x i32> %s1, <4 x i32> %s2) {28; CHECK-LABEL: smin_v4i32:29; CHECK: @ %bb.0: @ %entry30; CHECK-NEXT: vmin.s32 q0, q0, q131; CHECK-NEXT: bx lr32entry:33 %0 = icmp slt <4 x i32> %s1, %s234 %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s235 ret <4 x i32> %136}37 38define arm_aapcs_vfpcc <2 x i64> @smin_v2i64(<2 x i64> %s1, <2 x i64> %s2) {39; CHECK-LABEL: smin_v2i64:40; CHECK: @ %bb.0: @ %entry41; CHECK-NEXT: .save {r4, r5, r7, lr}42; CHECK-NEXT: push {r4, r5, r7, lr}43; CHECK-NEXT: vmov r0, r1, d244; CHECK-NEXT: vmov r2, r3, d045; CHECK-NEXT: vmov r12, lr, d346; CHECK-NEXT: vmov r4, r5, d147; CHECK-NEXT: subs r0, r2, r048; CHECK-NEXT: sbcs.w r0, r3, r149; CHECK-NEXT: mov.w r1, #050; CHECK-NEXT: csetm r0, lt51; CHECK-NEXT: bfi r1, r0, #0, #852; CHECK-NEXT: subs.w r0, r4, r1253; CHECK-NEXT: sbcs.w r0, r5, lr54; CHECK-NEXT: csetm r0, lt55; CHECK-NEXT: bfi r1, r0, #8, #856; CHECK-NEXT: vmsr p0, r157; CHECK-NEXT: vpsel q0, q0, q158; CHECK-NEXT: pop {r4, r5, r7, pc}59entry:60 %0 = icmp slt <2 x i64> %s1, %s261 %1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s262 ret <2 x i64> %163}64 65define arm_aapcs_vfpcc <16 x i8> @umin_v16i8(<16 x i8> %s1, <16 x i8> %s2) {66; CHECK-LABEL: umin_v16i8:67; CHECK: @ %bb.0: @ %entry68; CHECK-NEXT: vmin.u8 q0, q0, q169; CHECK-NEXT: bx lr70entry:71 %0 = icmp ult <16 x i8> %s1, %s272 %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s273 ret <16 x i8> %174}75 76define arm_aapcs_vfpcc <8 x i16> @umin_v8i16(<8 x i16> %s1, <8 x i16> %s2) {77; CHECK-LABEL: umin_v8i16:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vmin.u16 q0, q0, q180; CHECK-NEXT: bx lr81entry:82 %0 = icmp ult <8 x i16> %s1, %s283 %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s284 ret <8 x i16> %185}86 87define arm_aapcs_vfpcc <4 x i32> @umin_v4i32(<4 x i32> %s1, <4 x i32> %s2) {88; CHECK-LABEL: umin_v4i32:89; CHECK: @ %bb.0: @ %entry90; CHECK-NEXT: vmin.u32 q0, q0, q191; CHECK-NEXT: bx lr92entry:93 %0 = icmp ult <4 x i32> %s1, %s294 %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s295 ret <4 x i32> %196}97 98define arm_aapcs_vfpcc <2 x i64> @umin_v2i64(<2 x i64> %s1, <2 x i64> %s2) {99; CHECK-LABEL: umin_v2i64:100; CHECK: @ %bb.0: @ %entry101; CHECK-NEXT: .save {r4, r5, r7, lr}102; CHECK-NEXT: push {r4, r5, r7, lr}103; CHECK-NEXT: vmov r0, r1, d2104; CHECK-NEXT: vmov r2, r3, d0105; CHECK-NEXT: vmov r12, lr, d3106; CHECK-NEXT: vmov r4, r5, d1107; CHECK-NEXT: subs r0, r2, r0108; CHECK-NEXT: sbcs.w r0, r3, r1109; CHECK-NEXT: mov.w r1, #0110; CHECK-NEXT: csetm r0, lo111; CHECK-NEXT: bfi r1, r0, #0, #8112; CHECK-NEXT: subs.w r0, r4, r12113; CHECK-NEXT: sbcs.w r0, r5, lr114; CHECK-NEXT: csetm r0, lo115; CHECK-NEXT: bfi r1, r0, #8, #8116; CHECK-NEXT: vmsr p0, r1117; CHECK-NEXT: vpsel q0, q0, q1118; CHECK-NEXT: pop {r4, r5, r7, pc}119entry:120 %0 = icmp ult <2 x i64> %s1, %s2121 %1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2122 ret <2 x i64> %1123}124 125 126define arm_aapcs_vfpcc <16 x i8> @smax_v16i8(<16 x i8> %s1, <16 x i8> %s2) {127; CHECK-LABEL: smax_v16i8:128; CHECK: @ %bb.0: @ %entry129; CHECK-NEXT: vmax.s8 q0, q0, q1130; CHECK-NEXT: bx lr131entry:132 %0 = icmp sgt <16 x i8> %s1, %s2133 %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2134 ret <16 x i8> %1135}136 137define arm_aapcs_vfpcc <8 x i16> @smax_v8i16(<8 x i16> %s1, <8 x i16> %s2) {138; CHECK-LABEL: smax_v8i16:139; CHECK: @ %bb.0: @ %entry140; CHECK-NEXT: vmax.s16 q0, q0, q1141; CHECK-NEXT: bx lr142entry:143 %0 = icmp sgt <8 x i16> %s1, %s2144 %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2145 ret <8 x i16> %1146}147 148define arm_aapcs_vfpcc <4 x i32> @smax_v4i32(<4 x i32> %s1, <4 x i32> %s2) {149; CHECK-LABEL: smax_v4i32:150; CHECK: @ %bb.0: @ %entry151; CHECK-NEXT: vmax.s32 q0, q0, q1152; CHECK-NEXT: bx lr153entry:154 %0 = icmp sgt <4 x i32> %s1, %s2155 %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2156 ret <4 x i32> %1157}158 159define arm_aapcs_vfpcc <2 x i64> @smax_v2i64(<2 x i64> %s1, <2 x i64> %s2) {160; CHECK-LABEL: smax_v2i64:161; CHECK: @ %bb.0: @ %entry162; CHECK-NEXT: .save {r4, r5, r7, lr}163; CHECK-NEXT: push {r4, r5, r7, lr}164; CHECK-NEXT: vmov r0, r1, d0165; CHECK-NEXT: vmov r2, r3, d2166; CHECK-NEXT: vmov r12, lr, d1167; CHECK-NEXT: vmov r4, r5, d3168; CHECK-NEXT: subs r0, r2, r0169; CHECK-NEXT: sbcs.w r0, r3, r1170; CHECK-NEXT: mov.w r1, #0171; CHECK-NEXT: csetm r0, lt172; CHECK-NEXT: bfi r1, r0, #0, #8173; CHECK-NEXT: subs.w r0, r4, r12174; CHECK-NEXT: sbcs.w r0, r5, lr175; CHECK-NEXT: csetm r0, lt176; CHECK-NEXT: bfi r1, r0, #8, #8177; CHECK-NEXT: vmsr p0, r1178; CHECK-NEXT: vpsel q0, q0, q1179; CHECK-NEXT: pop {r4, r5, r7, pc}180entry:181 %0 = icmp sgt <2 x i64> %s1, %s2182 %1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2183 ret <2 x i64> %1184}185 186define arm_aapcs_vfpcc <16 x i8> @umax_v16i8(<16 x i8> %s1, <16 x i8> %s2) {187; CHECK-LABEL: umax_v16i8:188; CHECK: @ %bb.0: @ %entry189; CHECK-NEXT: vmax.u8 q0, q0, q1190; CHECK-NEXT: bx lr191entry:192 %0 = icmp ugt <16 x i8> %s1, %s2193 %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2194 ret <16 x i8> %1195}196 197define arm_aapcs_vfpcc <8 x i16> @umax_v8i16(<8 x i16> %s1, <8 x i16> %s2) {198; CHECK-LABEL: umax_v8i16:199; CHECK: @ %bb.0: @ %entry200; CHECK-NEXT: vmax.u16 q0, q0, q1201; CHECK-NEXT: bx lr202entry:203 %0 = icmp ugt <8 x i16> %s1, %s2204 %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2205 ret <8 x i16> %1206}207 208define arm_aapcs_vfpcc <4 x i32> @umax_v4i32(<4 x i32> %s1, <4 x i32> %s2) {209; CHECK-LABEL: umax_v4i32:210; CHECK: @ %bb.0: @ %entry211; CHECK-NEXT: vmax.u32 q0, q0, q1212; CHECK-NEXT: bx lr213entry:214 %0 = icmp ugt <4 x i32> %s1, %s2215 %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2216 ret <4 x i32> %1217}218 219define arm_aapcs_vfpcc <2 x i64> @umax_v2i64(<2 x i64> %s1, <2 x i64> %s2) {220; CHECK-LABEL: umax_v2i64:221; CHECK: @ %bb.0: @ %entry222; CHECK-NEXT: .save {r4, r5, r7, lr}223; CHECK-NEXT: push {r4, r5, r7, lr}224; CHECK-NEXT: vmov r0, r1, d0225; CHECK-NEXT: vmov r2, r3, d2226; CHECK-NEXT: vmov r12, lr, d1227; CHECK-NEXT: vmov r4, r5, d3228; CHECK-NEXT: subs r0, r2, r0229; CHECK-NEXT: sbcs.w r0, r3, r1230; CHECK-NEXT: mov.w r1, #0231; CHECK-NEXT: csetm r0, lo232; CHECK-NEXT: bfi r1, r0, #0, #8233; CHECK-NEXT: subs.w r0, r4, r12234; CHECK-NEXT: sbcs.w r0, r5, lr235; CHECK-NEXT: csetm r0, lo236; CHECK-NEXT: bfi r1, r0, #8, #8237; CHECK-NEXT: vmsr p0, r1238; CHECK-NEXT: vpsel q0, q0, q1239; CHECK-NEXT: pop {r4, r5, r7, pc}240entry:241 %0 = icmp ugt <2 x i64> %s1, %s2242 %1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2243 ret <2 x i64> %1244}245 246 247define arm_aapcs_vfpcc <4 x float> @maxnm_float32_t(<4 x float> %src1, <4 x float> %src2) {248; CHECK-MVE-LABEL: maxnm_float32_t:249; CHECK-MVE: @ %bb.0: @ %entry250; CHECK-MVE-NEXT: vmaxnm.f32 s3, s7, s3251; CHECK-MVE-NEXT: vmaxnm.f32 s2, s6, s2252; CHECK-MVE-NEXT: vmaxnm.f32 s1, s5, s1253; CHECK-MVE-NEXT: vmaxnm.f32 s0, s4, s0254; CHECK-MVE-NEXT: bx lr255;256; CHECK-MVEFP-LABEL: maxnm_float32_t:257; CHECK-MVEFP: @ %bb.0: @ %entry258; CHECK-MVEFP-NEXT: vmaxnm.f32 q0, q1, q0259; CHECK-MVEFP-NEXT: bx lr260entry:261 %cmp = fcmp fast ogt <4 x float> %src2, %src1262 %0 = select <4 x i1> %cmp, <4 x float> %src2, <4 x float> %src1263 ret <4 x float> %0264}265 266define arm_aapcs_vfpcc <8 x half> @minnm_float16_t(<8 x half> %src1, <8 x half> %src2) {267; CHECK-MVE-LABEL: minnm_float16_t:268; CHECK-MVE: @ %bb.0: @ %entry269; CHECK-MVE-NEXT: vmovx.f16 s8, s0270; CHECK-MVE-NEXT: vmovx.f16 s10, s4271; CHECK-MVE-NEXT: vminnm.f16 s0, s4, s0272; CHECK-MVE-NEXT: vminnm.f16 s8, s10, s8273; CHECK-MVE-NEXT: vins.f16 s0, s8274; CHECK-MVE-NEXT: vmovx.f16 s4, s1275; CHECK-MVE-NEXT: vmovx.f16 s8, s5276; CHECK-MVE-NEXT: vminnm.f16 s1, s5, s1277; CHECK-MVE-NEXT: vminnm.f16 s4, s8, s4278; CHECK-MVE-NEXT: vmovx.f16 s8, s6279; CHECK-MVE-NEXT: vins.f16 s1, s4280; CHECK-MVE-NEXT: vmovx.f16 s4, s2281; CHECK-MVE-NEXT: vminnm.f16 s2, s6, s2282; CHECK-MVE-NEXT: vminnm.f16 s4, s8, s4283; CHECK-MVE-NEXT: vins.f16 s2, s4284; CHECK-MVE-NEXT: vmovx.f16 s4, s3285; CHECK-MVE-NEXT: vmovx.f16 s6, s7286; CHECK-MVE-NEXT: vminnm.f16 s3, s7, s3287; CHECK-MVE-NEXT: vminnm.f16 s4, s6, s4288; CHECK-MVE-NEXT: vins.f16 s3, s4289; CHECK-MVE-NEXT: bx lr290;291; CHECK-MVEFP-LABEL: minnm_float16_t:292; CHECK-MVEFP: @ %bb.0: @ %entry293; CHECK-MVEFP-NEXT: vminnm.f16 q0, q1, q0294; CHECK-MVEFP-NEXT: bx lr295entry:296 %cmp = fcmp fast ogt <8 x half> %src2, %src1297 %0 = select <8 x i1> %cmp, <8 x half> %src1, <8 x half> %src2298 ret <8 x half> %0299}300 301define arm_aapcs_vfpcc <2 x double> @maxnm_float64_t(<2 x double> %src1, <2 x double> %src2) {302; CHECK-LABEL: maxnm_float64_t:303; CHECK: @ %bb.0: @ %entry304; CHECK-NEXT: .save {r4, lr}305; CHECK-NEXT: push {r4, lr}306; CHECK-NEXT: .vsave {d8, d9, d10, d11}307; CHECK-NEXT: vpush {d8, d9, d10, d11}308; CHECK-NEXT: vmov q4, q1309; CHECK-NEXT: vmov q5, q0310; CHECK-NEXT: vmov r0, r1, d8311; CHECK-NEXT: vmov r2, r3, d10312; CHECK-NEXT: bl __aeabi_dcmpgt313; CHECK-NEXT: vmov r12, r1, d9314; CHECK-NEXT: cmp r0, #0315; CHECK-NEXT: vmov r2, r3, d11316; CHECK-NEXT: csetm r0, ne317; CHECK-NEXT: movs r4, #0318; CHECK-NEXT: bfi r4, r0, #0, #8319; CHECK-NEXT: mov r0, r12320; CHECK-NEXT: bl __aeabi_dcmpgt321; CHECK-NEXT: cmp r0, #0322; CHECK-NEXT: csetm r0, ne323; CHECK-NEXT: bfi r4, r0, #8, #8324; CHECK-NEXT: vmsr p0, r4325; CHECK-NEXT: vpsel q0, q4, q5326; CHECK-NEXT: vpop {d8, d9, d10, d11}327; CHECK-NEXT: pop {r4, pc}328entry:329 %cmp = fcmp fast ogt <2 x double> %src2, %src1330 %0 = select <2 x i1> %cmp, <2 x double> %src2, <2 x double> %src1331 ret <2 x double> %0332}333