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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve --verify-machineinstrs %s -o - | FileCheck %s3 4declare i8 @llvm.smax.i8(i8 %a, i8 %b) readnone5 6define arm_aapcs_vfpcc i8 @smaxi8(i8 %a, i8 %b) {7; CHECK-LABEL: smaxi8:8; CHECK: @ %bb.0:9; CHECK-NEXT: sxtb r1, r110; CHECK-NEXT: sxtb r0, r011; CHECK-NEXT: cmp r0, r112; CHECK-NEXT: csel r0, r0, r1, gt13; CHECK-NEXT: bx lr14 %c = call i8 @llvm.smax.i8(i8 %a, i8 %b)15 ret i8 %c16}17 18declare i16 @llvm.smax.i16(i16 %a, i16 %b) readnone19 20define arm_aapcs_vfpcc i16 @smaxi16(i16 %a, i16 %b) {21; CHECK-LABEL: smaxi16:22; CHECK: @ %bb.0:23; CHECK-NEXT: sxth r1, r124; CHECK-NEXT: sxth r0, r025; CHECK-NEXT: cmp r0, r126; CHECK-NEXT: csel r0, r0, r1, gt27; CHECK-NEXT: bx lr28 %c = call i16 @llvm.smax.i16(i16 %a, i16 %b)29 ret i16 %c30}31 32declare i32 @llvm.smax.i32(i32 %a, i32 %b) readnone33 34define arm_aapcs_vfpcc i32 @smaxi32(i32 %a, i32 %b) {35; CHECK-LABEL: smaxi32:36; CHECK: @ %bb.0:37; CHECK-NEXT: cmp r0, r138; CHECK-NEXT: csel r0, r0, r1, gt39; CHECK-NEXT: bx lr40 %c = call i32 @llvm.smax.i32(i32 %a, i32 %b)41 ret i32 %c42}43 44declare i64 @llvm.smax.i64(i64 %a, i64 %b) readnone45 46define arm_aapcs_vfpcc i64 @smaxi64(i64 %a, i64 %b) {47; CHECK-LABEL: smaxi64:48; CHECK: @ %bb.0:49; CHECK-NEXT: subs.w r12, r2, r050; CHECK-NEXT: sbcs.w r12, r3, r151; CHECK-NEXT: csel r0, r0, r2, lt52; CHECK-NEXT: csel r1, r1, r3, lt53; CHECK-NEXT: bx lr54 %c = call i64 @llvm.smax.i64(i64 %a, i64 %b)55 ret i64 %c56}57 58declare <8 x i8> @llvm.smax.v8i8(<8 x i8> %a, <8 x i8> %b) readnone59 60define arm_aapcs_vfpcc <8 x i8> @smax8i8(<8 x i8> %a, <8 x i8> %b) {61; CHECK-LABEL: smax8i8:62; CHECK: @ %bb.0:63; CHECK-NEXT: vmovlb.s8 q1, q164; CHECK-NEXT: vmovlb.s8 q0, q065; CHECK-NEXT: vmax.s16 q0, q0, q166; CHECK-NEXT: bx lr67 %c = call <8 x i8> @llvm.smax.v8i8(<8 x i8> %a, <8 x i8> %b)68 ret <8 x i8> %c69}70 71declare <16 x i8> @llvm.smax.v16i8(<16 x i8> %a, <16 x i8> %b) readnone72 73define arm_aapcs_vfpcc <16 x i8> @smax16i8(<16 x i8> %a, <16 x i8> %b) {74; CHECK-LABEL: smax16i8:75; CHECK: @ %bb.0:76; CHECK-NEXT: vmax.s8 q0, q0, q177; CHECK-NEXT: bx lr78 %c = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %a, <16 x i8> %b)79 ret <16 x i8> %c80}81 82declare <32 x i8> @llvm.smax.v32i8(<32 x i8> %a, <32 x i8> %b) readnone83 84define arm_aapcs_vfpcc void @smax32i8(<32 x i8> %a, <32 x i8> %b, ptr %p) {85; CHECK-LABEL: smax32i8:86; CHECK: @ %bb.0:87; CHECK-NEXT: vmax.s8 q1, q1, q388; CHECK-NEXT: vmax.s8 q0, q0, q289; CHECK-NEXT: vstrw.32 q1, [r0, #16]90; CHECK-NEXT: vstrw.32 q0, [r0]91; CHECK-NEXT: bx lr92 %c = call <32 x i8> @llvm.smax.v32i8(<32 x i8> %a, <32 x i8> %b)93 store <32 x i8> %c, ptr %p94 ret void95}96 97declare <4 x i16> @llvm.smax.v4i16(<4 x i16> %a, <4 x i16> %b) readnone98 99define arm_aapcs_vfpcc <4 x i16> @smax4i16(<4 x i16> %a, <4 x i16> %b) {100; CHECK-LABEL: smax4i16:101; CHECK: @ %bb.0:102; CHECK-NEXT: vmovlb.s16 q1, q1103; CHECK-NEXT: vmovlb.s16 q0, q0104; CHECK-NEXT: vmax.s32 q0, q0, q1105; CHECK-NEXT: bx lr106 %c = call <4 x i16> @llvm.smax.v4i16(<4 x i16> %a, <4 x i16> %b)107 ret <4 x i16> %c108}109 110declare <8 x i16> @llvm.smax.v8i16(<8 x i16> %a, <8 x i16> %b) readnone111 112define arm_aapcs_vfpcc <8 x i16> @smax8i16(<8 x i16> %a, <8 x i16> %b) {113; CHECK-LABEL: smax8i16:114; CHECK: @ %bb.0:115; CHECK-NEXT: vmax.s16 q0, q0, q1116; CHECK-NEXT: bx lr117 %c = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %a, <8 x i16> %b)118 ret <8 x i16> %c119}120 121declare <16 x i16> @llvm.smax.v16i16(<16 x i16> %a, <16 x i16> %b) readnone122 123define arm_aapcs_vfpcc void @smax16i16(<16 x i16> %a, <16 x i16> %b, ptr %p) {124; CHECK-LABEL: smax16i16:125; CHECK: @ %bb.0:126; CHECK-NEXT: vmax.s16 q1, q1, q3127; CHECK-NEXT: vmax.s16 q0, q0, q2128; CHECK-NEXT: vstrw.32 q1, [r0, #16]129; CHECK-NEXT: vstrw.32 q0, [r0]130; CHECK-NEXT: bx lr131 %c = call <16 x i16> @llvm.smax.v16i16(<16 x i16> %a, <16 x i16> %b)132 store <16 x i16> %c, ptr %p133 ret void134}135 136declare <2 x i32> @llvm.smax.v2i32(<2 x i32> %a, <2 x i32> %b) readnone137 138define arm_aapcs_vfpcc <2 x i32> @smax2i32(<2 x i32> %a, <2 x i32> %b) {139; CHECK-LABEL: smax2i32:140; CHECK: @ %bb.0:141; CHECK-NEXT: .save {r4, r5, r7, lr}142; CHECK-NEXT: push {r4, r5, r7, lr}143; CHECK-NEXT: vmov r1, s4144; CHECK-NEXT: vmov r3, s0145; CHECK-NEXT: vmov r0, s6146; CHECK-NEXT: vmov r2, s2147; CHECK-NEXT: vmov q1[2], q1[0], r1, r0148; CHECK-NEXT: vmov q0[2], q0[0], r3, r2149; CHECK-NEXT: asr.w lr, r1, #31150; CHECK-NEXT: subs r1, r1, r3151; CHECK-NEXT: sbcs.w r1, lr, r3, asr #31152; CHECK-NEXT: asr.w r5, r3, #31153; CHECK-NEXT: asr.w r12, r0, #31154; CHECK-NEXT: csetm r1, lt155; CHECK-NEXT: subs r0, r0, r2156; CHECK-NEXT: mov.w r3, #0157; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31158; CHECK-NEXT: bfi r3, r1, #0, #8159; CHECK-NEXT: csetm r0, lt160; CHECK-NEXT: asrs r4, r2, #31161; CHECK-NEXT: bfi r3, r0, #8, #8162; CHECK-NEXT: vmov q1[3], q1[1], lr, r12163; CHECK-NEXT: vmov q0[3], q0[1], r5, r4164; CHECK-NEXT: vmsr p0, r3165; CHECK-NEXT: vpsel q0, q0, q1166; CHECK-NEXT: pop {r4, r5, r7, pc}167 %c = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %a, <2 x i32> %b)168 ret <2 x i32> %c169}170 171declare <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> %b) readnone172 173define arm_aapcs_vfpcc <4 x i32> @smax4i32(<4 x i32> %a, <4 x i32> %b) {174; CHECK-LABEL: smax4i32:175; CHECK: @ %bb.0:176; CHECK-NEXT: vmax.s32 q0, q0, q1177; CHECK-NEXT: bx lr178 %c = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> %b)179 ret <4 x i32> %c180}181 182declare <8 x i32> @llvm.smax.v8i32(<8 x i32> %a, <8 x i32> %b) readnone183 184define arm_aapcs_vfpcc void @smax8i32(<8 x i32> %a, <8 x i32> %b, ptr %p) {185; CHECK-LABEL: smax8i32:186; CHECK: @ %bb.0:187; CHECK-NEXT: vmax.s32 q1, q1, q3188; CHECK-NEXT: vmax.s32 q0, q0, q2189; CHECK-NEXT: vstrw.32 q1, [r0, #16]190; CHECK-NEXT: vstrw.32 q0, [r0]191; CHECK-NEXT: bx lr192 %c = call <8 x i32>@llvm.smax.v8i32(<8 x i32> %a, <8 x i32> %b)193 store <8 x i32> %c, ptr %p194 ret void195}196 197declare <1 x i64> @llvm.smax.v1i64(<1 x i64> %a, <1 x i64> %b) readnone198 199define arm_aapcs_vfpcc <1 x i64> @smax1i64(<1 x i64> %a, <1 x i64> %b) {200; CHECK-LABEL: smax1i64:201; CHECK: @ %bb.0:202; CHECK-NEXT: .pad #8203; CHECK-NEXT: sub sp, #8204; CHECK-NEXT: subs.w r12, r2, r0205; CHECK-NEXT: sbcs.w r12, r3, r1206; CHECK-NEXT: csel r0, r0, r2, lt207; CHECK-NEXT: csel r1, r1, r3, lt208; CHECK-NEXT: add sp, #8209; CHECK-NEXT: bx lr210 %c = call <1 x i64> @llvm.smax.v1i64(<1 x i64> %a, <1 x i64> %b)211 ret <1 x i64> %c212}213 214declare <2 x i64> @llvm.smax.v2i64(<2 x i64> %a, <2 x i64> %b) readnone215 216define arm_aapcs_vfpcc <2 x i64> @smax2i64(<2 x i64> %a, <2 x i64> %b) {217; CHECK-LABEL: smax2i64:218; CHECK: @ %bb.0:219; CHECK-NEXT: vmov r0, r1, d0220; CHECK-NEXT: vmov r2, r3, d2221; CHECK-NEXT: subs r0, r2, r0222; CHECK-NEXT: sbcs.w r0, r3, r1223; CHECK-NEXT: mov.w r1, #0224; CHECK-NEXT: csetm r0, lt225; CHECK-NEXT: vmov r3, r2, d3226; CHECK-NEXT: bfi r1, r0, #0, #8227; CHECK-NEXT: vmov r0, r12, d1228; CHECK-NEXT: subs r0, r3, r0229; CHECK-NEXT: sbcs.w r0, r2, r12230; CHECK-NEXT: csetm r0, lt231; CHECK-NEXT: bfi r1, r0, #8, #8232; CHECK-NEXT: vmsr p0, r1233; CHECK-NEXT: vpsel q0, q0, q1234; CHECK-NEXT: bx lr235 %c = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %a, <2 x i64> %b)236 ret <2 x i64> %c237}238 239declare <4 x i64> @llvm.smax.v4i64(<4 x i64> %a, <4 x i64> %b) readnone240 241define arm_aapcs_vfpcc void @smax4i64(<4 x i64> %a, <4 x i64> %b, ptr %p) {242; CHECK-LABEL: smax4i64:243; CHECK: @ %bb.0:244; CHECK-NEXT: .save {r4, lr}245; CHECK-NEXT: push {r4, lr}246; CHECK-NEXT: vmov r1, r12, d2247; CHECK-NEXT: vmov r3, r2, d6248; CHECK-NEXT: subs r1, r3, r1249; CHECK-NEXT: mov.w r3, #0250; CHECK-NEXT: sbcs.w r1, r2, r12251; CHECK-NEXT: vmov lr, r12, d3252; CHECK-NEXT: csetm r2, lt253; CHECK-NEXT: movs r1, #0254; CHECK-NEXT: bfi r3, r2, #0, #8255; CHECK-NEXT: vmov r2, r4, d7256; CHECK-NEXT: subs.w r2, r2, lr257; CHECK-NEXT: sbcs.w r2, r4, r12258; CHECK-NEXT: csetm r2, lt259; CHECK-NEXT: bfi r3, r2, #8, #8260; CHECK-NEXT: vmov r2, r12, d0261; CHECK-NEXT: vmsr p0, r3262; CHECK-NEXT: vmov r4, r3, d4263; CHECK-NEXT: vpsel q1, q1, q3264; CHECK-NEXT: vstrw.32 q1, [r0, #16]265; CHECK-NEXT: subs r2, r4, r2266; CHECK-NEXT: sbcs.w r2, r3, r12267; CHECK-NEXT: vmov r4, r3, d5268; CHECK-NEXT: csetm r2, lt269; CHECK-NEXT: bfi r1, r2, #0, #8270; CHECK-NEXT: vmov r2, r12, d1271; CHECK-NEXT: subs r2, r4, r2272; CHECK-NEXT: sbcs.w r2, r3, r12273; CHECK-NEXT: csetm r2, lt274; CHECK-NEXT: bfi r1, r2, #8, #8275; CHECK-NEXT: vmsr p0, r1276; CHECK-NEXT: vpsel q0, q0, q2277; CHECK-NEXT: vstrw.32 q0, [r0]278; CHECK-NEXT: pop {r4, pc}279 %c = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %a, <4 x i64> %b)280 store <4 x i64> %c, ptr %p281 ret void282}283 284declare i8 @llvm.umax.i8(i8 %a, i8 %b) readnone285 286define arm_aapcs_vfpcc i8 @umaxi8(i8 %a, i8 %b) {287; CHECK-LABEL: umaxi8:288; CHECK: @ %bb.0:289; CHECK-NEXT: uxtb r1, r1290; CHECK-NEXT: uxtb r0, r0291; CHECK-NEXT: cmp r0, r1292; CHECK-NEXT: csel r0, r0, r1, hi293; CHECK-NEXT: bx lr294 %c = call i8 @llvm.umax.i8(i8 %a, i8 %b)295 ret i8 %c296}297 298declare i16 @llvm.umax.i16(i16 %a, i16 %b) readnone299 300define arm_aapcs_vfpcc i16 @umaxi16(i16 %a, i16 %b) {301; CHECK-LABEL: umaxi16:302; CHECK: @ %bb.0:303; CHECK-NEXT: uxth r1, r1304; CHECK-NEXT: uxth r0, r0305; CHECK-NEXT: cmp r0, r1306; CHECK-NEXT: csel r0, r0, r1, hi307; CHECK-NEXT: bx lr308 %c = call i16 @llvm.umax.i16(i16 %a, i16 %b)309 ret i16 %c310}311 312declare i32 @llvm.umax.i32(i32 %a, i32 %b) readnone313 314define arm_aapcs_vfpcc i32 @umaxi32(i32 %a, i32 %b) {315; CHECK-LABEL: umaxi32:316; CHECK: @ %bb.0:317; CHECK-NEXT: cmp r0, r1318; CHECK-NEXT: csel r0, r0, r1, hi319; CHECK-NEXT: bx lr320 %c = call i32 @llvm.umax.i32(i32 %a, i32 %b)321 ret i32 %c322}323 324declare i64 @llvm.umax.i64(i64 %a, i64 %b) readnone325 326define arm_aapcs_vfpcc i64 @umaxi64(i64 %a, i64 %b) {327; CHECK-LABEL: umaxi64:328; CHECK: @ %bb.0:329; CHECK-NEXT: subs.w r12, r2, r0330; CHECK-NEXT: sbcs.w r12, r3, r1331; CHECK-NEXT: csel r0, r0, r2, lo332; CHECK-NEXT: csel r1, r1, r3, lo333; CHECK-NEXT: bx lr334 %c = call i64 @llvm.umax.i64(i64 %a, i64 %b)335 ret i64 %c336}337 338declare <8 x i8> @llvm.umax.v8i8(<8 x i8> %a, <8 x i8> %b) readnone339 340define arm_aapcs_vfpcc <8 x i8> @umax8i8(<8 x i8> %a, <8 x i8> %b) {341; CHECK-LABEL: umax8i8:342; CHECK: @ %bb.0:343; CHECK-NEXT: vmovlb.u8 q1, q1344; CHECK-NEXT: vmovlb.u8 q0, q0345; CHECK-NEXT: vmax.u16 q0, q0, q1346; CHECK-NEXT: bx lr347 %c = call <8 x i8> @llvm.umax.v8i8(<8 x i8> %a, <8 x i8> %b)348 ret <8 x i8> %c349}350 351declare <16 x i8> @llvm.umax.v16i8(<16 x i8> %a, <16 x i8> %b) readnone352 353define arm_aapcs_vfpcc <16 x i8> @umax16i8(<16 x i8> %a, <16 x i8> %b) {354; CHECK-LABEL: umax16i8:355; CHECK: @ %bb.0:356; CHECK-NEXT: vmax.u8 q0, q0, q1357; CHECK-NEXT: bx lr358 %c = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %a, <16 x i8> %b)359 ret <16 x i8> %c360}361 362declare <32 x i8> @llvm.umax.v32i8(<32 x i8> %a, <32 x i8> %b) readnone363 364define arm_aapcs_vfpcc void @umax32i8(<32 x i8> %a, <32 x i8> %b, ptr %p) {365; CHECK-LABEL: umax32i8:366; CHECK: @ %bb.0:367; CHECK-NEXT: vmax.u8 q1, q1, q3368; CHECK-NEXT: vmax.u8 q0, q0, q2369; CHECK-NEXT: vstrw.32 q1, [r0, #16]370; CHECK-NEXT: vstrw.32 q0, [r0]371; CHECK-NEXT: bx lr372 %c = call <32 x i8> @llvm.umax.v32i8(<32 x i8> %a, <32 x i8> %b)373 store <32 x i8> %c, ptr %p374 ret void375}376 377declare <4 x i16> @llvm.umax.v4i16(<4 x i16> %a, <4 x i16> %b) readnone378 379define arm_aapcs_vfpcc <4 x i16> @umax4i16(<4 x i16> %a, <4 x i16> %b) {380; CHECK-LABEL: umax4i16:381; CHECK: @ %bb.0:382; CHECK-NEXT: vmovlb.u16 q1, q1383; CHECK-NEXT: vmovlb.u16 q0, q0384; CHECK-NEXT: vmax.u32 q0, q0, q1385; CHECK-NEXT: bx lr386 %c = call <4 x i16> @llvm.umax.v4i16(<4 x i16> %a, <4 x i16> %b)387 ret <4 x i16> %c388}389 390declare <8 x i16> @llvm.umax.v8i16(<8 x i16> %a, <8 x i16> %b) readnone391 392define arm_aapcs_vfpcc <8 x i16> @umax8i16(<8 x i16> %a, <8 x i16> %b) {393; CHECK-LABEL: umax8i16:394; CHECK: @ %bb.0:395; CHECK-NEXT: vmax.u16 q0, q0, q1396; CHECK-NEXT: bx lr397 %c = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %a, <8 x i16> %b)398 ret <8 x i16> %c399}400 401declare <16 x i16> @llvm.umax.v16i16(<16 x i16> %a, <16 x i16> %b) readnone402 403define arm_aapcs_vfpcc void @umax16i16(<16 x i16> %a, <16 x i16> %b, ptr %p) {404; CHECK-LABEL: umax16i16:405; CHECK: @ %bb.0:406; CHECK-NEXT: vmax.u16 q1, q1, q3407; CHECK-NEXT: vmax.u16 q0, q0, q2408; CHECK-NEXT: vstrw.32 q1, [r0, #16]409; CHECK-NEXT: vstrw.32 q0, [r0]410; CHECK-NEXT: bx lr411 %c = call <16 x i16> @llvm.umax.v16i16(<16 x i16> %a, <16 x i16> %b)412 store <16 x i16> %c, ptr %p413 ret void414}415 416declare <2 x i32> @llvm.umax.v2i32(<2 x i32> %a, <2 x i32> %b) readnone417 418define arm_aapcs_vfpcc <2 x i32> @umax2i32(<2 x i32> %a, <2 x i32> %b) {419; CHECK-LABEL: umax2i32:420; CHECK: @ %bb.0:421; CHECK-NEXT: vmov.i64 q2, #0xffffffff422; CHECK-NEXT: vand q0, q0, q2423; CHECK-NEXT: vand q1, q1, q2424; CHECK-NEXT: vmov r0, r1, d0425; CHECK-NEXT: vmov r2, r3, d2426; CHECK-NEXT: subs r0, r2, r0427; CHECK-NEXT: sbcs.w r0, r3, r1428; CHECK-NEXT: mov.w r1, #0429; CHECK-NEXT: csetm r0, lo430; CHECK-NEXT: vmov r3, r2, d3431; CHECK-NEXT: bfi r1, r0, #0, #8432; CHECK-NEXT: vmov r0, r12, d1433; CHECK-NEXT: subs r0, r3, r0434; CHECK-NEXT: sbcs.w r0, r2, r12435; CHECK-NEXT: csetm r0, lo436; CHECK-NEXT: bfi r1, r0, #8, #8437; CHECK-NEXT: vmsr p0, r1438; CHECK-NEXT: vpsel q0, q0, q1439; CHECK-NEXT: bx lr440 %c = call <2 x i32> @llvm.umax.v2i32(<2 x i32> %a, <2 x i32> %b)441 ret <2 x i32> %c442}443 444declare <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> %b) readnone445 446define arm_aapcs_vfpcc <4 x i32> @umax4i32(<4 x i32> %a, <4 x i32> %b) {447; CHECK-LABEL: umax4i32:448; CHECK: @ %bb.0:449; CHECK-NEXT: vmax.u32 q0, q0, q1450; CHECK-NEXT: bx lr451 %c = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> %b)452 ret <4 x i32> %c453}454 455declare <8 x i32> @llvm.umax.v8i32(<8 x i32> %a, <8 x i32> %b) readnone456 457define arm_aapcs_vfpcc void @umax8i32(<8 x i32> %a, <8 x i32> %b, ptr %p) {458; CHECK-LABEL: umax8i32:459; CHECK: @ %bb.0:460; CHECK-NEXT: vmax.u32 q1, q1, q3461; CHECK-NEXT: vmax.u32 q0, q0, q2462; CHECK-NEXT: vstrw.32 q1, [r0, #16]463; CHECK-NEXT: vstrw.32 q0, [r0]464; CHECK-NEXT: bx lr465 %c = call <8 x i32>@llvm.umax.v8i32(<8 x i32> %a, <8 x i32> %b)466 store <8 x i32> %c, ptr %p467 ret void468}469 470declare <1 x i64> @llvm.umax.v1i64(<1 x i64> %a, <1 x i64> %b) readnone471 472define arm_aapcs_vfpcc <1 x i64> @umax1i64(<1 x i64> %a, <1 x i64> %b) {473; CHECK-LABEL: umax1i64:474; CHECK: @ %bb.0:475; CHECK-NEXT: .pad #8476; CHECK-NEXT: sub sp, #8477; CHECK-NEXT: subs.w r12, r2, r0478; CHECK-NEXT: sbcs.w r12, r3, r1479; CHECK-NEXT: csel r0, r0, r2, lo480; CHECK-NEXT: csel r1, r1, r3, lo481; CHECK-NEXT: add sp, #8482; CHECK-NEXT: bx lr483 %c = call <1 x i64> @llvm.umax.v1i64(<1 x i64> %a, <1 x i64> %b)484 ret <1 x i64> %c485}486 487declare <2 x i64> @llvm.umax.v2i64(<2 x i64> %a, <2 x i64> %b) readnone488 489define arm_aapcs_vfpcc <2 x i64> @umax2i64(<2 x i64> %a, <2 x i64> %b) {490; CHECK-LABEL: umax2i64:491; CHECK: @ %bb.0:492; CHECK-NEXT: vmov r0, r1, d0493; CHECK-NEXT: vmov r2, r3, d2494; CHECK-NEXT: subs r0, r2, r0495; CHECK-NEXT: sbcs.w r0, r3, r1496; CHECK-NEXT: mov.w r1, #0497; CHECK-NEXT: csetm r0, lo498; CHECK-NEXT: vmov r3, r2, d3499; CHECK-NEXT: bfi r1, r0, #0, #8500; CHECK-NEXT: vmov r0, r12, d1501; CHECK-NEXT: subs r0, r3, r0502; CHECK-NEXT: sbcs.w r0, r2, r12503; CHECK-NEXT: csetm r0, lo504; CHECK-NEXT: bfi r1, r0, #8, #8505; CHECK-NEXT: vmsr p0, r1506; CHECK-NEXT: vpsel q0, q0, q1507; CHECK-NEXT: bx lr508 %c = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %a, <2 x i64> %b)509 ret <2 x i64> %c510}511 512declare <4 x i64> @llvm.umax.v4i64(<4 x i64> %a, <4 x i64> %b) readnone513 514define arm_aapcs_vfpcc void @umax4i64(<4 x i64> %a, <4 x i64> %b, ptr %p) {515; CHECK-LABEL: umax4i64:516; CHECK: @ %bb.0:517; CHECK-NEXT: .save {r4, lr}518; CHECK-NEXT: push {r4, lr}519; CHECK-NEXT: vmov r1, r12, d2520; CHECK-NEXT: vmov r3, r2, d6521; CHECK-NEXT: subs r1, r3, r1522; CHECK-NEXT: mov.w r3, #0523; CHECK-NEXT: sbcs.w r1, r2, r12524; CHECK-NEXT: vmov lr, r12, d3525; CHECK-NEXT: csetm r2, lo526; CHECK-NEXT: movs r1, #0527; CHECK-NEXT: bfi r3, r2, #0, #8528; CHECK-NEXT: vmov r2, r4, d7529; CHECK-NEXT: subs.w r2, r2, lr530; CHECK-NEXT: sbcs.w r2, r4, r12531; CHECK-NEXT: csetm r2, lo532; CHECK-NEXT: bfi r3, r2, #8, #8533; CHECK-NEXT: vmov r2, r12, d0534; CHECK-NEXT: vmsr p0, r3535; CHECK-NEXT: vmov r4, r3, d4536; CHECK-NEXT: vpsel q1, q1, q3537; CHECK-NEXT: vstrw.32 q1, [r0, #16]538; CHECK-NEXT: subs r2, r4, r2539; CHECK-NEXT: sbcs.w r2, r3, r12540; CHECK-NEXT: vmov r4, r3, d5541; CHECK-NEXT: csetm r2, lo542; CHECK-NEXT: bfi r1, r2, #0, #8543; CHECK-NEXT: vmov r2, r12, d1544; CHECK-NEXT: subs r2, r4, r2545; CHECK-NEXT: sbcs.w r2, r3, r12546; CHECK-NEXT: csetm r2, lo547; CHECK-NEXT: bfi r1, r2, #8, #8548; CHECK-NEXT: vmsr p0, r1549; CHECK-NEXT: vpsel q0, q0, q2550; CHECK-NEXT: vstrw.32 q0, [r0]551; CHECK-NEXT: pop {r4, pc}552 %c = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %a, <4 x i64> %b)553 store <4 x i64> %c, ptr %p554 ret void555}556 557declare i8 @llvm.smin.i8(i8 %a, i8 %b) readnone558 559define arm_aapcs_vfpcc i8 @smini8(i8 %a, i8 %b) {560; CHECK-LABEL: smini8:561; CHECK: @ %bb.0:562; CHECK-NEXT: sxtb r1, r1563; CHECK-NEXT: sxtb r0, r0564; CHECK-NEXT: cmp r0, r1565; CHECK-NEXT: csel r0, r0, r1, lt566; CHECK-NEXT: bx lr567 %c = call i8 @llvm.smin.i8(i8 %a, i8 %b)568 ret i8 %c569}570 571declare i16 @llvm.smin.i16(i16 %a, i16 %b) readnone572 573define arm_aapcs_vfpcc i16 @smini16(i16 %a, i16 %b) {574; CHECK-LABEL: smini16:575; CHECK: @ %bb.0:576; CHECK-NEXT: sxth r1, r1577; CHECK-NEXT: sxth r0, r0578; CHECK-NEXT: cmp r0, r1579; CHECK-NEXT: csel r0, r0, r1, lt580; CHECK-NEXT: bx lr581 %c = call i16 @llvm.smin.i16(i16 %a, i16 %b)582 ret i16 %c583}584 585declare i32 @llvm.smin.i32(i32 %a, i32 %b) readnone586 587define arm_aapcs_vfpcc i32 @smini32(i32 %a, i32 %b) {588; CHECK-LABEL: smini32:589; CHECK: @ %bb.0:590; CHECK-NEXT: cmp r0, r1591; CHECK-NEXT: csel r0, r0, r1, lt592; CHECK-NEXT: bx lr593 %c = call i32 @llvm.smin.i32(i32 %a, i32 %b)594 ret i32 %c595}596 597declare i64 @llvm.smin.i64(i64 %a, i64 %b) readnone598 599define arm_aapcs_vfpcc i64 @smini64(i64 %a, i64 %b) {600; CHECK-LABEL: smini64:601; CHECK: @ %bb.0:602; CHECK-NEXT: subs.w r12, r0, r2603; CHECK-NEXT: sbcs.w r12, r1, r3604; CHECK-NEXT: csel r0, r0, r2, lt605; CHECK-NEXT: csel r1, r1, r3, lt606; CHECK-NEXT: bx lr607 %c = call i64 @llvm.smin.i64(i64 %a, i64 %b)608 ret i64 %c609}610 611declare <8 x i8> @llvm.smin.v8i8(<8 x i8> %a, <8 x i8> %b) readnone612 613define arm_aapcs_vfpcc <8 x i8> @smin8i8(<8 x i8> %a, <8 x i8> %b) {614; CHECK-LABEL: smin8i8:615; CHECK: @ %bb.0:616; CHECK-NEXT: vmovlb.s8 q1, q1617; CHECK-NEXT: vmovlb.s8 q0, q0618; CHECK-NEXT: vmin.s16 q0, q0, q1619; CHECK-NEXT: bx lr620 %c = call <8 x i8> @llvm.smin.v8i8(<8 x i8> %a, <8 x i8> %b)621 ret <8 x i8> %c622}623 624declare <16 x i8> @llvm.smin.v16i8(<16 x i8> %a, <16 x i8> %b) readnone625 626define arm_aapcs_vfpcc <16 x i8> @smin16i8(<16 x i8> %a, <16 x i8> %b) {627; CHECK-LABEL: smin16i8:628; CHECK: @ %bb.0:629; CHECK-NEXT: vmin.s8 q0, q0, q1630; CHECK-NEXT: bx lr631 %c = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %a, <16 x i8> %b)632 ret <16 x i8> %c633}634 635declare <32 x i8> @llvm.smin.v32i8(<32 x i8> %a, <32 x i8> %b) readnone636 637define arm_aapcs_vfpcc void @smin32i8(<32 x i8> %a, <32 x i8> %b, ptr %p) {638; CHECK-LABEL: smin32i8:639; CHECK: @ %bb.0:640; CHECK-NEXT: vmin.s8 q1, q1, q3641; CHECK-NEXT: vmin.s8 q0, q0, q2642; CHECK-NEXT: vstrw.32 q1, [r0, #16]643; CHECK-NEXT: vstrw.32 q0, [r0]644; CHECK-NEXT: bx lr645 %c = call <32 x i8> @llvm.smin.v32i8(<32 x i8> %a, <32 x i8> %b)646 store <32 x i8> %c, ptr %p647 ret void648}649 650declare <4 x i16> @llvm.smin.v4i16(<4 x i16> %a, <4 x i16> %b) readnone651 652define arm_aapcs_vfpcc <4 x i16> @smin4i16(<4 x i16> %a, <4 x i16> %b) {653; CHECK-LABEL: smin4i16:654; CHECK: @ %bb.0:655; CHECK-NEXT: vmovlb.s16 q1, q1656; CHECK-NEXT: vmovlb.s16 q0, q0657; CHECK-NEXT: vmin.s32 q0, q0, q1658; CHECK-NEXT: bx lr659 %c = call <4 x i16> @llvm.smin.v4i16(<4 x i16> %a, <4 x i16> %b)660 ret <4 x i16> %c661}662 663declare <8 x i16> @llvm.smin.v8i16(<8 x i16> %a, <8 x i16> %b) readnone664 665define arm_aapcs_vfpcc <8 x i16> @smin8i16(<8 x i16> %a, <8 x i16> %b) {666; CHECK-LABEL: smin8i16:667; CHECK: @ %bb.0:668; CHECK-NEXT: vmin.s16 q0, q0, q1669; CHECK-NEXT: bx lr670 %c = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %a, <8 x i16> %b)671 ret <8 x i16> %c672}673 674declare <16 x i16> @llvm.smin.v16i16(<16 x i16> %a, <16 x i16> %b) readnone675 676define arm_aapcs_vfpcc void @smin16i16(<16 x i16> %a, <16 x i16> %b, ptr %p) {677; CHECK-LABEL: smin16i16:678; CHECK: @ %bb.0:679; CHECK-NEXT: vmin.s16 q1, q1, q3680; CHECK-NEXT: vmin.s16 q0, q0, q2681; CHECK-NEXT: vstrw.32 q1, [r0, #16]682; CHECK-NEXT: vstrw.32 q0, [r0]683; CHECK-NEXT: bx lr684 %c = call <16 x i16> @llvm.smin.v16i16(<16 x i16> %a, <16 x i16> %b)685 store <16 x i16> %c, ptr %p686 ret void687}688 689declare <2 x i32> @llvm.smin.v2i32(<2 x i32> %a, <2 x i32> %b) readnone690 691define arm_aapcs_vfpcc <2 x i32> @smin2i32(<2 x i32> %a, <2 x i32> %b) {692; CHECK-LABEL: smin2i32:693; CHECK: @ %bb.0:694; CHECK-NEXT: .save {r7, lr}695; CHECK-NEXT: push {r7, lr}696; CHECK-NEXT: vmov r0, s6697; CHECK-NEXT: vmov r1, s4698; CHECK-NEXT: vmov q1[2], q1[0], r1, r0699; CHECK-NEXT: asrs r2, r0, #31700; CHECK-NEXT: asrs r3, r1, #31701; CHECK-NEXT: vmov q1[3], q1[1], r3, r2702; CHECK-NEXT: vmov r3, s0703; CHECK-NEXT: vmov r2, s2704; CHECK-NEXT: vmov q0[2], q0[0], r3, r2705; CHECK-NEXT: asr.w lr, r3, #31706; CHECK-NEXT: subs r3, r3, r1707; CHECK-NEXT: sbcs.w r1, lr, r1, asr #31708; CHECK-NEXT: mov.w r3, #0709; CHECK-NEXT: csetm r1, lt710; CHECK-NEXT: asr.w r12, r2, #31711; CHECK-NEXT: bfi r3, r1, #0, #8712; CHECK-NEXT: subs r1, r2, r0713; CHECK-NEXT: sbcs.w r0, r12, r0, asr #31714; CHECK-NEXT: vmov q0[3], q0[1], lr, r12715; CHECK-NEXT: csetm r0, lt716; CHECK-NEXT: bfi r3, r0, #8, #8717; CHECK-NEXT: vmsr p0, r3718; CHECK-NEXT: vpsel q0, q0, q1719; CHECK-NEXT: pop {r7, pc}720 %c = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %a, <2 x i32> %b)721 ret <2 x i32> %c722}723 724declare <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> %b) readnone725 726define arm_aapcs_vfpcc <4 x i32> @smin4i32(<4 x i32> %a, <4 x i32> %b) {727; CHECK-LABEL: smin4i32:728; CHECK: @ %bb.0:729; CHECK-NEXT: vmin.s32 q0, q0, q1730; CHECK-NEXT: bx lr731 %c = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> %b)732 ret <4 x i32> %c733}734 735declare <8 x i32> @llvm.smin.v8i32(<8 x i32> %a, <8 x i32> %b) readnone736 737define arm_aapcs_vfpcc void @smin8i32(<8 x i32> %a, <8 x i32> %b, ptr %p) {738; CHECK-LABEL: smin8i32:739; CHECK: @ %bb.0:740; CHECK-NEXT: vmin.s32 q1, q1, q3741; CHECK-NEXT: vmin.s32 q0, q0, q2742; CHECK-NEXT: vstrw.32 q1, [r0, #16]743; CHECK-NEXT: vstrw.32 q0, [r0]744; CHECK-NEXT: bx lr745 %c = call <8 x i32>@llvm.smin.v8i32(<8 x i32> %a, <8 x i32> %b)746 store <8 x i32> %c, ptr %p747 ret void748}749 750declare <1 x i64> @llvm.smin.v1i64(<1 x i64> %a, <1 x i64> %b) readnone751 752define arm_aapcs_vfpcc <1 x i64> @smin1i64(<1 x i64> %a, <1 x i64> %b) {753; CHECK-LABEL: smin1i64:754; CHECK: @ %bb.0:755; CHECK-NEXT: .pad #8756; CHECK-NEXT: sub sp, #8757; CHECK-NEXT: subs.w r12, r0, r2758; CHECK-NEXT: sbcs.w r12, r1, r3759; CHECK-NEXT: csel r0, r0, r2, lt760; CHECK-NEXT: csel r1, r1, r3, lt761; CHECK-NEXT: add sp, #8762; CHECK-NEXT: bx lr763 %c = call <1 x i64> @llvm.smin.v1i64(<1 x i64> %a, <1 x i64> %b)764 ret <1 x i64> %c765}766 767declare <2 x i64> @llvm.smin.v2i64(<2 x i64> %a, <2 x i64> %b) readnone768 769define arm_aapcs_vfpcc <2 x i64> @smin2i64(<2 x i64> %a, <2 x i64> %b) {770; CHECK-LABEL: smin2i64:771; CHECK: @ %bb.0:772; CHECK-NEXT: vmov r0, r1, d2773; CHECK-NEXT: vmov r2, r3, d0774; CHECK-NEXT: subs r0, r2, r0775; CHECK-NEXT: sbcs.w r0, r3, r1776; CHECK-NEXT: mov.w r1, #0777; CHECK-NEXT: csetm r0, lt778; CHECK-NEXT: vmov r3, r2, d1779; CHECK-NEXT: bfi r1, r0, #0, #8780; CHECK-NEXT: vmov r0, r12, d3781; CHECK-NEXT: subs r0, r3, r0782; CHECK-NEXT: sbcs.w r0, r2, r12783; CHECK-NEXT: csetm r0, lt784; CHECK-NEXT: bfi r1, r0, #8, #8785; CHECK-NEXT: vmsr p0, r1786; CHECK-NEXT: vpsel q0, q0, q1787; CHECK-NEXT: bx lr788 %c = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %a, <2 x i64> %b)789 ret <2 x i64> %c790}791 792declare <4 x i64> @llvm.smin.v4i64(<4 x i64> %a, <4 x i64> %b) readnone793 794define arm_aapcs_vfpcc void @smin4i64(<4 x i64> %a, <4 x i64> %b, ptr %p) {795; CHECK-LABEL: smin4i64:796; CHECK: @ %bb.0:797; CHECK-NEXT: .save {r4, lr}798; CHECK-NEXT: push {r4, lr}799; CHECK-NEXT: vmov r1, r12, d6800; CHECK-NEXT: vmov r3, r2, d2801; CHECK-NEXT: subs r1, r3, r1802; CHECK-NEXT: mov.w r3, #0803; CHECK-NEXT: sbcs.w r1, r2, r12804; CHECK-NEXT: vmov lr, r12, d7805; CHECK-NEXT: csetm r2, lt806; CHECK-NEXT: movs r1, #0807; CHECK-NEXT: bfi r3, r2, #0, #8808; CHECK-NEXT: vmov r2, r4, d3809; CHECK-NEXT: subs.w r2, r2, lr810; CHECK-NEXT: sbcs.w r2, r4, r12811; CHECK-NEXT: csetm r2, lt812; CHECK-NEXT: bfi r3, r2, #8, #8813; CHECK-NEXT: vmov r2, r12, d4814; CHECK-NEXT: vmsr p0, r3815; CHECK-NEXT: vmov r4, r3, d0816; CHECK-NEXT: vpsel q1, q1, q3817; CHECK-NEXT: vstrw.32 q1, [r0, #16]818; CHECK-NEXT: subs r2, r4, r2819; CHECK-NEXT: sbcs.w r2, r3, r12820; CHECK-NEXT: vmov r4, r3, d1821; CHECK-NEXT: csetm r2, lt822; CHECK-NEXT: bfi r1, r2, #0, #8823; CHECK-NEXT: vmov r2, r12, d5824; CHECK-NEXT: subs r2, r4, r2825; CHECK-NEXT: sbcs.w r2, r3, r12826; CHECK-NEXT: csetm r2, lt827; CHECK-NEXT: bfi r1, r2, #8, #8828; CHECK-NEXT: vmsr p0, r1829; CHECK-NEXT: vpsel q0, q0, q2830; CHECK-NEXT: vstrw.32 q0, [r0]831; CHECK-NEXT: pop {r4, pc}832 %c = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %a, <4 x i64> %b)833 store <4 x i64> %c, ptr %p834 ret void835}836 837declare i8 @llvm.umin.i8(i8 %a, i8 %b) readnone838 839define arm_aapcs_vfpcc i8 @umini8(i8 %a, i8 %b) {840; CHECK-LABEL: umini8:841; CHECK: @ %bb.0:842; CHECK-NEXT: uxtb r1, r1843; CHECK-NEXT: uxtb r0, r0844; CHECK-NEXT: cmp r0, r1845; CHECK-NEXT: csel r0, r0, r1, lo846; CHECK-NEXT: bx lr847 %c = call i8 @llvm.umin.i8(i8 %a, i8 %b)848 ret i8 %c849}850 851declare i16 @llvm.umin.i16(i16 %a, i16 %b) readnone852 853define arm_aapcs_vfpcc i16 @umini16(i16 %a, i16 %b) {854; CHECK-LABEL: umini16:855; CHECK: @ %bb.0:856; CHECK-NEXT: uxth r1, r1857; CHECK-NEXT: uxth r0, r0858; CHECK-NEXT: cmp r0, r1859; CHECK-NEXT: csel r0, r0, r1, lo860; CHECK-NEXT: bx lr861 %c = call i16 @llvm.umin.i16(i16 %a, i16 %b)862 ret i16 %c863}864 865declare i32 @llvm.umin.i32(i32 %a, i32 %b) readnone866 867define arm_aapcs_vfpcc i32 @umini32(i32 %a, i32 %b) {868; CHECK-LABEL: umini32:869; CHECK: @ %bb.0:870; CHECK-NEXT: cmp r0, r1871; CHECK-NEXT: csel r0, r0, r1, lo872; CHECK-NEXT: bx lr873 %c = call i32 @llvm.umin.i32(i32 %a, i32 %b)874 ret i32 %c875}876 877declare i64 @llvm.umin.i64(i64 %a, i64 %b) readnone878 879define arm_aapcs_vfpcc i64 @umini64(i64 %a, i64 %b) {880; CHECK-LABEL: umini64:881; CHECK: @ %bb.0:882; CHECK-NEXT: subs.w r12, r0, r2883; CHECK-NEXT: sbcs.w r12, r1, r3884; CHECK-NEXT: csel r0, r0, r2, lo885; CHECK-NEXT: csel r1, r1, r3, lo886; CHECK-NEXT: bx lr887 %c = call i64 @llvm.umin.i64(i64 %a, i64 %b)888 ret i64 %c889}890 891declare <8 x i8> @llvm.umin.v8i8(<8 x i8> %a, <8 x i8> %b) readnone892 893define arm_aapcs_vfpcc <8 x i8> @umin8i8(<8 x i8> %a, <8 x i8> %b) {894; CHECK-LABEL: umin8i8:895; CHECK: @ %bb.0:896; CHECK-NEXT: vmovlb.u8 q1, q1897; CHECK-NEXT: vmovlb.u8 q0, q0898; CHECK-NEXT: vmin.u16 q0, q0, q1899; CHECK-NEXT: bx lr900 %c = call <8 x i8> @llvm.umin.v8i8(<8 x i8> %a, <8 x i8> %b)901 ret <8 x i8> %c902}903 904declare <16 x i8> @llvm.umin.v16i8(<16 x i8> %a, <16 x i8> %b) readnone905 906define arm_aapcs_vfpcc <16 x i8> @umin16i8(<16 x i8> %a, <16 x i8> %b) {907; CHECK-LABEL: umin16i8:908; CHECK: @ %bb.0:909; CHECK-NEXT: vmin.u8 q0, q0, q1910; CHECK-NEXT: bx lr911 %c = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %a, <16 x i8> %b)912 ret <16 x i8> %c913}914 915declare <32 x i8> @llvm.umin.v32i8(<32 x i8> %a, <32 x i8> %b) readnone916 917define arm_aapcs_vfpcc void @umin32i8(<32 x i8> %a, <32 x i8> %b, ptr %p) {918; CHECK-LABEL: umin32i8:919; CHECK: @ %bb.0:920; CHECK-NEXT: vmin.u8 q1, q1, q3921; CHECK-NEXT: vmin.u8 q0, q0, q2922; CHECK-NEXT: vstrw.32 q1, [r0, #16]923; CHECK-NEXT: vstrw.32 q0, [r0]924; CHECK-NEXT: bx lr925 %c = call <32 x i8> @llvm.umin.v32i8(<32 x i8> %a, <32 x i8> %b)926 store <32 x i8> %c, ptr %p927 ret void928}929 930declare <4 x i16> @llvm.umin.v4i16(<4 x i16> %a, <4 x i16> %b) readnone931 932define arm_aapcs_vfpcc <4 x i16> @umin4i16(<4 x i16> %a, <4 x i16> %b) {933; CHECK-LABEL: umin4i16:934; CHECK: @ %bb.0:935; CHECK-NEXT: vmovlb.u16 q1, q1936; CHECK-NEXT: vmovlb.u16 q0, q0937; CHECK-NEXT: vmin.u32 q0, q0, q1938; CHECK-NEXT: bx lr939 %c = call <4 x i16> @llvm.umin.v4i16(<4 x i16> %a, <4 x i16> %b)940 ret <4 x i16> %c941}942 943declare <8 x i16> @llvm.umin.v8i16(<8 x i16> %a, <8 x i16> %b) readnone944 945define arm_aapcs_vfpcc <8 x i16> @umin8i16(<8 x i16> %a, <8 x i16> %b) {946; CHECK-LABEL: umin8i16:947; CHECK: @ %bb.0:948; CHECK-NEXT: vmin.u16 q0, q0, q1949; CHECK-NEXT: bx lr950 %c = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %a, <8 x i16> %b)951 ret <8 x i16> %c952}953 954declare <16 x i16> @llvm.umin.v16i16(<16 x i16> %a, <16 x i16> %b) readnone955 956define arm_aapcs_vfpcc void @umin16i16(<16 x i16> %a, <16 x i16> %b, ptr %p) {957; CHECK-LABEL: umin16i16:958; CHECK: @ %bb.0:959; CHECK-NEXT: vmin.u16 q1, q1, q3960; CHECK-NEXT: vmin.u16 q0, q0, q2961; CHECK-NEXT: vstrw.32 q1, [r0, #16]962; CHECK-NEXT: vstrw.32 q0, [r0]963; CHECK-NEXT: bx lr964 %c = call <16 x i16> @llvm.umin.v16i16(<16 x i16> %a, <16 x i16> %b)965 store <16 x i16> %c, ptr %p966 ret void967}968 969declare <2 x i32> @llvm.umin.v2i32(<2 x i32> %a, <2 x i32> %b) readnone970 971define arm_aapcs_vfpcc <2 x i32> @umin2i32(<2 x i32> %a, <2 x i32> %b) {972; CHECK-LABEL: umin2i32:973; CHECK: @ %bb.0:974; CHECK-NEXT: vmov.i64 q2, #0xffffffff975; CHECK-NEXT: vand q1, q1, q2976; CHECK-NEXT: vand q0, q0, q2977; CHECK-NEXT: vmov r0, r1, d2978; CHECK-NEXT: vmov r2, r3, d0979; CHECK-NEXT: subs r0, r2, r0980; CHECK-NEXT: sbcs.w r0, r3, r1981; CHECK-NEXT: mov.w r1, #0982; CHECK-NEXT: csetm r0, lo983; CHECK-NEXT: vmov r3, r2, d1984; CHECK-NEXT: bfi r1, r0, #0, #8985; CHECK-NEXT: vmov r0, r12, d3986; CHECK-NEXT: subs r0, r3, r0987; CHECK-NEXT: sbcs.w r0, r2, r12988; CHECK-NEXT: csetm r0, lo989; CHECK-NEXT: bfi r1, r0, #8, #8990; CHECK-NEXT: vmsr p0, r1991; CHECK-NEXT: vpsel q0, q0, q1992; CHECK-NEXT: bx lr993 %c = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %a, <2 x i32> %b)994 ret <2 x i32> %c995}996 997declare <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> %b) readnone998 999define arm_aapcs_vfpcc <4 x i32> @umin4i32(<4 x i32> %a, <4 x i32> %b) {1000; CHECK-LABEL: umin4i32:1001; CHECK: @ %bb.0:1002; CHECK-NEXT: vmin.u32 q0, q0, q11003; CHECK-NEXT: bx lr1004 %c = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> %b)1005 ret <4 x i32> %c1006}1007 1008declare <8 x i32> @llvm.umin.v8i32(<8 x i32> %a, <8 x i32> %b) readnone1009 1010define arm_aapcs_vfpcc void @umin8i32(<8 x i32> %a, <8 x i32> %b, ptr %p) {1011; CHECK-LABEL: umin8i32:1012; CHECK: @ %bb.0:1013; CHECK-NEXT: vmin.u32 q1, q1, q31014; CHECK-NEXT: vmin.u32 q0, q0, q21015; CHECK-NEXT: vstrw.32 q1, [r0, #16]1016; CHECK-NEXT: vstrw.32 q0, [r0]1017; CHECK-NEXT: bx lr1018 %c = call <8 x i32>@llvm.umin.v8i32(<8 x i32> %a, <8 x i32> %b)1019 store <8 x i32> %c, ptr %p1020 ret void1021}1022 1023declare <1 x i64> @llvm.umin.v1i64(<1 x i64> %a, <1 x i64> %b) readnone1024 1025define arm_aapcs_vfpcc <1 x i64> @umin1i64(<1 x i64> %a, <1 x i64> %b) {1026; CHECK-LABEL: umin1i64:1027; CHECK: @ %bb.0:1028; CHECK-NEXT: .pad #81029; CHECK-NEXT: sub sp, #81030; CHECK-NEXT: subs.w r12, r0, r21031; CHECK-NEXT: sbcs.w r12, r1, r31032; CHECK-NEXT: csel r0, r0, r2, lo1033; CHECK-NEXT: csel r1, r1, r3, lo1034; CHECK-NEXT: add sp, #81035; CHECK-NEXT: bx lr1036 %c = call <1 x i64> @llvm.umin.v1i64(<1 x i64> %a, <1 x i64> %b)1037 ret <1 x i64> %c1038}1039 1040declare <2 x i64> @llvm.umin.v2i64(<2 x i64> %a, <2 x i64> %b) readnone1041 1042define arm_aapcs_vfpcc <2 x i64> @umin2i64(<2 x i64> %a, <2 x i64> %b) {1043; CHECK-LABEL: umin2i64:1044; CHECK: @ %bb.0:1045; CHECK-NEXT: vmov r0, r1, d21046; CHECK-NEXT: vmov r2, r3, d01047; CHECK-NEXT: subs r0, r2, r01048; CHECK-NEXT: sbcs.w r0, r3, r11049; CHECK-NEXT: mov.w r1, #01050; CHECK-NEXT: csetm r0, lo1051; CHECK-NEXT: vmov r3, r2, d11052; CHECK-NEXT: bfi r1, r0, #0, #81053; CHECK-NEXT: vmov r0, r12, d31054; CHECK-NEXT: subs r0, r3, r01055; CHECK-NEXT: sbcs.w r0, r2, r121056; CHECK-NEXT: csetm r0, lo1057; CHECK-NEXT: bfi r1, r0, #8, #81058; CHECK-NEXT: vmsr p0, r11059; CHECK-NEXT: vpsel q0, q0, q11060; CHECK-NEXT: bx lr1061 %c = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %a, <2 x i64> %b)1062 ret <2 x i64> %c1063}1064 1065declare <4 x i64> @llvm.umin.v4i64(<4 x i64> %a, <4 x i64> %b) readnone1066 1067define arm_aapcs_vfpcc void @umin4i64(<4 x i64> %a, <4 x i64> %b, ptr %p) {1068; CHECK-LABEL: umin4i64:1069; CHECK: @ %bb.0:1070; CHECK-NEXT: .save {r4, lr}1071; CHECK-NEXT: push {r4, lr}1072; CHECK-NEXT: vmov r1, r12, d61073; CHECK-NEXT: vmov r3, r2, d21074; CHECK-NEXT: subs r1, r3, r11075; CHECK-NEXT: mov.w r3, #01076; CHECK-NEXT: sbcs.w r1, r2, r121077; CHECK-NEXT: vmov lr, r12, d71078; CHECK-NEXT: csetm r2, lo1079; CHECK-NEXT: movs r1, #01080; CHECK-NEXT: bfi r3, r2, #0, #81081; CHECK-NEXT: vmov r2, r4, d31082; CHECK-NEXT: subs.w r2, r2, lr1083; CHECK-NEXT: sbcs.w r2, r4, r121084; CHECK-NEXT: csetm r2, lo1085; CHECK-NEXT: bfi r3, r2, #8, #81086; CHECK-NEXT: vmov r2, r12, d41087; CHECK-NEXT: vmsr p0, r31088; CHECK-NEXT: vmov r4, r3, d01089; CHECK-NEXT: vpsel q1, q1, q31090; CHECK-NEXT: vstrw.32 q1, [r0, #16]1091; CHECK-NEXT: subs r2, r4, r21092; CHECK-NEXT: sbcs.w r2, r3, r121093; CHECK-NEXT: vmov r4, r3, d11094; CHECK-NEXT: csetm r2, lo1095; CHECK-NEXT: bfi r1, r2, #0, #81096; CHECK-NEXT: vmov r2, r12, d51097; CHECK-NEXT: subs r2, r4, r21098; CHECK-NEXT: sbcs.w r2, r3, r121099; CHECK-NEXT: csetm r2, lo1100; CHECK-NEXT: bfi r1, r2, #8, #81101; CHECK-NEXT: vmsr p0, r11102; CHECK-NEXT: vpsel q0, q0, q21103; CHECK-NEXT: vstrw.32 q0, [r0]1104; CHECK-NEXT: pop {r4, pc}1105 %c = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %a, <4 x i64> %b)1106 store <4 x i64> %c, ptr %p1107 ret void1108}1109