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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O3 -mattr=+mve %s -o - | FileCheck %s3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O3 -mattr=+mve -early-live-intervals -verify-machineinstrs %s -o - | FileCheck %s4 5declare void @external_function()6 7define arm_aapcs_vfpcc void @spill_multivector(ptr %p) {8; CHECK-LABEL: spill_multivector:9; CHECK: @ %bb.0: @ %entry10; CHECK-NEXT: .save {r4, r5, r7, lr}11; CHECK-NEXT: push {r4, r5, r7, lr}12; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}13; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}14; CHECK-NEXT: .pad #9615; CHECK-NEXT: sub sp, #9616; CHECK-NEXT: vld20.32 {q0, q1}, [r0]17; CHECK-NEXT: mov r5, r018; CHECK-NEXT: add.w lr, sp, #6419; CHECK-NEXT: mov r4, r020; CHECK-NEXT: vld21.32 {q0, q1}, [r5]!21; CHECK-NEXT: adds r0, #6422; CHECK-NEXT: vstmia lr, {d0, d1, d2, d3} @ 32-byte Spill23; CHECK-NEXT: vld20.32 {q0, q1}, [r0]24; CHECK-NEXT: add.w lr, sp, #3225; CHECK-NEXT: vld21.32 {q0, q1}, [r0]26; CHECK-NEXT: add.w r0, r4, #12827; CHECK-NEXT: vstmia lr, {d0, d1, d2, d3} @ 32-byte Spill28; CHECK-NEXT: vld20.32 {q0, q1}, [r0]29; CHECK-NEXT: vld21.32 {q0, q1}, [r0]30; CHECK-NEXT: add.w r0, r4, #19231; CHECK-NEXT: vld20.32 {q6, q7}, [r0]32; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3} @ 32-byte Spill33; CHECK-NEXT: vld21.32 {q6, q7}, [r0]34; CHECK-NEXT: add.w r0, r4, #25635; CHECK-NEXT: vld20.32 {q4, q5}, [r0]36; CHECK-NEXT: vld21.32 {q4, q5}, [r0]37; CHECK-NEXT: bl external_function38; CHECK-NEXT: vldmia sp, {d2, d3, d4, d5} @ 32-byte Reload39; CHECK-NEXT: add.w lr, sp, #3240; CHECK-NEXT: vstrw.32 q2, [r4, #80]41; CHECK-NEXT: vstrw.32 q5, [r4, #144]42; CHECK-NEXT: vstrw.32 q4, [r4, #128]43; CHECK-NEXT: vstrw.32 q7, [r4, #112]44; CHECK-NEXT: vstrw.32 q1, [r4, #64]45; CHECK-NEXT: vldmia lr, {d2, d3, d4, d5} @ 32-byte Reload46; CHECK-NEXT: add.w lr, sp, #6447; CHECK-NEXT: vstrw.32 q2, [r4, #48]48; CHECK-NEXT: vstrw.32 q6, [r4, #96]49; CHECK-NEXT: vstrw.32 q1, [r5]50; CHECK-NEXT: vldmia lr, {d2, d3, d4, d5} @ 32-byte Reload51; CHECK-NEXT: vstrw.32 q2, [r4, #16]52; CHECK-NEXT: vstrw.32 q1, [r4]53; CHECK-NEXT: add sp, #9654; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}55; CHECK-NEXT: pop {r4, r5, r7, pc}56entry:57 %v01 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.v4i32.p0(ptr %p)58 %ip23 = getelementptr i32, ptr %p, i32 1659 %v23 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.v4i32.p0(ptr %ip23)60 %ip45 = getelementptr i32, ptr %ip23, i32 1661 %v45 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.v4i32.p0(ptr %ip45)62 %ip67 = getelementptr i32, ptr %ip45, i32 1663 %v67 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.v4i32.p0(ptr %ip67)64 %ip89 = getelementptr i32, ptr %ip67, i32 1665 %v89 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.v4i32.p0(ptr %ip89)66 call void @external_function()67 68 %v0 = extractvalue { <4 x i32>, <4 x i32> } %v01, 069 %v1 = extractvalue { <4 x i32>, <4 x i32> } %v01, 170 store <4 x i32> %v0, ptr %p, align 471 %p1 = getelementptr <4 x i32>, ptr %p, i32 172 store <4 x i32> %v1, ptr %p1, align 473 74 %v2 = extractvalue { <4 x i32>, <4 x i32> } %v23, 075 %v3 = extractvalue { <4 x i32>, <4 x i32> } %v23, 176 %p2 = getelementptr <4 x i32>, ptr %p, i32 277 store <4 x i32> %v2, ptr %p2, align 478 %p3 = getelementptr <4 x i32>, ptr %p, i32 379 store <4 x i32> %v3, ptr %p3, align 480 81 %v4 = extractvalue { <4 x i32>, <4 x i32> } %v45, 082 %v5 = extractvalue { <4 x i32>, <4 x i32> } %v45, 183 %p4 = getelementptr <4 x i32>, ptr %p, i32 484 store <4 x i32> %v4, ptr %p4, align 485 %p5 = getelementptr <4 x i32>, ptr %p, i32 586 store <4 x i32> %v5, ptr %p5, align 487 88 %v6 = extractvalue { <4 x i32>, <4 x i32> } %v67, 089 %v7 = extractvalue { <4 x i32>, <4 x i32> } %v67, 190 %p6 = getelementptr <4 x i32>, ptr %p, i32 691 store <4 x i32> %v6, ptr %p6, align 492 %p7 = getelementptr <4 x i32>, ptr %p, i32 793 store <4 x i32> %v7, ptr %p7, align 494 95 %v8 = extractvalue { <4 x i32>, <4 x i32> } %v89, 096 %v9 = extractvalue { <4 x i32>, <4 x i32> } %v89, 197 %p8 = getelementptr <4 x i32>, ptr %p, i32 898 store <4 x i32> %v8, ptr %p8, align 499 %p9 = getelementptr <4 x i32>, ptr %p, i32 9100 store <4 x i32> %v9, ptr %p9, align 4101 ret void102}103 104declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.v4i32.p0(ptr)105