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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve,-vfp2 -o - %s | FileCheck %s --check-prefix=CHECK-NOFP3; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp -o - %s | FileCheck --check-prefix=CHECK-FP %s4 5; This file tests tests that we expand floating point operations correctly,6; even if we do not have an fpu.7 8define arm_aapcs_vfpcc <8 x half> @vector_add_f16(<8 x half> %lhs, <8 x half> %rhs) {9; CHECK-NOFP-LABEL: vector_add_f16:10; CHECK-NOFP: @ %bb.0: @ %entry11; CHECK-NOFP-NEXT: .save {r4, lr}12; CHECK-NOFP-NEXT: push {r4, lr}13; CHECK-NOFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13}14; CHECK-NOFP-NEXT: vpush {d8, d9, d10, d11, d12, d13}15; CHECK-NOFP-NEXT: vmov.u16 r0, q1[0]16; CHECK-NOFP-NEXT: vmov q5, q117; CHECK-NOFP-NEXT: vmov q4, q018; CHECK-NOFP-NEXT: bl __aeabi_h2f19; CHECK-NOFP-NEXT: mov r4, r020; CHECK-NOFP-NEXT: vmov.u16 r0, q4[0]21; CHECK-NOFP-NEXT: bl __aeabi_h2f22; CHECK-NOFP-NEXT: mov r1, r423; CHECK-NOFP-NEXT: bl __aeabi_fadd24; CHECK-NOFP-NEXT: bl __aeabi_f2h25; CHECK-NOFP-NEXT: vmov.16 q6[0], r026; CHECK-NOFP-NEXT: vmov.u16 r0, q5[1]27; CHECK-NOFP-NEXT: bl __aeabi_h2f28; CHECK-NOFP-NEXT: mov r4, r029; CHECK-NOFP-NEXT: vmov.u16 r0, q4[1]30; CHECK-NOFP-NEXT: bl __aeabi_h2f31; CHECK-NOFP-NEXT: mov r1, r432; CHECK-NOFP-NEXT: bl __aeabi_fadd33; CHECK-NOFP-NEXT: bl __aeabi_f2h34; CHECK-NOFP-NEXT: vmov.16 q6[1], r035; CHECK-NOFP-NEXT: vmov.u16 r0, q5[2]36; CHECK-NOFP-NEXT: bl __aeabi_h2f37; CHECK-NOFP-NEXT: mov r4, r038; CHECK-NOFP-NEXT: vmov.u16 r0, q4[2]39; CHECK-NOFP-NEXT: bl __aeabi_h2f40; CHECK-NOFP-NEXT: mov r1, r441; CHECK-NOFP-NEXT: bl __aeabi_fadd42; CHECK-NOFP-NEXT: bl __aeabi_f2h43; CHECK-NOFP-NEXT: vmov.16 q6[2], r044; CHECK-NOFP-NEXT: vmov.u16 r0, q5[3]45; CHECK-NOFP-NEXT: bl __aeabi_h2f46; CHECK-NOFP-NEXT: mov r4, r047; CHECK-NOFP-NEXT: vmov.u16 r0, q4[3]48; CHECK-NOFP-NEXT: bl __aeabi_h2f49; CHECK-NOFP-NEXT: mov r1, r450; CHECK-NOFP-NEXT: bl __aeabi_fadd51; CHECK-NOFP-NEXT: bl __aeabi_f2h52; CHECK-NOFP-NEXT: vmov.16 q6[3], r053; CHECK-NOFP-NEXT: vmov.u16 r0, q5[4]54; CHECK-NOFP-NEXT: bl __aeabi_h2f55; CHECK-NOFP-NEXT: mov r4, r056; CHECK-NOFP-NEXT: vmov.u16 r0, q4[4]57; CHECK-NOFP-NEXT: bl __aeabi_h2f58; CHECK-NOFP-NEXT: mov r1, r459; CHECK-NOFP-NEXT: bl __aeabi_fadd60; CHECK-NOFP-NEXT: bl __aeabi_f2h61; CHECK-NOFP-NEXT: vmov.16 q6[4], r062; CHECK-NOFP-NEXT: vmov.u16 r0, q5[5]63; CHECK-NOFP-NEXT: bl __aeabi_h2f64; CHECK-NOFP-NEXT: mov r4, r065; CHECK-NOFP-NEXT: vmov.u16 r0, q4[5]66; CHECK-NOFP-NEXT: bl __aeabi_h2f67; CHECK-NOFP-NEXT: mov r1, r468; CHECK-NOFP-NEXT: bl __aeabi_fadd69; CHECK-NOFP-NEXT: bl __aeabi_f2h70; CHECK-NOFP-NEXT: vmov.16 q6[5], r071; CHECK-NOFP-NEXT: vmov.u16 r0, q5[6]72; CHECK-NOFP-NEXT: bl __aeabi_h2f73; CHECK-NOFP-NEXT: mov r4, r074; CHECK-NOFP-NEXT: vmov.u16 r0, q4[6]75; CHECK-NOFP-NEXT: bl __aeabi_h2f76; CHECK-NOFP-NEXT: mov r1, r477; CHECK-NOFP-NEXT: bl __aeabi_fadd78; CHECK-NOFP-NEXT: bl __aeabi_f2h79; CHECK-NOFP-NEXT: vmov.16 q6[6], r080; CHECK-NOFP-NEXT: vmov.u16 r0, q5[7]81; CHECK-NOFP-NEXT: bl __aeabi_h2f82; CHECK-NOFP-NEXT: mov r4, r083; CHECK-NOFP-NEXT: vmov.u16 r0, q4[7]84; CHECK-NOFP-NEXT: bl __aeabi_h2f85; CHECK-NOFP-NEXT: mov r1, r486; CHECK-NOFP-NEXT: bl __aeabi_fadd87; CHECK-NOFP-NEXT: bl __aeabi_f2h88; CHECK-NOFP-NEXT: vmov.16 q6[7], r089; CHECK-NOFP-NEXT: vmov q0, q690; CHECK-NOFP-NEXT: vpop {d8, d9, d10, d11, d12, d13}91; CHECK-NOFP-NEXT: pop {r4, pc}92;93; CHECK-FP-LABEL: vector_add_f16:94; CHECK-FP: @ %bb.0: @ %entry95; CHECK-FP-NEXT: vadd.f16 q0, q0, q196; CHECK-FP-NEXT: bx lr97entry:98 %sum = fadd <8 x half> %lhs, %rhs99 ret <8 x half> %sum100}101 102define arm_aapcs_vfpcc <4 x float> @vector_add_f32(<4 x float> %lhs, <4 x float> %rhs) {103; CHECK-NOFP-LABEL: vector_add_f32:104; CHECK-NOFP: @ %bb.0: @ %entry105; CHECK-NOFP-NEXT: .save {r4, r5, r7, lr}106; CHECK-NOFP-NEXT: push {r4, r5, r7, lr}107; CHECK-NOFP-NEXT: .vsave {d8, d9, d10, d11}108; CHECK-NOFP-NEXT: vpush {d8, d9, d10, d11}109; CHECK-NOFP-NEXT: vmov q4, q1110; CHECK-NOFP-NEXT: vmov q5, q0111; CHECK-NOFP-NEXT: vmov r4, r0, d11112; CHECK-NOFP-NEXT: vmov r5, r1, d9113; CHECK-NOFP-NEXT: bl __aeabi_fadd114; CHECK-NOFP-NEXT: vmov s19, r0115; CHECK-NOFP-NEXT: mov r0, r4116; CHECK-NOFP-NEXT: mov r1, r5117; CHECK-NOFP-NEXT: bl __aeabi_fadd118; CHECK-NOFP-NEXT: vmov s18, r0119; CHECK-NOFP-NEXT: vmov r4, r0, d10120; CHECK-NOFP-NEXT: vmov r5, r1, d8121; CHECK-NOFP-NEXT: bl __aeabi_fadd122; CHECK-NOFP-NEXT: vmov s17, r0123; CHECK-NOFP-NEXT: mov r0, r4124; CHECK-NOFP-NEXT: mov r1, r5125; CHECK-NOFP-NEXT: bl __aeabi_fadd126; CHECK-NOFP-NEXT: vmov s16, r0127; CHECK-NOFP-NEXT: vmov q0, q4128; CHECK-NOFP-NEXT: vpop {d8, d9, d10, d11}129; CHECK-NOFP-NEXT: pop {r4, r5, r7, pc}130;131; CHECK-FP-LABEL: vector_add_f32:132; CHECK-FP: @ %bb.0: @ %entry133; CHECK-FP-NEXT: vadd.f32 q0, q0, q1134; CHECK-FP-NEXT: bx lr135entry:136 %sum = fadd <4 x float> %lhs, %rhs137 ret <4 x float> %sum138}139 140