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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp --arm-memtransfer-tploop=allow -enable-arm-maskedgatscat=false -verify-machineinstrs %s -o - | FileCheck %s3 4; verify-machineinstrs previously caught the incorrect use of QPR in the stack reloads.5 6define arm_aapcs_vfpcc void @k() {7; CHECK-LABEL: k:8; CHECK: @ %bb.0: @ %entry9; CHECK-NEXT: .save {r4, r5, r6, lr}10; CHECK-NEXT: push {r4, r5, r6, lr}11; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14}12; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14}13; CHECK-NEXT: .pad #3214; CHECK-NEXT: sub sp, #3215; CHECK-NEXT: adr r5, .LCPI0_016; CHECK-NEXT: adr r4, .LCPI0_117; CHECK-NEXT: vldrw.u32 q6, [r5]18; CHECK-NEXT: vldrw.u32 q5, [r4]19; CHECK-NEXT: add r0, sp, #1620; CHECK-NEXT: vmov.i32 q0, #0x121; CHECK-NEXT: vmov.i8 q1, #0x022; CHECK-NEXT: vmov.i8 q2, #0xff23; CHECK-NEXT: vmov.i16 q3, #0x624; CHECK-NEXT: vmov.i16 q4, #0x325; CHECK-NEXT: movs r1, #026; CHECK-NEXT: .LBB0_1: @ %vector.body27; CHECK-NEXT: @ =>This Inner Loop Header: Depth=128; CHECK-NEXT: vand q5, q5, q029; CHECK-NEXT: vand q6, q6, q030; CHECK-NEXT: vcmp.i32 eq, q5, zr31; CHECK-NEXT: vpsel q5, q2, q132; CHECK-NEXT: vcmp.i32 eq, q6, zr33; CHECK-NEXT: vpsel q6, q2, q134; CHECK-NEXT: vstrh.32 q5, [r0]35; CHECK-NEXT: vstrh.32 q6, [r0, #8]36; CHECK-NEXT: vldrw.u32 q5, [r0]37; CHECK-NEXT: vcmp.i16 ne, q5, zr38; CHECK-NEXT: vmov.i32 q5, #0x039; CHECK-NEXT: vpsel q6, q4, q340; CHECK-NEXT: vstrh.16 q6, [r0]41; CHECK-NEXT: vmov.i32 q6, #0x042; CHECK-NEXT: cbz r1, .LBB0_243; CHECK-NEXT: le .LBB0_144; CHECK-NEXT: .LBB0_2: @ %for.cond4.preheader45; CHECK-NEXT: movs r6, #046; CHECK-NEXT: cbnz r6, .LBB0_547; CHECK-NEXT: .LBB0_3: @ %for.body1048; CHECK-NEXT: @ =>This Inner Loop Header: Depth=149; CHECK-NEXT: cbnz r6, .LBB0_450; CHECK-NEXT: le .LBB0_351; CHECK-NEXT: .LBB0_4: @ %for.cond4.loopexit52; CHECK-NEXT: bl l53; CHECK-NEXT: .LBB0_5: @ %vector.body105.preheader54; CHECK-NEXT: vldrw.u32 q0, [r5]55; CHECK-NEXT: vldrw.u32 q1, [r4]56; CHECK-NEXT: movs r0, #857; CHECK-NEXT: .LBB0_6: @ %vector.body10558; CHECK-NEXT: @ =>This Inner Loop Header: Depth=159; CHECK-NEXT: vadd.i32 q1, q1, r060; CHECK-NEXT: vadd.i32 q0, q0, r061; CHECK-NEXT: cbz r6, .LBB0_762; CHECK-NEXT: le .LBB0_663; CHECK-NEXT: .LBB0_7: @ %vector.body115.ph64; CHECK-NEXT: vldrw.u32 q0, [r4]65; CHECK-NEXT: movs r0, #466; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill67; CHECK-NEXT: @APP68; CHECK-NEXT: nop69; CHECK-NEXT: @NO_APP70; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload71; CHECK-NEXT: .LBB0_8: @ %vector.body11572; CHECK-NEXT: @ =>This Inner Loop Header: Depth=173; CHECK-NEXT: vadd.i32 q0, q0, r074; CHECK-NEXT: b .LBB0_875; CHECK-NEXT: .p2align 476; CHECK-NEXT: @ %bb.9:77; CHECK-NEXT: .LCPI0_0:78; CHECK-NEXT: .long 4 @ 0x479; CHECK-NEXT: .long 5 @ 0x580; CHECK-NEXT: .long 6 @ 0x681; CHECK-NEXT: .long 7 @ 0x782; CHECK-NEXT: .LCPI0_1:83; CHECK-NEXT: .long 0 @ 0x084; CHECK-NEXT: .long 1 @ 0x185; CHECK-NEXT: .long 2 @ 0x286; CHECK-NEXT: .long 3 @ 0x387entry:88 br label %vector.body89 90vector.body: ; preds = %vector.body, %entry91 %vec.ind = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %entry ], [ zeroinitializer, %vector.body ]92 %0 = and <8 x i32> %vec.ind, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>93 %1 = icmp eq <8 x i32> %0, zeroinitializer94 %2 = select <8 x i1> %1, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>, <8 x i16> <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>95 %3 = bitcast ptr undef to ptr96 store <8 x i16> %2, ptr %3, align 297 %4 = icmp eq i32 undef, 12898 br i1 %4, label %for.cond4.preheader, label %vector.body99 100for.cond4.preheader: ; preds = %vector.body101 br i1 undef, label %vector.body105, label %for.body10102 103for.cond4.loopexit: ; preds = %for.body10104 %call5 = call arm_aapcs_vfpcc i32 @l()105 br label %vector.body105106 107for.body10: ; preds = %for.body10, %for.cond4.preheader108 %exitcond88 = icmp eq i32 undef, 7109 br i1 %exitcond88, label %for.cond4.loopexit, label %for.body10110 111vector.body105: ; preds = %vector.body105, %for.cond4.loopexit, %for.cond4.preheader112 %vec.ind113 = phi <8 x i32> [ %vec.ind.next114, %vector.body105 ], [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %for.cond4.loopexit ], [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %for.cond4.preheader ]113 %5 = and <8 x i32> %vec.ind113, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>114 %vec.ind.next114 = add <8 x i32> %vec.ind113, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>115 %6 = icmp eq i32 undef, 256116 br i1 %6, label %vector.body115.ph, label %vector.body105117 118vector.body115.ph: ; preds = %vector.body105119 tail call void asm sideeffect "nop", "~{s0},~{s4},~{s8},~{s12},~{s16},~{s20},~{s24},~{s28},~{memory}"()120 br label %vector.body115121 122vector.body115: ; preds = %vector.body115, %vector.body115.ph123 %vec.ind123 = phi <4 x i32> [ %vec.ind.next124, %vector.body115 ], [ <i32 0, i32 1, i32 2, i32 3>, %vector.body115.ph ]124 %7 = icmp eq <4 x i32> %vec.ind123, zeroinitializer125 %vec.ind.next124 = add <4 x i32> %vec.ind123, <i32 4, i32 4, i32 4, i32 4>126 br label %vector.body115127}128 129 130@a = external dso_local global i32, align 4131@b = dso_local local_unnamed_addr global i32 ptrtoint (ptr @a to i32), align 4132@c = dso_local global i32 2, align 4133@d = dso_local global i32 2, align 4134 135define dso_local i32 @e() #0 {136; CHECK-LABEL: e:137; CHECK: @ %bb.0: @ %entry138; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}139; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}140; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}141; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}142; CHECK-NEXT: .pad #392143; CHECK-NEXT: sub sp, #392144; CHECK-NEXT: movw r7, :lower16:.L_MergedGlobals145; CHECK-NEXT: vldr s15, .LCPI1_1146; CHECK-NEXT: movt r7, :upper16:.L_MergedGlobals147; CHECK-NEXT: movw r2, :lower16:e148; CHECK-NEXT: mov r4, r7149; CHECK-NEXT: mov r3, r7150; CHECK-NEXT: ldr r6, [r4, #8]!151; CHECK-NEXT: movt r2, :upper16:e152; CHECK-NEXT: ldr r0, [r3, #4]!153; CHECK-NEXT: vmov r5, s15154; CHECK-NEXT: vmov q0[2], q0[0], r4, r4155; CHECK-NEXT: vldr s12, .LCPI1_0156; CHECK-NEXT: vmov s13, r3157; CHECK-NEXT: vmov q0[3], q0[1], r5, r2158; CHECK-NEXT: vdup.32 q7, r3159; CHECK-NEXT: vmov q6[2], q6[0], r3, r5160; CHECK-NEXT: vstrw.32 q0, [sp, #76]161; CHECK-NEXT: vmov q0, q7162; CHECK-NEXT: vmov q6[3], q6[1], r3, r2163; CHECK-NEXT: vmov q4, q7164; CHECK-NEXT: vmov.32 q0[0], r2165; CHECK-NEXT: vmov.32 q7[1], r2166; CHECK-NEXT: vmov s21, r2167; CHECK-NEXT: movs r1, #64168; CHECK-NEXT: vmov.f32 s20, s12169; CHECK-NEXT: str r0, [sp, #24]170; CHECK-NEXT: vmov.f32 s22, s13171; CHECK-NEXT: str r6, [r0]172; CHECK-NEXT: vmov.f32 s23, s15173; CHECK-NEXT: str r0, [r0]174; CHECK-NEXT: vstrw.32 q5, [r0]175; CHECK-NEXT: vstrw.32 q7, [r0]176; CHECK-NEXT: vstrw.32 q0, [r0]177; CHECK-NEXT: vstrw.32 q6, [r0]178; CHECK-NEXT: mov.w r8, #0179; CHECK-NEXT: vmov q1[2], q1[0], r4, r3180; CHECK-NEXT: vmov q2[2], q2[0], r3, r3181; CHECK-NEXT: mov.w r12, #4182; CHECK-NEXT: vmov q1[3], q1[1], r2, r4183; CHECK-NEXT: vmov.f32 s14, s13184; CHECK-NEXT: vmov q2[3], q2[1], r4, r5185; CHECK-NEXT: vmov.32 q4[0], r8186; CHECK-NEXT: @ implicit-def: $r2187; CHECK-NEXT: str.w r8, [sp, #28]188; CHECK-NEXT: vstrw.32 q3, [sp, #44]189; CHECK-NEXT: strh.w r12, [sp, #390]190; CHECK-NEXT: wlstp.8 lr, r1, .LBB1_2191; CHECK-NEXT: .LBB1_1: @ =>This Inner Loop Header: Depth=1192; CHECK-NEXT: vmov.i32 q0, #0x0193; CHECK-NEXT: vstrb.8 q0, [r2], #16194; CHECK-NEXT: letp lr, .LBB1_1195; CHECK-NEXT: .LBB1_2: @ %entry196; CHECK-NEXT: vstrw.32 q1, [r0]197; CHECK-NEXT: str.w r8, [r7]198; CHECK-NEXT: vstrw.32 q4, [r0]199; CHECK-NEXT: vstrw.32 q2, [r0]200; CHECK-NEXT: str.w r12, [sp, #308]201; CHECK-NEXT: .LBB1_3: @ %for.cond202; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1203; CHECK-NEXT: b .LBB1_3204; CHECK-NEXT: .p2align 2205; CHECK-NEXT: @ %bb.4:206; CHECK-NEXT: .LCPI1_0:207; CHECK-NEXT: .long 0x00000004 @ float 5.60519386E-45208; CHECK-NEXT: .LCPI1_1:209; CHECK-NEXT: .long 0x00000000 @ float 0210entry:211 %f = alloca i16, align 2212 %g = alloca [3 x [8 x [4 x ptr]]], align 4213 store i16 4, ptr %f, align 2214 %0 = load i32, ptr @c, align 4215 %1 = load i32, ptr @d, align 4216 %arrayinit.element7 = getelementptr inbounds [3 x [8 x [4 x ptr]]], ptr %g, i32 0, i32 0, i32 1, i32 1217 %2 = bitcast ptr %arrayinit.element7 to ptr218 store i32 %0, ptr %2, align 4219 %arrayinit.element8 = getelementptr inbounds [3 x [8 x [4 x ptr]]], ptr %g, i32 0, i32 0, i32 1, i32 2220 store ptr null, ptr %arrayinit.element8, align 4221 %3 = bitcast ptr undef to ptr222 store i32 %1, ptr %3, align 4223 %4 = bitcast ptr undef to ptr224 store i32 %0, ptr %4, align 4225 %arrayinit.element13 = getelementptr inbounds [3 x [8 x [4 x ptr]]], ptr %g, i32 0, i32 0, i32 2, i32 2226 %5 = bitcast ptr %arrayinit.element13 to ptr227 store <4 x ptr> <ptr inttoptr (i32 4 to ptr), ptr @c, ptr @c, ptr null>, ptr %5, align 4228 %arrayinit.element24 = getelementptr inbounds [3 x [8 x [4 x ptr]]], ptr %g, i32 0, i32 0, i32 4, i32 2229 %6 = bitcast ptr %arrayinit.element24 to ptr230 store <4 x ptr> <ptr @d, ptr null, ptr @d, ptr @e>, ptr %6, align 4231 %7 = bitcast ptr undef to ptr232 store <4 x ptr> <ptr inttoptr (i32 4 to ptr), ptr @e, ptr @c, ptr null>, ptr %7, align 4233 %8 = bitcast ptr undef to ptr234 store <4 x ptr> <ptr @c, ptr @e, ptr @c, ptr @c>, ptr %8, align 4235 %9 = bitcast ptr undef to ptr236 store <4 x ptr> <ptr @e, ptr @c, ptr @c, ptr @c>, ptr %9, align 4237 %10 = bitcast ptr undef to ptr238 store <4 x ptr> <ptr @c, ptr @c, ptr null, ptr @e>, ptr %10, align 4239 call void @llvm.memset.p0.i32(ptr nonnull align 4 dereferenceable(64) undef, i8 0, i32 64, i1 false)240 %11 = bitcast ptr undef to ptr241 store <4 x ptr> <ptr @d, ptr @e, ptr @c, ptr @d>, ptr %11, align 4242 %12 = bitcast ptr undef to ptr243 store <4 x ptr> <ptr null, ptr @c, ptr @c, ptr @c>, ptr %12, align 4244 %13 = bitcast ptr undef to ptr245 store <4 x ptr> <ptr @c, ptr @d, ptr @c, ptr null>, ptr %13, align 4246 %arrayinit.begin78 = getelementptr inbounds [3 x [8 x [4 x ptr]]], ptr %g, i32 0, i32 2, i32 3, i32 0247 store ptr inttoptr (i32 4 to ptr), ptr %arrayinit.begin78, align 4248 store i32 0, ptr @b, align 4249 br label %for.cond250 251for.cond: ; preds = %for.cond, %entry252 br label %for.cond253}254 255; Function Attrs: argmemonly nounwind willreturn256declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) #1257 258; Function Attrs: argmemonly nounwind willreturn259declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1260 261 262declare arm_aapcs_vfpcc i32 @l(...)263