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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - -verify-machineinstrs | FileCheck %s3 4--- |5 define ptr @MVE_VLDRWU32(ptr %x) { unreachable }6 define ptr @MVE_VLDRHU16(ptr %x) { unreachable }7 define ptr @MVE_VLDRBU8(ptr %x) { unreachable }8 define ptr @MVE_VLDRBS32(ptr %x) { unreachable }9 define ptr @MVE_VLDRBU32(ptr %x) { unreachable }10 define ptr @MVE_VLDRHS32(ptr %x) { unreachable }11 define ptr @MVE_VLDRHU32(ptr %x) { unreachable }12 define ptr @MVE_VLDRBS16(ptr %x) { unreachable }13 define ptr @MVE_VLDRBU16(ptr %x) { unreachable }14 define ptr @MVE_VSTRWU32(ptr %x, <4 x i32> %y) { unreachable }15 define ptr @MVE_VSTRHU16(ptr %x, <4 x i32> %y) { unreachable }16 define ptr @MVE_VSTRBU8(ptr %x, <4 x i32> %y) { unreachable }17 define ptr @MVE_VSTRH32(ptr %x, <4 x i32> %y) { unreachable }18 define ptr @MVE_VSTRB32(ptr %x, <4 x i32> %y) { unreachable }19 define ptr @MVE_VSTRB16(ptr %x, <4 x i32> %y) { unreachable }20 21 define ptr @ld0ld4(ptr %x) { unreachable }22 define ptr @ld4ld0(ptr %x) { unreachable }23 define ptr @ld0ld4ld0(ptr %x) { unreachable }24 define ptr @ld4ld0ld4(ptr %x) { unreachable }25 define ptr @addload(ptr %x) { unreachable }26 define ptr @sub(ptr %x) { unreachable }27 define ptr @otherUse(ptr %x) { unreachable }28 define ptr @postincUse(ptr %x) { unreachable }29 define ptr @badScale(ptr %x) { unreachable }30 define ptr @badRange(ptr %x) { unreachable }31 32 define ptr @addUseOK(ptr %x) { unreachable }33 define ptr @addUseDom(ptr %x) { unreachable }34 define ptr @addUseKilled(ptr %x) { unreachable }35 36 define ptr @MVE_VLDRWU32_post(ptr %x) { unreachable }37 define ptr @MVE_VLDRHU16_post(ptr %x) { unreachable }38 define ptr @MVE_VLDRBU8_post(ptr %x) { unreachable }39 define ptr @MVE_VLDRBS32_post(ptr %x) { unreachable }40 define ptr @MVE_VLDRBU32_post(ptr %x) { unreachable }41 define ptr @MVE_VLDRHS32_post(ptr %x) { unreachable }42 define ptr @MVE_VLDRHU32_post(ptr %x) { unreachable }43 define ptr @MVE_VLDRBS16_post(ptr %x) { unreachable }44 define ptr @MVE_VLDRBU16_post(ptr %x) { unreachable }45 define ptr @MVE_VSTRWU32_post(ptr %x, <4 x i32> %y) { unreachable }46 define ptr @MVE_VSTRHU16_post(ptr %x, <4 x i32> %y) { unreachable }47 define ptr @MVE_VSTRBU8_post(ptr %x, <4 x i32> %y) { unreachable }48 define ptr @MVE_VSTRH32_post(ptr %x, <4 x i32> %y) { unreachable }49 define ptr @MVE_VSTRB32_post(ptr %x, <4 x i32> %y) { unreachable }50 define ptr @MVE_VSTRB16_post(ptr %x, <4 x i32> %y) { unreachable }51 define ptr @MVE_VLDRWU32_pre(ptr %x) { unreachable }52 define ptr @MVE_VLDRHU16_pre(ptr %x) { unreachable }53 define ptr @MVE_VLDRBU8_pre(ptr %x) { unreachable }54 define ptr @MVE_VLDRBS32_pre(ptr %x) { unreachable }55 define ptr @MVE_VLDRBU32_pre(ptr %x) { unreachable }56 define ptr @MVE_VLDRHS32_pre(ptr %x) { unreachable }57 define ptr @MVE_VLDRHU32_pre(ptr %x) { unreachable }58 define ptr @MVE_VLDRBS16_pre(ptr %x) { unreachable }59 define ptr @MVE_VLDRBU16_pre(ptr %x) { unreachable }60 define ptr @MVE_VSTRWU32_pre(ptr %x, <4 x i32> %y) { unreachable }61 define ptr @MVE_VSTRHU16_pre(ptr %x, <4 x i32> %y) { unreachable }62 define ptr @MVE_VSTRBU8_pre(ptr %x, <4 x i32> %y) { unreachable }63 define ptr @MVE_VSTRH32_pre(ptr %x, <4 x i32> %y) { unreachable }64 define ptr @MVE_VSTRB32_pre(ptr %x, <4 x i32> %y) { unreachable }65 define ptr @MVE_VSTRB16_pre(ptr %x, <4 x i32> %y) { unreachable }66 67 define ptr @multiple2(ptr %x) { unreachable }68 define ptr @multiple3(ptr %x) { unreachable }69 define ptr @multiple4(ptr %x) { unreachable }70 define ptr @badScale2(ptr %x) { unreachable }71 define ptr @badRange2(ptr %x) { unreachable }72 define ptr @regtype(ptr %x) { unreachable }73 74...75---76name: MVE_VLDRWU3277tracksRegLiveness: true78registers:79 - { id: 0, class: gprnopc, preferred-register: '' }80 - { id: 1, class: mqpr, preferred-register: '' }81 - { id: 2, class: rgpr, preferred-register: '' }82liveins:83 - { reg: '$r0', virtual-reg: '%0' }84 - { reg: '$q0', virtual-reg: '%1' }85body: |86 bb.0:87 liveins: $r0, $q088 89 ; CHECK-LABEL: name: MVE_VLDRWU3290 ; CHECK: liveins: $r0, $q091 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r092 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)93 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]94 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r095 %0:gprnopc = COPY $r096 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)97 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg98 $r0 = COPY %299 tBX_RET 14, $noreg, implicit $r0100 101...102---103name: MVE_VLDRHU16104tracksRegLiveness: true105registers:106 - { id: 0, class: gprnopc, preferred-register: '' }107 - { id: 1, class: mqpr, preferred-register: '' }108 - { id: 2, class: rgpr, preferred-register: '' }109liveins:110 - { reg: '$r0', virtual-reg: '%0' }111 - { reg: '$q0', virtual-reg: '%1' }112body: |113 bb.0:114 liveins: $r0, $q0115 116 ; CHECK-LABEL: name: MVE_VLDRHU16117 ; CHECK: liveins: $r0, $q0118 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0119 ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)120 ; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]]121 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0122 %0:gprnopc = COPY $r0123 %1:mqpr = MVE_VLDRHU16 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)124 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg125 $r0 = COPY %2126 tBX_RET 14, $noreg, implicit $r0127 128...129---130name: MVE_VLDRBU8131tracksRegLiveness: true132registers:133 - { id: 0, class: gprnopc, preferred-register: '' }134 - { id: 1, class: mqpr, preferred-register: '' }135 - { id: 2, class: rgpr, preferred-register: '' }136liveins:137 - { reg: '$r0', virtual-reg: '%0' }138 - { reg: '$q0', virtual-reg: '%1' }139body: |140 bb.0:141 liveins: $r0, $q0142 143 ; CHECK-LABEL: name: MVE_VLDRBU8144 ; CHECK: liveins: $r0, $q0145 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0146 ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)147 ; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]]148 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0149 %0:gprnopc = COPY $r0150 %1:mqpr = MVE_VLDRBU8 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)151 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg152 $r0 = COPY %2153 tBX_RET 14, $noreg, implicit $r0154 155...156---157name: MVE_VLDRBS32158tracksRegLiveness: true159registers:160 - { id: 0, class: tgpr, preferred-register: '' }161 - { id: 1, class: mqpr, preferred-register: '' }162 - { id: 2, class: rgpr, preferred-register: '' }163liveins:164 - { reg: '$r0', virtual-reg: '%0' }165 - { reg: '$q0', virtual-reg: '%1' }166body: |167 bb.0:168 liveins: $r0, $q0169 170 ; CHECK-LABEL: name: MVE_VLDRBS32171 ; CHECK: liveins: $r0, $q0172 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0173 ; CHECK: [[MVE_VLDRBS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_post1:%[0-9]+]]:mqpr = MVE_VLDRBS32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s32), align 8)174 ; CHECK: $r0 = COPY [[MVE_VLDRBS32_post]]175 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0176 %0:tgpr = COPY $r0177 %1:mqpr = MVE_VLDRBS32 %0, 0, 0, $noreg, $noreg :: (load (s32), align 8)178 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg179 $r0 = COPY %2180 tBX_RET 14, $noreg, implicit $r0181 182...183---184name: MVE_VLDRBU32185tracksRegLiveness: true186registers:187 - { id: 0, class: tgpr, preferred-register: '' }188 - { id: 1, class: mqpr, preferred-register: '' }189 - { id: 2, class: rgpr, preferred-register: '' }190liveins:191 - { reg: '$r0', virtual-reg: '%0' }192 - { reg: '$q0', virtual-reg: '%1' }193body: |194 bb.0:195 liveins: $r0, $q0196 197 ; CHECK-LABEL: name: MVE_VLDRBU32198 ; CHECK: liveins: $r0, $q0199 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0200 ; CHECK: [[MVE_VLDRBU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_post1:%[0-9]+]]:mqpr = MVE_VLDRBU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s32), align 8)201 ; CHECK: $r0 = COPY [[MVE_VLDRBU32_post]]202 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0203 %0:tgpr = COPY $r0204 %1:mqpr = MVE_VLDRBU32 %0, 0, 0, $noreg, $noreg :: (load (s32), align 8)205 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg206 $r0 = COPY %2207 tBX_RET 14, $noreg, implicit $r0208 209...210---211name: MVE_VLDRHS32212tracksRegLiveness: true213registers:214 - { id: 0, class: tgpr, preferred-register: '' }215 - { id: 1, class: mqpr, preferred-register: '' }216 - { id: 2, class: rgpr, preferred-register: '' }217liveins:218 - { reg: '$r0', virtual-reg: '%0' }219 - { reg: '$q0', virtual-reg: '%1' }220body: |221 bb.0:222 liveins: $r0, $q0223 224 ; CHECK-LABEL: name: MVE_VLDRHS32225 ; CHECK: liveins: $r0, $q0226 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0227 ; CHECK: [[MVE_VLDRHS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_post1:%[0-9]+]]:mqpr = MVE_VLDRHS32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s64))228 ; CHECK: $r0 = COPY [[MVE_VLDRHS32_post]]229 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0230 %0:tgpr = COPY $r0231 %1:mqpr = MVE_VLDRHS32 %0, 0, 0, $noreg, $noreg :: (load (s64), align 8)232 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg233 $r0 = COPY %2234 tBX_RET 14, $noreg, implicit $r0235 236...237---238name: MVE_VLDRHU32239tracksRegLiveness: true240registers:241 - { id: 0, class: tgpr, preferred-register: '' }242 - { id: 1, class: mqpr, preferred-register: '' }243 - { id: 2, class: rgpr, preferred-register: '' }244liveins:245 - { reg: '$r0', virtual-reg: '%0' }246 - { reg: '$q0', virtual-reg: '%1' }247body: |248 bb.0:249 liveins: $r0, $q0250 251 ; CHECK-LABEL: name: MVE_VLDRHU32252 ; CHECK: liveins: $r0, $q0253 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0254 ; CHECK: [[MVE_VLDRHU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_post1:%[0-9]+]]:mqpr = MVE_VLDRHU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s64))255 ; CHECK: $r0 = COPY [[MVE_VLDRHU32_post]]256 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0257 %0:tgpr = COPY $r0258 %1:mqpr = MVE_VLDRHU32 %0, 0, 0, $noreg, $noreg :: (load (s64), align 8)259 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg260 $r0 = COPY %2261 tBX_RET 14, $noreg, implicit $r0262 263...264---265name: MVE_VLDRBS16266tracksRegLiveness: true267registers:268 - { id: 0, class: tgpr, preferred-register: '' }269 - { id: 1, class: mqpr, preferred-register: '' }270 - { id: 2, class: rgpr, preferred-register: '' }271liveins:272 - { reg: '$r0', virtual-reg: '%0' }273 - { reg: '$q0', virtual-reg: '%1' }274body: |275 bb.0:276 liveins: $r0, $q0277 278 ; CHECK-LABEL: name: MVE_VLDRBS16279 ; CHECK: liveins: $r0, $q0280 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0281 ; CHECK: [[MVE_VLDRBS16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_post1:%[0-9]+]]:mqpr = MVE_VLDRBS16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s64))282 ; CHECK: $r0 = COPY [[MVE_VLDRBS16_post]]283 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0284 %0:tgpr = COPY $r0285 %1:mqpr = MVE_VLDRBS16 %0, 0, 0, $noreg, $noreg :: (load (s64), align 8)286 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg287 $r0 = COPY %2288 tBX_RET 14, $noreg, implicit $r0289 290...291---292name: MVE_VLDRBU16293tracksRegLiveness: true294registers:295 - { id: 0, class: tgpr, preferred-register: '' }296 - { id: 1, class: mqpr, preferred-register: '' }297 - { id: 2, class: rgpr, preferred-register: '' }298liveins:299 - { reg: '$r0', virtual-reg: '%0' }300 - { reg: '$q0', virtual-reg: '%1' }301body: |302 bb.0:303 liveins: $r0, $q0304 305 ; CHECK-LABEL: name: MVE_VLDRBU16306 ; CHECK: liveins: $r0, $q0307 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0308 ; CHECK: [[MVE_VLDRBU16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_post1:%[0-9]+]]:mqpr = MVE_VLDRBU16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s64))309 ; CHECK: $r0 = COPY [[MVE_VLDRBU16_post]]310 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0311 %0:tgpr = COPY $r0312 %1:mqpr = MVE_VLDRBU16 %0, 0, 0, $noreg, $noreg :: (load (s64), align 8)313 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg314 $r0 = COPY %2315 tBX_RET 14, $noreg, implicit $r0316 317...318---319name: MVE_VSTRWU32320tracksRegLiveness: true321registers:322 - { id: 0, class: gprnopc, preferred-register: '' }323 - { id: 1, class: mqpr, preferred-register: '' }324 - { id: 2, class: rgpr, preferred-register: '' }325liveins:326 - { reg: '$r0', virtual-reg: '%0' }327 - { reg: '$q0', virtual-reg: '%1' }328body: |329 bb.0:330 liveins: $r0, $q0331 332 ; CHECK-LABEL: name: MVE_VSTRWU32333 ; CHECK: liveins: $r0, $q0334 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0335 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0336 ; CHECK: [[MVE_VSTRWU32_post:%[0-9]+]]:rgpr = MVE_VSTRWU32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)337 ; CHECK: $r0 = COPY [[MVE_VSTRWU32_post]]338 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0339 %1:mqpr = COPY $q0340 %0:gprnopc = COPY $r0341 MVE_VSTRWU32 %1, %0, 0, 0, $noreg, $noreg :: (store (s128), align 8)342 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg343 $r0 = COPY %2344 tBX_RET 14, $noreg, implicit $r0345 346...347---348name: MVE_VSTRHU16349tracksRegLiveness: true350registers:351 - { id: 0, class: gprnopc, preferred-register: '' }352 - { id: 1, class: mqpr, preferred-register: '' }353 - { id: 2, class: rgpr, preferred-register: '' }354liveins:355 - { reg: '$r0', virtual-reg: '%0' }356 - { reg: '$q0', virtual-reg: '%1' }357body: |358 bb.0:359 liveins: $r0, $q0360 361 ; CHECK-LABEL: name: MVE_VSTRHU16362 ; CHECK: liveins: $r0, $q0363 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0364 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0365 ; CHECK: [[MVE_VSTRHU16_post:%[0-9]+]]:rgpr = MVE_VSTRHU16_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)366 ; CHECK: $r0 = COPY [[MVE_VSTRHU16_post]]367 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0368 %1:mqpr = COPY $q0369 %0:gprnopc = COPY $r0370 MVE_VSTRHU16 %1, %0, 0, 0, $noreg, $noreg :: (store (s128), align 8)371 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg372 $r0 = COPY %2373 tBX_RET 14, $noreg, implicit $r0374 375...376---377name: MVE_VSTRBU8378tracksRegLiveness: true379registers:380 - { id: 0, class: gprnopc, preferred-register: '' }381 - { id: 1, class: mqpr, preferred-register: '' }382 - { id: 2, class: rgpr, preferred-register: '' }383liveins:384 - { reg: '$r0', virtual-reg: '%0' }385 - { reg: '$q0', virtual-reg: '%1' }386body: |387 bb.0:388 liveins: $r0, $q0389 390 ; CHECK-LABEL: name: MVE_VSTRBU8391 ; CHECK: liveins: $r0, $q0392 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0393 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0394 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)395 ; CHECK: $r0 = COPY [[MVE_VSTRBU8_post]]396 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0397 %1:mqpr = COPY $q0398 %0:gprnopc = COPY $r0399 MVE_VSTRBU8 %1, %0, 0, 0, $noreg, $noreg :: (store (s128), align 8)400 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg401 $r0 = COPY %2402 tBX_RET 14, $noreg, implicit $r0403 404...405---406name: MVE_VSTRH32407tracksRegLiveness: true408registers:409 - { id: 0, class: tgpr, preferred-register: '' }410 - { id: 1, class: mqpr, preferred-register: '' }411 - { id: 2, class: rgpr, preferred-register: '' }412liveins:413 - { reg: '$r0', virtual-reg: '%0' }414 - { reg: '$q0', virtual-reg: '%1' }415body: |416 bb.0:417 liveins: $r0, $q0418 419 ; CHECK-LABEL: name: MVE_VSTRH32420 ; CHECK: liveins: $r0, $q0421 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0422 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0423 ; CHECK: [[MVE_VSTRH32_post:%[0-9]+]]:tgpr = MVE_VSTRH32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s64))424 ; CHECK: $r0 = COPY [[MVE_VSTRH32_post]]425 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0426 %1:mqpr = COPY $q0427 %0:tgpr = COPY $r0428 MVE_VSTRH32 %1, %0, 0, 0, $noreg, $noreg :: (store (s64), align 8)429 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg430 $r0 = COPY %2431 tBX_RET 14, $noreg, implicit $r0432 433...434---435name: MVE_VSTRB32436tracksRegLiveness: true437registers:438 - { id: 0, class: tgpr, preferred-register: '' }439 - { id: 1, class: mqpr, preferred-register: '' }440 - { id: 2, class: rgpr, preferred-register: '' }441liveins:442 - { reg: '$r0', virtual-reg: '%0' }443 - { reg: '$q0', virtual-reg: '%1' }444body: |445 bb.0:446 liveins: $r0, $q0447 448 ; CHECK-LABEL: name: MVE_VSTRB32449 ; CHECK: liveins: $r0, $q0450 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0451 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0452 ; CHECK: [[MVE_VSTRB32_post:%[0-9]+]]:tgpr = MVE_VSTRB32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s32), align 8)453 ; CHECK: $r0 = COPY [[MVE_VSTRB32_post]]454 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0455 %1:mqpr = COPY $q0456 %0:tgpr = COPY $r0457 MVE_VSTRB32 %1, %0, 0, 0, $noreg, $noreg :: (store (s32), align 8)458 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg459 $r0 = COPY %2460 tBX_RET 14, $noreg, implicit $r0461 462...463---464name: MVE_VSTRB16465tracksRegLiveness: true466registers:467 - { id: 0, class: tgpr, preferred-register: '' }468 - { id: 1, class: mqpr, preferred-register: '' }469 - { id: 2, class: rgpr, preferred-register: '' }470liveins:471 - { reg: '$r0', virtual-reg: '%0' }472 - { reg: '$q0', virtual-reg: '%1' }473body: |474 bb.0:475 liveins: $r0, $q0476 477 ; CHECK-LABEL: name: MVE_VSTRB16478 ; CHECK: liveins: $r0, $q0479 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0480 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0481 ; CHECK: [[MVE_VSTRB16_post:%[0-9]+]]:tgpr = MVE_VSTRB16_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s64))482 ; CHECK: $r0 = COPY [[MVE_VSTRB16_post]]483 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0484 %1:mqpr = COPY $q0485 %0:tgpr = COPY $r0486 MVE_VSTRB16 %1, %0, 0, 0, $noreg, $noreg :: (store (s64), align 8)487 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg488 $r0 = COPY %2489 tBX_RET 14, $noreg, implicit $r0490 491...492---493name: ld0ld4494tracksRegLiveness: true495registers:496 - { id: 0, class: gprnopc, preferred-register: '' }497 - { id: 1, class: mqpr, preferred-register: '' }498 - { id: 2, class: rgpr, preferred-register: '' }499 - { id: 3, class: mqpr, preferred-register: '' }500liveins:501 - { reg: '$r0', virtual-reg: '%0' }502 - { reg: '$q0', virtual-reg: '%1' }503body: |504 bb.0:505 liveins: $r0, $q0506 507 ; CHECK-LABEL: name: ld0ld4508 ; CHECK: liveins: $r0, $q0509 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0510 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)511 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg, $noreg :: (load (s128), align 8)512 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]513 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0514 %0:gprnopc = COPY $r0515 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)516 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg517 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)518 $r0 = COPY %2519 tBX_RET 14, $noreg, implicit $r0520 521...522---523name: ld4ld0524tracksRegLiveness: true525registers:526 - { id: 0, class: gprnopc, preferred-register: '' }527 - { id: 1, class: mqpr, preferred-register: '' }528 - { id: 2, class: rgpr, preferred-register: '' }529 - { id: 3, class: mqpr, preferred-register: '' }530liveins:531 - { reg: '$r0', virtual-reg: '%0' }532 - { reg: '$q0', virtual-reg: '%1' }533body: |534 bb.0:535 liveins: $r0, $q0536 537 ; CHECK-LABEL: name: ld4ld0538 ; CHECK: liveins: $r0, $q0539 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0540 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)541 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)542 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]543 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0544 %0:gprnopc = COPY $r0545 %1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)546 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg547 %3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)548 $r0 = COPY %2549 tBX_RET 14, $noreg, implicit $r0550 551...552---553name: ld0ld4ld0554tracksRegLiveness: true555registers:556 - { id: 0, class: gprnopc, preferred-register: '' }557 - { id: 1, class: mqpr, preferred-register: '' }558 - { id: 2, class: rgpr, preferred-register: '' }559 - { id: 3, class: mqpr, preferred-register: '' }560 - { id: 4, class: mqpr, preferred-register: '' }561liveins:562 - { reg: '$r0', virtual-reg: '%0' }563 - { reg: '$q0', virtual-reg: '%1' }564body: |565 bb.0:566 liveins: $r0, $q0567 568 ; CHECK-LABEL: name: ld0ld4ld0569 ; CHECK: liveins: $r0, $q0570 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0571 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)572 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)573 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)574 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]575 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0576 %0:gprnopc = COPY $r0577 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)578 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg579 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)580 %4:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)581 $r0 = COPY %2582 tBX_RET 14, $noreg, implicit $r0583 584...585---586name: ld4ld0ld4587tracksRegLiveness: true588registers:589 - { id: 0, class: gprnopc, preferred-register: '' }590 - { id: 1, class: mqpr, preferred-register: '' }591 - { id: 2, class: rgpr, preferred-register: '' }592 - { id: 3, class: mqpr, preferred-register: '' }593 - { id: 4, class: mqpr, preferred-register: '' }594liveins:595 - { reg: '$r0', virtual-reg: '%0' }596 - { reg: '$q0', virtual-reg: '%1' }597body: |598 bb.0:599 liveins: $r0, $q0600 601 ; CHECK-LABEL: name: ld4ld0ld4602 ; CHECK: liveins: $r0, $q0603 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0604 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)605 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)606 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg, $noreg :: (load (s128), align 8)607 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]608 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0609 %0:gprnopc = COPY $r0610 %1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)611 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg612 %3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)613 %4:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)614 $r0 = COPY %2615 tBX_RET 14, $noreg, implicit $r0616 617...618---619name: addload620tracksRegLiveness: true621registers:622 - { id: 0, class: gprnopc, preferred-register: '' }623 - { id: 1, class: mqpr, preferred-register: '' }624 - { id: 2, class: rgpr, preferred-register: '' }625 - { id: 3, class: mqpr, preferred-register: '' }626liveins:627 - { reg: '$r0', virtual-reg: '%0' }628 - { reg: '$q0', virtual-reg: '%1' }629body: |630 bb.0:631 liveins: $r0, $q0632 633 ; CHECK-LABEL: name: addload634 ; CHECK: liveins: $r0, $q0635 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0636 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)637 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg, $noreg :: (load (s128), align 8)638 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]639 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0640 %0:gprnopc = COPY $r0641 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg642 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)643 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)644 $r0 = COPY %2645 tBX_RET 14, $noreg, implicit $r0646 647...648---649name: sub650tracksRegLiveness: true651registers:652 - { id: 0, class: gprnopc, preferred-register: '' }653 - { id: 1, class: mqpr, preferred-register: '' }654 - { id: 2, class: rgpr, preferred-register: '' }655 - { id: 3, class: mqpr, preferred-register: '' }656liveins:657 - { reg: '$r0', virtual-reg: '%0' }658 - { reg: '$q0', virtual-reg: '%1' }659body: |660 bb.0:661 liveins: $r0, $q0662 663 ; CHECK-LABEL: name: sub664 ; CHECK: liveins: $r0, $q0665 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0666 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg, $noreg :: (load (s128), align 8)667 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg, $noreg :: (load (s128), align 8)668 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]669 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0670 %0:gprnopc = COPY $r0671 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)672 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg673 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)674 $r0 = COPY %2675 tBX_RET 14, $noreg, implicit $r0676 677...678---679name: otherUse680tracksRegLiveness: true681registers:682 - { id: 0, class: gprnopc, preferred-register: '' }683 - { id: 1, class: mqpr, preferred-register: '' }684 - { id: 2, class: rgpr, preferred-register: '' }685 - { id: 3, class: mqpr, preferred-register: '' }686liveins:687 - { reg: '$r0', virtual-reg: '%0' }688 - { reg: '$q0', virtual-reg: '%1' }689body: |690 bb.0:691 liveins: $r0, $q0692 693 ; CHECK-LABEL: name: otherUse694 ; CHECK: liveins: $r0, $q0695 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0696 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg697 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)698 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)699 ; CHECK: $r0 = COPY [[COPY]]700 ; CHECK: $r0 = COPY [[t2ADDri]]701 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0702 %0:gprnopc = COPY $r0703 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg704 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)705 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)706 $r0 = COPY %0707 $r0 = COPY %2708 tBX_RET 14, $noreg, implicit $r0709 710...711---712name: postincUse713tracksRegLiveness: true714registers:715 - { id: 0, class: rgpr, preferred-register: '' }716 - { id: 1, class: mqpr, preferred-register: '' }717 - { id: 2, class: rgpr, preferred-register: '' }718 - { id: 3, class: mqpr, preferred-register: '' }719 - { id: 4, class: rgpr, preferred-register: '' }720liveins:721 - { reg: '$r0', virtual-reg: '%0' }722 - { reg: '$q0', virtual-reg: '%1' }723body: |724 bb.0:725 liveins: $r0, $q0726 727 ; CHECK-LABEL: name: postincUse728 ; CHECK: liveins: $r0, $q0729 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0730 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg731 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)732 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)733 ; CHECK: $r0 = COPY [[t2ADDri]]734 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0735 %0:rgpr = COPY $r0736 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg737 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)738 %4:rgpr, %3:mqpr = MVE_VLDRWU32_post %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)739 $r0 = COPY %2740 tBX_RET 14, $noreg, implicit $r0741 742...743---744name: badScale745tracksRegLiveness: true746registers:747 - { id: 0, class: gprnopc, preferred-register: '' }748 - { id: 1, class: mqpr, preferred-register: '' }749 - { id: 2, class: rgpr, preferred-register: '' }750 - { id: 3, class: mqpr, preferred-register: '' }751liveins:752 - { reg: '$r0', virtual-reg: '%0' }753 - { reg: '$q0', virtual-reg: '%1' }754body: |755 bb.0:756 liveins: $r0, $q0757 758 ; CHECK-LABEL: name: badScale759 ; CHECK: liveins: $r0, $q0760 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0761 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)762 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 3, 14 /* CC::al */, $noreg, $noreg763 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)764 ; CHECK: $r0 = COPY [[t2SUBri]]765 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0766 %0:gprnopc = COPY $r0767 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)768 %2:rgpr = nuw t2SUBri %0, 3, 14, $noreg, $noreg769 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)770 $r0 = COPY %2771 tBX_RET 14, $noreg, implicit $r0772 773...774---775name: badRange776tracksRegLiveness: true777registers:778 - { id: 0, class: gprnopc, preferred-register: '' }779 - { id: 1, class: mqpr, preferred-register: '' }780 - { id: 2, class: rgpr, preferred-register: '' }781 - { id: 3, class: mqpr, preferred-register: '' }782liveins:783 - { reg: '$r0', virtual-reg: '%0' }784 - { reg: '$q0', virtual-reg: '%1' }785body: |786 bb.0:787 liveins: $r0, $q0788 789 ; CHECK-LABEL: name: badRange790 ; CHECK: liveins: $r0, $q0791 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0792 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)793 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], -300, 14 /* CC::al */, $noreg, $noreg794 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], -300, 0, $noreg, $noreg :: (load (s128), align 8)795 ; CHECK: $r0 = COPY [[t2SUBri]]796 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0797 %0:gprnopc = COPY $r0798 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)799 %2:rgpr = nuw t2SUBri %0, -300, 14, $noreg, $noreg800 %3:mqpr = MVE_VLDRWU32 %0, -300, 0, $noreg, $noreg :: (load (s128), align 8)801 $r0 = COPY %2802 tBX_RET 14, $noreg, implicit $r0803 804...805---806name: addUseOK807tracksRegLiveness: true808registers:809 - { id: 0, class: gprnopc, preferred-register: '' }810 - { id: 1, class: mqpr, preferred-register: '' }811 - { id: 2, class: rgpr, preferred-register: '' }812 - { id: 3, class: mqpr, preferred-register: '' }813 - { id: 4, class: rgpr, preferred-register: '' }814liveins:815 - { reg: '$r0', virtual-reg: '%0' }816 - { reg: '$q0', virtual-reg: '%1' }817body: |818 bb.0:819 liveins: $r0, $q0820 821 ; CHECK-LABEL: name: addUseOK822 ; CHECK: liveins: $r0, $q0823 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0824 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg, $noreg :: (load (s128), align 8)825 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg, $noreg :: (load (s128), align 8)826 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg827 ; CHECK: $r0 = COPY [[t2LSRri]]828 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0829 %0:gprnopc = COPY $r0830 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)831 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg832 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)833 %4:rgpr = nuw t2LSRri %2, 2, 14, $noreg, $noreg834 $r0 = COPY %4835 tBX_RET 14, $noreg, implicit $r0836 837...838---839name: addUseDom840tracksRegLiveness: true841registers:842 - { id: 0, class: gprnopc, preferred-register: '' }843 - { id: 1, class: mqpr, preferred-register: '' }844 - { id: 2, class: rgpr, preferred-register: '' }845 - { id: 3, class: mqpr, preferred-register: '' }846 - { id: 4, class: rgpr, preferred-register: '' }847liveins:848 - { reg: '$r0', virtual-reg: '%0' }849 - { reg: '$q0', virtual-reg: '%1' }850body: |851 bb.0:852 liveins: $r0, $q0853 854 ; CHECK-LABEL: name: addUseDom855 ; CHECK: liveins: $r0, $q0856 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0857 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg858 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[t2SUBri]], 2, 14 /* CC::al */, $noreg, $noreg859 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)860 ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)861 ; CHECK: $r0 = COPY [[t2LSRri]]862 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0863 %0:gprnopc = COPY $r0864 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg865 %4:rgpr = nuw t2LSRri %2, 2, 14, $noreg, $noreg866 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)867 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)868 $r0 = COPY %4869 tBX_RET 14, $noreg, implicit $r0870 871...872---873name: addUseKilled874tracksRegLiveness: true875registers:876 - { id: 0, class: gprnopc, preferred-register: '' }877 - { id: 1, class: mqpr, preferred-register: '' }878 - { id: 2, class: rgpr, preferred-register: '' }879 - { id: 3, class: mqpr, preferred-register: '' }880 - { id: 4, class: rgpr, preferred-register: '' }881liveins:882 - { reg: '$r0', virtual-reg: '%0' }883 - { reg: '$q0', virtual-reg: '%1' }884body: |885 bb.0:886 liveins: $r0, $q0887 888 ; CHECK-LABEL: name: addUseKilled889 ; CHECK: liveins: $r0, $q0890 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0891 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg, $noreg :: (load (s128), align 8)892 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg893 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg, $noreg :: (load (s128), align 8)894 ; CHECK: $r0 = COPY [[t2LSRri]]895 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0896 %0:gprnopc = COPY $r0897 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)898 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg899 %4:rgpr = nuw t2LSRri killed %2, 2, 14, $noreg, $noreg900 %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)901 $r0 = COPY %4902 tBX_RET 14, $noreg, implicit $r0903 904...905---906name: MVE_VLDRWU32_post907tracksRegLiveness: true908registers:909 - { id: 0, class: rgpr, preferred-register: '' }910 - { id: 1, class: mqpr, preferred-register: '' }911 - { id: 2, class: rgpr, preferred-register: '' }912liveins:913 - { reg: '$r0', virtual-reg: '%0' }914 - { reg: '$q0', virtual-reg: '%1' }915body: |916 bb.0:917 liveins: $r0, $q0918 919 ; CHECK-LABEL: name: MVE_VLDRWU32_post920 ; CHECK: liveins: $r0, $q0921 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0922 ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)923 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)924 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]925 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0926 %0:rgpr = COPY $r0927 %2:rgpr, %1:mqpr = MVE_VLDRWU32_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)928 %1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)929 $r0 = COPY %2930 tBX_RET 14, $noreg, implicit $r0931 932...933---934name: MVE_VLDRHU16_post935tracksRegLiveness: true936registers:937 - { id: 0, class: rgpr, preferred-register: '' }938 - { id: 1, class: mqpr, preferred-register: '' }939 - { id: 2, class: rgpr, preferred-register: '' }940liveins:941 - { reg: '$r0', virtual-reg: '%0' }942 - { reg: '$q0', virtual-reg: '%1' }943body: |944 bb.0:945 liveins: $r0, $q0946 947 ; CHECK-LABEL: name: MVE_VLDRHU16_post948 ; CHECK: liveins: $r0, $q0949 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0950 ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)951 ; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)952 ; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]]953 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0954 %0:rgpr = COPY $r0955 %2:rgpr, %1:mqpr = MVE_VLDRHU16_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)956 %1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)957 $r0 = COPY %2958 tBX_RET 14, $noreg, implicit $r0959 960...961---962name: MVE_VLDRBU8_post963tracksRegLiveness: true964registers:965 - { id: 0, class: rgpr, preferred-register: '' }966 - { id: 1, class: mqpr, preferred-register: '' }967 - { id: 2, class: rgpr, preferred-register: '' }968liveins:969 - { reg: '$r0', virtual-reg: '%0' }970 - { reg: '$q0', virtual-reg: '%1' }971body: |972 bb.0:973 liveins: $r0, $q0974 975 ; CHECK-LABEL: name: MVE_VLDRBU8_post976 ; CHECK: liveins: $r0, $q0977 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0978 ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)979 ; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)980 ; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]]981 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0982 %0:rgpr = COPY $r0983 %2:rgpr, %1:mqpr = MVE_VLDRBU8_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)984 %1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)985 $r0 = COPY %2986 tBX_RET 14, $noreg, implicit $r0987 988...989---990name: MVE_VLDRBS32_post991tracksRegLiveness: true992registers:993 - { id: 0, class: tgpr, preferred-register: '' }994 - { id: 1, class: mqpr, preferred-register: '' }995 - { id: 2, class: tgpr, preferred-register: '' }996liveins:997 - { reg: '$r0', virtual-reg: '%0' }998 - { reg: '$q0', virtual-reg: '%1' }999body: |1000 bb.0:1001 liveins: $r0, $q01002 1003 ; CHECK-LABEL: name: MVE_VLDRBS32_post1004 ; CHECK: liveins: $r0, $q01005 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01006 ; CHECK: [[MVE_VLDRBS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_post1:%[0-9]+]]:mqpr = MVE_VLDRBS32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1007 ; CHECK: [[MVE_VLDRBS32_:%[0-9]+]]:mqpr = MVE_VLDRBS32 [[MVE_VLDRBS32_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1008 ; CHECK: $r0 = COPY [[MVE_VLDRBS32_post]]1009 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01010 %0:tgpr = COPY $r01011 %2:tgpr, %1:mqpr = MVE_VLDRBS32_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1012 %1:mqpr = MVE_VLDRBS32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1013 $r0 = COPY %21014 tBX_RET 14, $noreg, implicit $r01015 1016...1017---1018name: MVE_VLDRBU32_post1019tracksRegLiveness: true1020registers:1021 - { id: 0, class: tgpr, preferred-register: '' }1022 - { id: 1, class: mqpr, preferred-register: '' }1023 - { id: 2, class: tgpr, preferred-register: '' }1024liveins:1025 - { reg: '$r0', virtual-reg: '%0' }1026 - { reg: '$q0', virtual-reg: '%1' }1027body: |1028 bb.0:1029 liveins: $r0, $q01030 1031 ; CHECK-LABEL: name: MVE_VLDRBU32_post1032 ; CHECK: liveins: $r0, $q01033 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01034 ; CHECK: [[MVE_VLDRBU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_post1:%[0-9]+]]:mqpr = MVE_VLDRBU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1035 ; CHECK: [[MVE_VLDRBU32_:%[0-9]+]]:mqpr = MVE_VLDRBU32 [[MVE_VLDRBU32_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1036 ; CHECK: $r0 = COPY [[MVE_VLDRBU32_post]]1037 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01038 %0:tgpr = COPY $r01039 %2:tgpr, %1:mqpr = MVE_VLDRBU32_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1040 %1:mqpr = MVE_VLDRBU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1041 $r0 = COPY %21042 tBX_RET 14, $noreg, implicit $r01043 1044...1045---1046name: MVE_VLDRHS32_post1047tracksRegLiveness: true1048registers:1049 - { id: 0, class: tgpr, preferred-register: '' }1050 - { id: 1, class: mqpr, preferred-register: '' }1051 - { id: 2, class: tgpr, preferred-register: '' }1052liveins:1053 - { reg: '$r0', virtual-reg: '%0' }1054 - { reg: '$q0', virtual-reg: '%1' }1055body: |1056 bb.0:1057 liveins: $r0, $q01058 1059 ; CHECK-LABEL: name: MVE_VLDRHS32_post1060 ; CHECK: liveins: $r0, $q01061 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01062 ; CHECK: [[MVE_VLDRHS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_post1:%[0-9]+]]:mqpr = MVE_VLDRHS32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1063 ; CHECK: [[MVE_VLDRHS32_:%[0-9]+]]:mqpr = MVE_VLDRHS32 [[MVE_VLDRHS32_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1064 ; CHECK: $r0 = COPY [[MVE_VLDRHS32_post]]1065 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01066 %0:tgpr = COPY $r01067 %2:tgpr, %1:mqpr = MVE_VLDRHS32_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1068 %1:mqpr = MVE_VLDRHS32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1069 $r0 = COPY %21070 tBX_RET 14, $noreg, implicit $r01071 1072...1073---1074name: MVE_VLDRHU32_post1075tracksRegLiveness: true1076registers:1077 - { id: 0, class: tgpr, preferred-register: '' }1078 - { id: 1, class: mqpr, preferred-register: '' }1079 - { id: 2, class: tgpr, preferred-register: '' }1080liveins:1081 - { reg: '$r0', virtual-reg: '%0' }1082 - { reg: '$q0', virtual-reg: '%1' }1083body: |1084 bb.0:1085 liveins: $r0, $q01086 1087 ; CHECK-LABEL: name: MVE_VLDRHU32_post1088 ; CHECK: liveins: $r0, $q01089 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01090 ; CHECK: [[MVE_VLDRHU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_post1:%[0-9]+]]:mqpr = MVE_VLDRHU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1091 ; CHECK: [[MVE_VLDRHU32_:%[0-9]+]]:mqpr = MVE_VLDRHU32 [[MVE_VLDRHU32_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1092 ; CHECK: $r0 = COPY [[MVE_VLDRHU32_post]]1093 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01094 %0:tgpr = COPY $r01095 %2:tgpr, %1:mqpr = MVE_VLDRHU32_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1096 %1:mqpr = MVE_VLDRHU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1097 $r0 = COPY %21098 tBX_RET 14, $noreg, implicit $r01099 1100...1101---1102name: MVE_VLDRBS16_post1103tracksRegLiveness: true1104registers:1105 - { id: 0, class: tgpr, preferred-register: '' }1106 - { id: 1, class: mqpr, preferred-register: '' }1107 - { id: 2, class: tgpr, preferred-register: '' }1108liveins:1109 - { reg: '$r0', virtual-reg: '%0' }1110 - { reg: '$q0', virtual-reg: '%1' }1111body: |1112 bb.0:1113 liveins: $r0, $q01114 1115 ; CHECK-LABEL: name: MVE_VLDRBS16_post1116 ; CHECK: liveins: $r0, $q01117 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01118 ; CHECK: [[MVE_VLDRBS16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_post1:%[0-9]+]]:mqpr = MVE_VLDRBS16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1119 ; CHECK: [[MVE_VLDRBS16_:%[0-9]+]]:mqpr = MVE_VLDRBS16 [[MVE_VLDRBS16_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1120 ; CHECK: $r0 = COPY [[MVE_VLDRBS16_post]]1121 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01122 %0:tgpr = COPY $r01123 %2:tgpr, %1:mqpr = MVE_VLDRBS16_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1124 %1:mqpr = MVE_VLDRBS16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1125 $r0 = COPY %21126 tBX_RET 14, $noreg, implicit $r01127 1128...1129---1130name: MVE_VLDRBU16_post1131tracksRegLiveness: true1132registers:1133 - { id: 0, class: tgpr, preferred-register: '' }1134 - { id: 1, class: mqpr, preferred-register: '' }1135 - { id: 2, class: tgpr, preferred-register: '' }1136liveins:1137 - { reg: '$r0', virtual-reg: '%0' }1138 - { reg: '$q0', virtual-reg: '%1' }1139body: |1140 bb.0:1141 liveins: $r0, $q01142 1143 ; CHECK-LABEL: name: MVE_VLDRBU16_post1144 ; CHECK: liveins: $r0, $q01145 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01146 ; CHECK: [[MVE_VLDRBU16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_post1:%[0-9]+]]:mqpr = MVE_VLDRBU16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1147 ; CHECK: [[MVE_VLDRBU16_:%[0-9]+]]:mqpr = MVE_VLDRBU16 [[MVE_VLDRBU16_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1148 ; CHECK: $r0 = COPY [[MVE_VLDRBU16_post]]1149 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01150 %0:tgpr = COPY $r01151 %2:tgpr, %1:mqpr = MVE_VLDRBU16_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1152 %1:mqpr = MVE_VLDRBU16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1153 $r0 = COPY %21154 tBX_RET 14, $noreg, implicit $r01155 1156...1157---1158name: MVE_VSTRWU32_post1159tracksRegLiveness: true1160registers:1161 - { id: 0, class: rgpr, preferred-register: '' }1162 - { id: 1, class: mqpr, preferred-register: '' }1163 - { id: 2, class: rgpr, preferred-register: '' }1164liveins:1165 - { reg: '$r0', virtual-reg: '%0' }1166 - { reg: '$q0', virtual-reg: '%1' }1167body: |1168 bb.0:1169 liveins: $r0, $q01170 1171 ; CHECK-LABEL: name: MVE_VSTRWU32_post1172 ; CHECK: liveins: $r0, $q01173 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01174 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r01175 ; CHECK: [[MVE_VSTRWU32_post:%[0-9]+]]:rgpr = MVE_VSTRWU32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1176 ; CHECK: MVE_VSTRWU32 [[COPY]], [[MVE_VSTRWU32_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1177 ; CHECK: $r0 = COPY [[MVE_VSTRWU32_post]]1178 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01179 %1:mqpr = COPY $q01180 %0:rgpr = COPY $r01181 %2:rgpr = MVE_VSTRWU32_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1182 MVE_VSTRWU32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1183 $r0 = COPY %21184 tBX_RET 14, $noreg, implicit $r01185 1186...1187---1188name: MVE_VSTRHU16_post1189tracksRegLiveness: true1190registers:1191 - { id: 0, class: rgpr, preferred-register: '' }1192 - { id: 1, class: mqpr, preferred-register: '' }1193 - { id: 2, class: rgpr, preferred-register: '' }1194liveins:1195 - { reg: '$r0', virtual-reg: '%0' }1196 - { reg: '$q0', virtual-reg: '%1' }1197body: |1198 bb.0:1199 liveins: $r0, $q01200 1201 ; CHECK-LABEL: name: MVE_VSTRHU16_post1202 ; CHECK: liveins: $r0, $q01203 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01204 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r01205 ; CHECK: [[MVE_VSTRHU16_post:%[0-9]+]]:rgpr = MVE_VSTRHU16_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1206 ; CHECK: MVE_VSTRHU16 [[COPY]], [[MVE_VSTRHU16_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1207 ; CHECK: $r0 = COPY [[MVE_VSTRHU16_post]]1208 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01209 %1:mqpr = COPY $q01210 %0:rgpr = COPY $r01211 %2:rgpr = MVE_VSTRHU16_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1212 MVE_VSTRHU16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1213 $r0 = COPY %21214 tBX_RET 14, $noreg, implicit $r01215 1216...1217---1218name: MVE_VSTRBU8_post1219tracksRegLiveness: true1220registers:1221 - { id: 0, class: rgpr, preferred-register: '' }1222 - { id: 1, class: mqpr, preferred-register: '' }1223 - { id: 2, class: rgpr, preferred-register: '' }1224liveins:1225 - { reg: '$r0', virtual-reg: '%0' }1226 - { reg: '$q0', virtual-reg: '%1' }1227body: |1228 bb.0:1229 liveins: $r0, $q01230 1231 ; CHECK-LABEL: name: MVE_VSTRBU8_post1232 ; CHECK: liveins: $r0, $q01233 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01234 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r01235 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1236 ; CHECK: MVE_VSTRBU8 [[COPY]], [[MVE_VSTRBU8_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1237 ; CHECK: $r0 = COPY [[MVE_VSTRBU8_post]]1238 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01239 %1:mqpr = COPY $q01240 %0:rgpr = COPY $r01241 %2:rgpr = MVE_VSTRBU8_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1242 MVE_VSTRBU8 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1243 $r0 = COPY %21244 tBX_RET 14, $noreg, implicit $r01245 1246...1247---1248name: MVE_VSTRH32_post1249tracksRegLiveness: true1250registers:1251 - { id: 0, class: tgpr, preferred-register: '' }1252 - { id: 1, class: mqpr, preferred-register: '' }1253 - { id: 2, class: tgpr, preferred-register: '' }1254liveins:1255 - { reg: '$r0', virtual-reg: '%0' }1256 - { reg: '$q0', virtual-reg: '%1' }1257body: |1258 bb.0:1259 liveins: $r0, $q01260 1261 ; CHECK-LABEL: name: MVE_VSTRH32_post1262 ; CHECK: liveins: $r0, $q01263 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01264 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01265 ; CHECK: [[MVE_VSTRH32_post:%[0-9]+]]:tgpr = MVE_VSTRH32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1266 ; CHECK: MVE_VSTRH32 [[COPY]], [[MVE_VSTRH32_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1267 ; CHECK: $r0 = COPY [[MVE_VSTRH32_post]]1268 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01269 %1:mqpr = COPY $q01270 %0:tgpr = COPY $r01271 %2:tgpr = MVE_VSTRH32_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1272 MVE_VSTRH32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1273 $r0 = COPY %21274 tBX_RET 14, $noreg, implicit $r01275 1276...1277---1278name: MVE_VSTRB32_post1279tracksRegLiveness: true1280registers:1281 - { id: 0, class: tgpr, preferred-register: '' }1282 - { id: 1, class: mqpr, preferred-register: '' }1283 - { id: 2, class: tgpr, preferred-register: '' }1284liveins:1285 - { reg: '$r0', virtual-reg: '%0' }1286 - { reg: '$q0', virtual-reg: '%1' }1287body: |1288 bb.0:1289 liveins: $r0, $q01290 1291 ; CHECK-LABEL: name: MVE_VSTRB32_post1292 ; CHECK: liveins: $r0, $q01293 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01294 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01295 ; CHECK: [[MVE_VSTRB32_post:%[0-9]+]]:tgpr = MVE_VSTRB32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1296 ; CHECK: MVE_VSTRB32 [[COPY]], [[MVE_VSTRB32_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1297 ; CHECK: $r0 = COPY [[MVE_VSTRB32_post]]1298 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01299 %1:mqpr = COPY $q01300 %0:tgpr = COPY $r01301 %2:tgpr = MVE_VSTRB32_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1302 MVE_VSTRB32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1303 $r0 = COPY %21304 tBX_RET 14, $noreg, implicit $r01305 1306...1307---1308name: MVE_VSTRB16_post1309tracksRegLiveness: true1310registers:1311 - { id: 0, class: tgpr, preferred-register: '' }1312 - { id: 1, class: mqpr, preferred-register: '' }1313 - { id: 2, class: tgpr, preferred-register: '' }1314liveins:1315 - { reg: '$r0', virtual-reg: '%0' }1316 - { reg: '$q0', virtual-reg: '%1' }1317body: |1318 bb.0:1319 liveins: $r0, $q01320 1321 ; CHECK-LABEL: name: MVE_VSTRB16_post1322 ; CHECK: liveins: $r0, $q01323 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01324 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01325 ; CHECK: [[MVE_VSTRB16_post:%[0-9]+]]:tgpr = MVE_VSTRB16_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1326 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1327 ; CHECK: $r0 = COPY [[MVE_VSTRB16_post]]1328 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01329 %1:mqpr = COPY $q01330 %0:tgpr = COPY $r01331 %2:tgpr = MVE_VSTRB16_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1332 MVE_VSTRB16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1333 $r0 = COPY %21334 tBX_RET 14, $noreg, implicit $r01335 1336...1337---1338name: MVE_VLDRWU32_pre1339tracksRegLiveness: true1340registers:1341 - { id: 0, class: rgpr, preferred-register: '' }1342 - { id: 1, class: mqpr, preferred-register: '' }1343 - { id: 2, class: rgpr, preferred-register: '' }1344liveins:1345 - { reg: '$r0', virtual-reg: '%0' }1346 - { reg: '$q0', virtual-reg: '%1' }1347body: |1348 bb.0:1349 liveins: $r0, $q01350 1351 ; CHECK-LABEL: name: MVE_VLDRWU32_pre1352 ; CHECK: liveins: $r0, $q01353 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r01354 ; CHECK: [[MVE_VLDRWU32_pre:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRWU32_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1355 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1356 ; CHECK: $r0 = COPY [[MVE_VLDRWU32_pre]]1357 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01358 %0:rgpr = COPY $r01359 %2:rgpr, %1:mqpr = MVE_VLDRWU32_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1360 %1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1361 $r0 = COPY %21362 tBX_RET 14, $noreg, implicit $r01363 1364...1365---1366name: MVE_VLDRHU16_pre1367tracksRegLiveness: true1368registers:1369 - { id: 0, class: rgpr, preferred-register: '' }1370 - { id: 1, class: mqpr, preferred-register: '' }1371 - { id: 2, class: rgpr, preferred-register: '' }1372liveins:1373 - { reg: '$r0', virtual-reg: '%0' }1374 - { reg: '$q0', virtual-reg: '%1' }1375body: |1376 bb.0:1377 liveins: $r0, $q01378 1379 ; CHECK-LABEL: name: MVE_VLDRHU16_pre1380 ; CHECK: liveins: $r0, $q01381 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r01382 ; CHECK: [[MVE_VLDRHU16_pre:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_pre1:%[0-9]+]]:mqpr = MVE_VLDRHU16_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1383 ; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1384 ; CHECK: $r0 = COPY [[MVE_VLDRHU16_pre]]1385 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01386 %0:rgpr = COPY $r01387 %2:rgpr, %1:mqpr = MVE_VLDRHU16_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1388 %1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1389 $r0 = COPY %21390 tBX_RET 14, $noreg, implicit $r01391 1392...1393---1394name: MVE_VLDRBU8_pre1395tracksRegLiveness: true1396registers:1397 - { id: 0, class: rgpr, preferred-register: '' }1398 - { id: 1, class: mqpr, preferred-register: '' }1399 - { id: 2, class: rgpr, preferred-register: '' }1400liveins:1401 - { reg: '$r0', virtual-reg: '%0' }1402 - { reg: '$q0', virtual-reg: '%1' }1403body: |1404 bb.0:1405 liveins: $r0, $q01406 1407 ; CHECK-LABEL: name: MVE_VLDRBU8_pre1408 ; CHECK: liveins: $r0, $q01409 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r01410 ; CHECK: [[MVE_VLDRBU8_pre:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU8_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1411 ; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1412 ; CHECK: $r0 = COPY [[MVE_VLDRBU8_pre]]1413 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01414 %0:rgpr = COPY $r01415 %2:rgpr, %1:mqpr = MVE_VLDRBU8_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1416 %1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1417 $r0 = COPY %21418 tBX_RET 14, $noreg, implicit $r01419 1420...1421---1422name: MVE_VLDRBS32_pre1423tracksRegLiveness: true1424registers:1425 - { id: 0, class: tgpr, preferred-register: '' }1426 - { id: 1, class: mqpr, preferred-register: '' }1427 - { id: 2, class: tgpr, preferred-register: '' }1428liveins:1429 - { reg: '$r0', virtual-reg: '%0' }1430 - { reg: '$q0', virtual-reg: '%1' }1431body: |1432 bb.0:1433 liveins: $r0, $q01434 1435 ; CHECK-LABEL: name: MVE_VLDRBS32_pre1436 ; CHECK: liveins: $r0, $q01437 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01438 ; CHECK: [[MVE_VLDRBS32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_pre1:%[0-9]+]]:mqpr = MVE_VLDRBS32_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1439 ; CHECK: [[MVE_VLDRBS32_:%[0-9]+]]:mqpr = MVE_VLDRBS32 [[MVE_VLDRBS32_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1440 ; CHECK: $r0 = COPY [[MVE_VLDRBS32_pre]]1441 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01442 %0:tgpr = COPY $r01443 %2:tgpr, %1:mqpr = MVE_VLDRBS32_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1444 %1:mqpr = MVE_VLDRBS32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1445 $r0 = COPY %21446 tBX_RET 14, $noreg, implicit $r01447 1448...1449---1450name: MVE_VLDRBU32_pre1451tracksRegLiveness: true1452registers:1453 - { id: 0, class: tgpr, preferred-register: '' }1454 - { id: 1, class: mqpr, preferred-register: '' }1455 - { id: 2, class: tgpr, preferred-register: '' }1456liveins:1457 - { reg: '$r0', virtual-reg: '%0' }1458 - { reg: '$q0', virtual-reg: '%1' }1459body: |1460 bb.0:1461 liveins: $r0, $q01462 1463 ; CHECK-LABEL: name: MVE_VLDRBU32_pre1464 ; CHECK: liveins: $r0, $q01465 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01466 ; CHECK: [[MVE_VLDRBU32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU32_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1467 ; CHECK: [[MVE_VLDRBU32_:%[0-9]+]]:mqpr = MVE_VLDRBU32 [[MVE_VLDRBU32_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1468 ; CHECK: $r0 = COPY [[MVE_VLDRBU32_pre]]1469 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01470 %0:tgpr = COPY $r01471 %2:tgpr, %1:mqpr = MVE_VLDRBU32_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1472 %1:mqpr = MVE_VLDRBU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1473 $r0 = COPY %21474 tBX_RET 14, $noreg, implicit $r01475 1476...1477---1478name: MVE_VLDRHS32_pre1479tracksRegLiveness: true1480registers:1481 - { id: 0, class: tgpr, preferred-register: '' }1482 - { id: 1, class: mqpr, preferred-register: '' }1483 - { id: 2, class: tgpr, preferred-register: '' }1484liveins:1485 - { reg: '$r0', virtual-reg: '%0' }1486 - { reg: '$q0', virtual-reg: '%1' }1487body: |1488 bb.0:1489 liveins: $r0, $q01490 1491 ; CHECK-LABEL: name: MVE_VLDRHS32_pre1492 ; CHECK: liveins: $r0, $q01493 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01494 ; CHECK: [[MVE_VLDRHS32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_pre1:%[0-9]+]]:mqpr = MVE_VLDRHS32_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1495 ; CHECK: [[MVE_VLDRHS32_:%[0-9]+]]:mqpr = MVE_VLDRHS32 [[MVE_VLDRHS32_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1496 ; CHECK: $r0 = COPY [[MVE_VLDRHS32_pre]]1497 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01498 %0:tgpr = COPY $r01499 %2:tgpr, %1:mqpr = MVE_VLDRHS32_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1500 %1:mqpr = MVE_VLDRHS32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1501 $r0 = COPY %21502 tBX_RET 14, $noreg, implicit $r01503 1504...1505---1506name: MVE_VLDRHU32_pre1507tracksRegLiveness: true1508registers:1509 - { id: 0, class: tgpr, preferred-register: '' }1510 - { id: 1, class: mqpr, preferred-register: '' }1511 - { id: 2, class: tgpr, preferred-register: '' }1512liveins:1513 - { reg: '$r0', virtual-reg: '%0' }1514 - { reg: '$q0', virtual-reg: '%1' }1515body: |1516 bb.0:1517 liveins: $r0, $q01518 1519 ; CHECK-LABEL: name: MVE_VLDRHU32_pre1520 ; CHECK: liveins: $r0, $q01521 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01522 ; CHECK: [[MVE_VLDRHU32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRHU32_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1523 ; CHECK: [[MVE_VLDRHU32_:%[0-9]+]]:mqpr = MVE_VLDRHU32 [[MVE_VLDRHU32_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1524 ; CHECK: $r0 = COPY [[MVE_VLDRHU32_pre]]1525 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01526 %0:tgpr = COPY $r01527 %2:tgpr, %1:mqpr = MVE_VLDRHU32_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1528 %1:mqpr = MVE_VLDRHU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1529 $r0 = COPY %21530 tBX_RET 14, $noreg, implicit $r01531 1532...1533---1534name: MVE_VLDRBS16_pre1535tracksRegLiveness: true1536registers:1537 - { id: 0, class: tgpr, preferred-register: '' }1538 - { id: 1, class: mqpr, preferred-register: '' }1539 - { id: 2, class: tgpr, preferred-register: '' }1540liveins:1541 - { reg: '$r0', virtual-reg: '%0' }1542 - { reg: '$q0', virtual-reg: '%1' }1543body: |1544 bb.0:1545 liveins: $r0, $q01546 1547 ; CHECK-LABEL: name: MVE_VLDRBS16_pre1548 ; CHECK: liveins: $r0, $q01549 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01550 ; CHECK: [[MVE_VLDRBS16_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_pre1:%[0-9]+]]:mqpr = MVE_VLDRBS16_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1551 ; CHECK: [[MVE_VLDRBS16_:%[0-9]+]]:mqpr = MVE_VLDRBS16 [[MVE_VLDRBS16_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1552 ; CHECK: $r0 = COPY [[MVE_VLDRBS16_pre]]1553 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01554 %0:tgpr = COPY $r01555 %2:tgpr, %1:mqpr = MVE_VLDRBS16_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1556 %1:mqpr = MVE_VLDRBS16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1557 $r0 = COPY %21558 tBX_RET 14, $noreg, implicit $r01559 1560...1561---1562name: MVE_VLDRBU16_pre1563tracksRegLiveness: true1564registers:1565 - { id: 0, class: tgpr, preferred-register: '' }1566 - { id: 1, class: mqpr, preferred-register: '' }1567 - { id: 2, class: tgpr, preferred-register: '' }1568liveins:1569 - { reg: '$r0', virtual-reg: '%0' }1570 - { reg: '$q0', virtual-reg: '%1' }1571body: |1572 bb.0:1573 liveins: $r0, $q01574 1575 ; CHECK-LABEL: name: MVE_VLDRBU16_pre1576 ; CHECK: liveins: $r0, $q01577 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r01578 ; CHECK: [[MVE_VLDRBU16_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU16_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)1579 ; CHECK: [[MVE_VLDRBU16_:%[0-9]+]]:mqpr = MVE_VLDRBU16 [[MVE_VLDRBU16_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)1580 ; CHECK: $r0 = COPY [[MVE_VLDRBU16_pre]]1581 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01582 %0:tgpr = COPY $r01583 %2:tgpr, %1:mqpr = MVE_VLDRBU16_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)1584 %1:mqpr = MVE_VLDRBU16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)1585 $r0 = COPY %21586 tBX_RET 14, $noreg, implicit $r01587 1588...1589---1590name: MVE_VSTRWU32_pre1591tracksRegLiveness: true1592registers:1593 - { id: 0, class: rgpr, preferred-register: '' }1594 - { id: 1, class: mqpr, preferred-register: '' }1595 - { id: 2, class: rgpr, preferred-register: '' }1596liveins:1597 - { reg: '$r0', virtual-reg: '%0' }1598 - { reg: '$q0', virtual-reg: '%1' }1599body: |1600 bb.0:1601 liveins: $r0, $q01602 1603 ; CHECK-LABEL: name: MVE_VSTRWU32_pre1604 ; CHECK: liveins: $r0, $q01605 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01606 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r01607 ; CHECK: [[MVE_VSTRWU32_pre:%[0-9]+]]:rgpr = MVE_VSTRWU32_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1608 ; CHECK: MVE_VSTRWU32 [[COPY]], [[MVE_VSTRWU32_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1609 ; CHECK: $r0 = COPY [[MVE_VSTRWU32_pre]]1610 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01611 %1:mqpr = COPY $q01612 %0:rgpr = COPY $r01613 %2:rgpr = MVE_VSTRWU32_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1614 MVE_VSTRWU32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1615 $r0 = COPY %21616 tBX_RET 14, $noreg, implicit $r01617 1618...1619---1620name: MVE_VSTRHU16_pre1621tracksRegLiveness: true1622registers:1623 - { id: 0, class: rgpr, preferred-register: '' }1624 - { id: 1, class: mqpr, preferred-register: '' }1625 - { id: 2, class: rgpr, preferred-register: '' }1626liveins:1627 - { reg: '$r0', virtual-reg: '%0' }1628 - { reg: '$q0', virtual-reg: '%1' }1629body: |1630 bb.0:1631 liveins: $r0, $q01632 1633 ; CHECK-LABEL: name: MVE_VSTRHU16_pre1634 ; CHECK: liveins: $r0, $q01635 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01636 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r01637 ; CHECK: [[MVE_VSTRHU16_pre:%[0-9]+]]:rgpr = MVE_VSTRHU16_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1638 ; CHECK: MVE_VSTRHU16 [[COPY]], [[MVE_VSTRHU16_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1639 ; CHECK: $r0 = COPY [[MVE_VSTRHU16_pre]]1640 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01641 %1:mqpr = COPY $q01642 %0:rgpr = COPY $r01643 %2:rgpr = MVE_VSTRHU16_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1644 MVE_VSTRHU16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1645 $r0 = COPY %21646 tBX_RET 14, $noreg, implicit $r01647 1648...1649---1650name: MVE_VSTRBU8_pre1651tracksRegLiveness: true1652registers:1653 - { id: 0, class: rgpr, preferred-register: '' }1654 - { id: 1, class: mqpr, preferred-register: '' }1655 - { id: 2, class: rgpr, preferred-register: '' }1656liveins:1657 - { reg: '$r0', virtual-reg: '%0' }1658 - { reg: '$q0', virtual-reg: '%1' }1659body: |1660 bb.0:1661 liveins: $r0, $q01662 1663 ; CHECK-LABEL: name: MVE_VSTRBU8_pre1664 ; CHECK: liveins: $r0, $q01665 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01666 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r01667 ; CHECK: [[MVE_VSTRBU8_pre:%[0-9]+]]:rgpr = MVE_VSTRBU8_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1668 ; CHECK: MVE_VSTRBU8 [[COPY]], [[MVE_VSTRBU8_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1669 ; CHECK: $r0 = COPY [[MVE_VSTRBU8_pre]]1670 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01671 %1:mqpr = COPY $q01672 %0:rgpr = COPY $r01673 %2:rgpr = MVE_VSTRBU8_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1674 MVE_VSTRBU8 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1675 $r0 = COPY %21676 tBX_RET 14, $noreg, implicit $r01677 1678...1679---1680name: MVE_VSTRH32_pre1681tracksRegLiveness: true1682registers:1683 - { id: 0, class: tgpr, preferred-register: '' }1684 - { id: 1, class: mqpr, preferred-register: '' }1685 - { id: 2, class: tgpr, preferred-register: '' }1686liveins:1687 - { reg: '$r0', virtual-reg: '%0' }1688 - { reg: '$q0', virtual-reg: '%1' }1689body: |1690 bb.0:1691 liveins: $r0, $q01692 1693 ; CHECK-LABEL: name: MVE_VSTRH32_pre1694 ; CHECK: liveins: $r0, $q01695 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01696 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01697 ; CHECK: [[MVE_VSTRH32_pre:%[0-9]+]]:tgpr = MVE_VSTRH32_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1698 ; CHECK: MVE_VSTRH32 [[COPY]], [[MVE_VSTRH32_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1699 ; CHECK: $r0 = COPY [[MVE_VSTRH32_pre]]1700 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01701 %1:mqpr = COPY $q01702 %0:tgpr = COPY $r01703 %2:tgpr = MVE_VSTRH32_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1704 MVE_VSTRH32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1705 $r0 = COPY %21706 tBX_RET 14, $noreg, implicit $r01707 1708...1709---1710name: MVE_VSTRB32_pre1711tracksRegLiveness: true1712registers:1713 - { id: 0, class: tgpr, preferred-register: '' }1714 - { id: 1, class: mqpr, preferred-register: '' }1715 - { id: 2, class: tgpr, preferred-register: '' }1716liveins:1717 - { reg: '$r0', virtual-reg: '%0' }1718 - { reg: '$q0', virtual-reg: '%1' }1719body: |1720 bb.0:1721 liveins: $r0, $q01722 1723 ; CHECK-LABEL: name: MVE_VSTRB32_pre1724 ; CHECK: liveins: $r0, $q01725 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01726 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01727 ; CHECK: [[MVE_VSTRB32_pre:%[0-9]+]]:tgpr = MVE_VSTRB32_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1728 ; CHECK: MVE_VSTRB32 [[COPY]], [[MVE_VSTRB32_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1729 ; CHECK: $r0 = COPY [[MVE_VSTRB32_pre]]1730 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01731 %1:mqpr = COPY $q01732 %0:tgpr = COPY $r01733 %2:tgpr = MVE_VSTRB32_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1734 MVE_VSTRB32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1735 $r0 = COPY %21736 tBX_RET 14, $noreg, implicit $r01737 1738...1739---1740name: MVE_VSTRB16_pre1741tracksRegLiveness: true1742registers:1743 - { id: 0, class: tgpr, preferred-register: '' }1744 - { id: 1, class: mqpr, preferred-register: '' }1745 - { id: 2, class: tgpr, preferred-register: '' }1746liveins:1747 - { reg: '$r0', virtual-reg: '%0' }1748 - { reg: '$q0', virtual-reg: '%1' }1749body: |1750 bb.0:1751 liveins: $r0, $q01752 1753 ; CHECK-LABEL: name: MVE_VSTRB16_pre1754 ; CHECK: liveins: $r0, $q01755 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01756 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01757 ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1758 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1759 ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]]1760 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01761 %1:mqpr = COPY $q01762 %0:tgpr = COPY $r01763 %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1764 MVE_VSTRB16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1765 $r0 = COPY %21766 tBX_RET 14, $noreg, implicit $r01767 1768...1769---1770name: multiple21771tracksRegLiveness: true1772registers:1773 - { id: 0, class: tgpr, preferred-register: '' }1774 - { id: 1, class: mqpr, preferred-register: '' }1775 - { id: 2, class: tgpr, preferred-register: '' }1776liveins:1777 - { reg: '$r0', virtual-reg: '%0' }1778 - { reg: '$q0', virtual-reg: '%1' }1779body: |1780 bb.0:1781 liveins: $r0, $q01782 1783 ; CHECK-LABEL: name: multiple21784 ; CHECK: liveins: $r0, $q01785 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01786 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01787 ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1788 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)1789 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -48, 0, $noreg, $noreg :: (store (s128), align 8)1790 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], 2, 0, $noreg, $noreg :: (store (s128), align 8)1791 ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]]1792 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01793 %1:mqpr = COPY $q01794 %0:tgpr = COPY $r01795 %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1796 MVE_VSTRB16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1797 MVE_VSTRB16 %1, %0, -16, 0, $noreg, $noreg :: (store (s128), align 8)1798 MVE_VSTRB16 %1, %0, 34, 0, $noreg, $noreg :: (store (s128), align 8)1799 $r0 = COPY %21800 tBX_RET 14, $noreg, implicit $r01801 1802...1803---1804name: multiple31805tracksRegLiveness: true1806registers:1807 - { id: 0, class: tgpr, preferred-register: '' }1808 - { id: 1, class: mqpr, preferred-register: '' }1809 - { id: 2, class: tgpr, preferred-register: '' }1810 - { id: 3, class: tgpr, preferred-register: '' }1811liveins:1812 - { reg: '$r0', virtual-reg: '%0' }1813 - { reg: '$q0', virtual-reg: '%1' }1814body: |1815 bb.0:1816 liveins: $r0, $q01817 1818 ; CHECK-LABEL: name: multiple31819 ; CHECK: liveins: $r0, $q01820 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01821 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01822 ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1823 ; CHECK: [[MVE_VSTRB16_pre1:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 64, 0, $noreg, $noreg :: (store (s128), align 8)1824 ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre1]], -48, 0, $noreg, $noreg :: (store (s128), align 8)1825 ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre1]]1826 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01827 %1:mqpr = COPY $q01828 %0:tgpr = COPY $r01829 %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1830 %3:tgpr = MVE_VSTRB16_pre %1, %0, 64, 0, $noreg, $noreg :: (store (s128), align 8)1831 MVE_VSTRB16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)1832 $r0 = COPY %31833 tBX_RET 14, $noreg, implicit $r01834 1835...1836---1837name: multiple41838tracksRegLiveness: true1839registers:1840 - { id: 0, class: tgpr, preferred-register: '' }1841 - { id: 1, class: mqpr, preferred-register: '' }1842 - { id: 2, class: tgpr, preferred-register: '' }1843 - { id: 3, class: tgpr, preferred-register: '' }1844liveins:1845 - { reg: '$r0', virtual-reg: '%0' }1846 - { reg: '$q0', virtual-reg: '%1' }1847body: |1848 bb.0:1849 liveins: $r0, $q01850 1851 ; CHECK-LABEL: name: multiple41852 ; CHECK: liveins: $r0, $q01853 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01854 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01855 ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)1856 ; CHECK: MVE_VSTRB16 [[COPY]], [[COPY1]], 0, 0, $noreg, $noreg :: (store (s128), align 8)1857 ; CHECK: [[t2ADDri:%[0-9]+]]:tgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg1858 ; CHECK: $r0 = COPY [[t2ADDri]]1859 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01860 %1:mqpr = COPY $q01861 %0:tgpr = COPY $r01862 %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)1863 MVE_VSTRB16 %1, %0, 0, 0, $noreg, $noreg :: (store (s128), align 8)1864 %3:tgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg1865 $r0 = COPY %31866 tBX_RET 14, $noreg, implicit $r01867 1868...1869---1870name: badScale21871tracksRegLiveness: true1872registers:1873 - { id: 0, class: tgpr, preferred-register: '' }1874 - { id: 1, class: mqpr, preferred-register: '' }1875 - { id: 2, class: tgpr, preferred-register: '' }1876liveins:1877 - { reg: '$r0', virtual-reg: '%0' }1878 - { reg: '$q0', virtual-reg: '%1' }1879body: |1880 bb.0:1881 liveins: $r0, $q01882 1883 ; CHECK-LABEL: name: badScale21884 ; CHECK: liveins: $r0, $q01885 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01886 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01887 ; CHECK: [[MVE_VSTRBU8_pre:%[0-9]+]]:tgpr = MVE_VSTRBU8_pre [[COPY]], [[COPY1]], 33, 0, $noreg, $noreg :: (store (s128), align 8)1888 ; CHECK: MVE_VSTRWU32 [[COPY]], [[COPY1]], 0, 0, $noreg, $noreg :: (store (s128), align 8)1889 ; CHECK: $r0 = COPY [[MVE_VSTRBU8_pre]]1890 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01891 %1:mqpr = COPY $q01892 %0:tgpr = COPY $r01893 %2:tgpr = MVE_VSTRBU8_pre %1, %0, 33, 0, $noreg, $noreg :: (store (s128), align 8)1894 MVE_VSTRWU32 %1, %0, 0, 0, $noreg, $noreg :: (store (s128), align 8)1895 $r0 = COPY %21896 tBX_RET 14, $noreg, implicit $r01897 1898...1899---1900name: badRange21901tracksRegLiveness: true1902registers:1903 - { id: 0, class: tgpr, preferred-register: '' }1904 - { id: 1, class: mqpr, preferred-register: '' }1905 - { id: 2, class: tgpr, preferred-register: '' }1906liveins:1907 - { reg: '$r0', virtual-reg: '%0' }1908 - { reg: '$q0', virtual-reg: '%1' }1909body: |1910 bb.0:1911 liveins: $r0, $q01912 1913 ; CHECK-LABEL: name: badRange21914 ; CHECK: liveins: $r0, $q01915 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01916 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01917 ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 100, 0, $noreg, $noreg :: (store (s128), align 8)1918 ; CHECK: MVE_VSTRB16 [[COPY]], [[COPY1]], -100, 0, $noreg, $noreg :: (store (s128), align 8)1919 ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]]1920 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01921 %1:mqpr = COPY $q01922 %0:tgpr = COPY $r01923 %2:tgpr = MVE_VSTRB16_pre %1, %0, 100, 0, $noreg, $noreg :: (store (s128), align 8)1924 MVE_VSTRB16 %1, %0, -100, 0, $noreg, $noreg :: (store (s128), align 8)1925 $r0 = COPY %21926 tBX_RET 14, $noreg, implicit $r01927 1928...1929---1930name: regtype1931tracksRegLiveness: true1932registers:1933 - { id: 0, class: tgpr, preferred-register: '' }1934 - { id: 1, class: mqpr, preferred-register: '' }1935 - { id: 2, class: rgpr, preferred-register: '' }1936 - { id: 3, class: rgpr, preferred-register: '' }1937liveins:1938 - { reg: '$r0', virtual-reg: '%0' }1939 - { reg: '$q0', virtual-reg: '%1' }1940body: |1941 bb.0:1942 liveins: $r0, $q01943 1944 ; CHECK-LABEL: name: regtype1945 ; CHECK: liveins: $r0, $q01946 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q01947 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r01948 ; CHECK: [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:tgpr = t2LDRB_POST [[COPY1]], 32, 14 /* CC::al */, $noreg :: (load (s8), align 2)1949 ; CHECK: MVE_VSTRB16 [[COPY]], [[t2LDRB_POST1]], -22, 0, $noreg, $noreg :: (store (s128), align 8)1950 ; CHECK: $r0 = COPY [[t2LDRB_POST1]]1951 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r01952 %1:mqpr = COPY $q01953 %0:tgpr = COPY $r01954 %2:rgpr = t2LDRBi12 %0:tgpr, 0, 14, $noreg :: (load (s8), align 2)1955 MVE_VSTRB16 %1, %0, 10, 0, $noreg, $noreg :: (store (s128), align 8)1956 %3:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg1957 $r0 = COPY %31958 tBX_RET 14, $noreg, implicit $r01959 1960...1961