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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {5; CHECK-LABEL: cmpeqz_v4i1:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vorr q2, q0, q18; CHECK-NEXT: vcmp.i32 eq, q2, zr9; CHECK-NEXT: vpsel q0, q0, q110; CHECK-NEXT: bx lr11entry:12 %c1 = icmp eq <4 x i32> %a, zeroinitializer13 %c2 = icmp eq <4 x i32> %b, zeroinitializer14 %o = and <4 x i1> %c1, %c215 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b16 ret <4 x i32> %s17}18 19define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {20; CHECK-LABEL: cmpnez_v4i1:21; CHECK: @ %bb.0: @ %entry22; CHECK-NEXT: vpt.i32 eq, q0, zr23; CHECK-NEXT: vcmpt.i32 ne, q1, zr24; CHECK-NEXT: vpsel q0, q0, q125; CHECK-NEXT: bx lr26entry:27 %c1 = icmp eq <4 x i32> %a, zeroinitializer28 %c2 = icmp ne <4 x i32> %b, zeroinitializer29 %o = and <4 x i1> %c1, %c230 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b31 ret <4 x i32> %s32}33 34define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {35; CHECK-LABEL: cmpsltz_v4i1:36; CHECK: @ %bb.0: @ %entry37; CHECK-NEXT: vpt.i32 eq, q0, zr38; CHECK-NEXT: vcmpt.s32 lt, q1, zr39; CHECK-NEXT: vpsel q0, q0, q140; CHECK-NEXT: bx lr41entry:42 %c1 = icmp eq <4 x i32> %a, zeroinitializer43 %c2 = icmp slt <4 x i32> %b, zeroinitializer44 %o = and <4 x i1> %c1, %c245 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b46 ret <4 x i32> %s47}48 49define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {50; CHECK-LABEL: cmpsgtz_v4i1:51; CHECK: @ %bb.0: @ %entry52; CHECK-NEXT: vpt.i32 eq, q0, zr53; CHECK-NEXT: vcmpt.s32 gt, q1, zr54; CHECK-NEXT: vpsel q0, q0, q155; CHECK-NEXT: bx lr56entry:57 %c1 = icmp eq <4 x i32> %a, zeroinitializer58 %c2 = icmp sgt <4 x i32> %b, zeroinitializer59 %o = and <4 x i1> %c1, %c260 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b61 ret <4 x i32> %s62}63 64define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {65; CHECK-LABEL: cmpslez_v4i1:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vpt.i32 eq, q0, zr68; CHECK-NEXT: vcmpt.s32 le, q1, zr69; CHECK-NEXT: vpsel q0, q0, q170; CHECK-NEXT: bx lr71entry:72 %c1 = icmp eq <4 x i32> %a, zeroinitializer73 %c2 = icmp sle <4 x i32> %b, zeroinitializer74 %o = and <4 x i1> %c1, %c275 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b76 ret <4 x i32> %s77}78 79define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {80; CHECK-LABEL: cmpsgez_v4i1:81; CHECK: @ %bb.0: @ %entry82; CHECK-NEXT: vpt.i32 eq, q0, zr83; CHECK-NEXT: vcmpt.s32 ge, q1, zr84; CHECK-NEXT: vpsel q0, q0, q185; CHECK-NEXT: bx lr86entry:87 %c1 = icmp eq <4 x i32> %a, zeroinitializer88 %c2 = icmp sge <4 x i32> %b, zeroinitializer89 %o = and <4 x i1> %c1, %c290 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b91 ret <4 x i32> %s92}93 94define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) {95; CHECK-LABEL: cmpultz_v4i1:96; CHECK: @ %bb.0: @ %entry97; CHECK-NEXT: vmov q0, q198; CHECK-NEXT: bx lr99entry:100 %c1 = icmp eq <4 x i32> %a, zeroinitializer101 %c2 = icmp ult <4 x i32> %b, zeroinitializer102 %o = and <4 x i1> %c1, %c2103 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b104 ret <4 x i32> %s105}106 107define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {108; CHECK-LABEL: cmpugtz_v4i1:109; CHECK: @ %bb.0: @ %entry110; CHECK-NEXT: vpt.i32 eq, q0, zr111; CHECK-NEXT: vcmpt.i32 ne, q1, zr112; CHECK-NEXT: vpsel q0, q0, q1113; CHECK-NEXT: bx lr114entry:115 %c1 = icmp eq <4 x i32> %a, zeroinitializer116 %c2 = icmp ugt <4 x i32> %b, zeroinitializer117 %o = and <4 x i1> %c1, %c2118 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b119 ret <4 x i32> %s120}121 122define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {123; CHECK-LABEL: cmpulez_v4i1:124; CHECK: @ %bb.0: @ %entry125; CHECK-NEXT: vmov.i32 q2, #0x0126; CHECK-NEXT: vpt.i32 eq, q0, zr127; CHECK-NEXT: vcmpt.u32 cs, q2, q1128; CHECK-NEXT: vpsel q0, q0, q1129; CHECK-NEXT: bx lr130entry:131 %c1 = icmp eq <4 x i32> %a, zeroinitializer132 %c2 = icmp ule <4 x i32> %b, zeroinitializer133 %o = and <4 x i1> %c1, %c2134 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b135 ret <4 x i32> %s136}137 138define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) {139; CHECK-LABEL: cmpugez_v4i1:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: vcmp.i32 eq, q0, zr142; CHECK-NEXT: vpsel q0, q0, q1143; CHECK-NEXT: bx lr144entry:145 %c1 = icmp eq <4 x i32> %a, zeroinitializer146 %c2 = icmp uge <4 x i32> %b, zeroinitializer147 %o = and <4 x i1> %c1, %c2148 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b149 ret <4 x i32> %s150}151 152 153 154define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {155; CHECK-LABEL: cmpeq_v4i1:156; CHECK: @ %bb.0: @ %entry157; CHECK-NEXT: vpt.i32 eq, q0, zr158; CHECK-NEXT: vcmpt.i32 eq, q1, q2159; CHECK-NEXT: vpsel q0, q0, q1160; CHECK-NEXT: bx lr161entry:162 %c1 = icmp eq <4 x i32> %a, zeroinitializer163 %c2 = icmp eq <4 x i32> %b, %c164 %o = and <4 x i1> %c1, %c2165 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b166 ret <4 x i32> %s167}168 169define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {170; CHECK-LABEL: cmpne_v4i1:171; CHECK: @ %bb.0: @ %entry172; CHECK-NEXT: vpt.i32 eq, q0, zr173; CHECK-NEXT: vcmpt.i32 ne, q1, q2174; CHECK-NEXT: vpsel q0, q0, q1175; CHECK-NEXT: bx lr176entry:177 %c1 = icmp eq <4 x i32> %a, zeroinitializer178 %c2 = icmp ne <4 x i32> %b, %c179 %o = and <4 x i1> %c1, %c2180 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b181 ret <4 x i32> %s182}183 184define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {185; CHECK-LABEL: cmpslt_v4i1:186; CHECK: @ %bb.0: @ %entry187; CHECK-NEXT: vpt.i32 eq, q0, zr188; CHECK-NEXT: vcmpt.s32 gt, q2, q1189; CHECK-NEXT: vpsel q0, q0, q1190; CHECK-NEXT: bx lr191entry:192 %c1 = icmp eq <4 x i32> %a, zeroinitializer193 %c2 = icmp slt <4 x i32> %b, %c194 %o = and <4 x i1> %c1, %c2195 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b196 ret <4 x i32> %s197}198 199define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {200; CHECK-LABEL: cmpsgt_v4i1:201; CHECK: @ %bb.0: @ %entry202; CHECK-NEXT: vpt.i32 eq, q0, zr203; CHECK-NEXT: vcmpt.s32 gt, q1, q2204; CHECK-NEXT: vpsel q0, q0, q1205; CHECK-NEXT: bx lr206entry:207 %c1 = icmp eq <4 x i32> %a, zeroinitializer208 %c2 = icmp sgt <4 x i32> %b, %c209 %o = and <4 x i1> %c1, %c2210 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b211 ret <4 x i32> %s212}213 214define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {215; CHECK-LABEL: cmpsle_v4i1:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vpt.i32 eq, q0, zr218; CHECK-NEXT: vcmpt.s32 ge, q2, q1219; CHECK-NEXT: vpsel q0, q0, q1220; CHECK-NEXT: bx lr221entry:222 %c1 = icmp eq <4 x i32> %a, zeroinitializer223 %c2 = icmp sle <4 x i32> %b, %c224 %o = and <4 x i1> %c1, %c2225 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b226 ret <4 x i32> %s227}228 229define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {230; CHECK-LABEL: cmpsge_v4i1:231; CHECK: @ %bb.0: @ %entry232; CHECK-NEXT: vpt.i32 eq, q0, zr233; CHECK-NEXT: vcmpt.s32 ge, q1, q2234; CHECK-NEXT: vpsel q0, q0, q1235; CHECK-NEXT: bx lr236entry:237 %c1 = icmp eq <4 x i32> %a, zeroinitializer238 %c2 = icmp sge <4 x i32> %b, %c239 %o = and <4 x i1> %c1, %c2240 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b241 ret <4 x i32> %s242}243 244define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {245; CHECK-LABEL: cmpult_v4i1:246; CHECK: @ %bb.0: @ %entry247; CHECK-NEXT: vpt.i32 eq, q0, zr248; CHECK-NEXT: vcmpt.u32 hi, q2, q1249; CHECK-NEXT: vpsel q0, q0, q1250; CHECK-NEXT: bx lr251entry:252 %c1 = icmp eq <4 x i32> %a, zeroinitializer253 %c2 = icmp ult <4 x i32> %b, %c254 %o = and <4 x i1> %c1, %c2255 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b256 ret <4 x i32> %s257}258 259define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {260; CHECK-LABEL: cmpugt_v4i1:261; CHECK: @ %bb.0: @ %entry262; CHECK-NEXT: vpt.i32 eq, q0, zr263; CHECK-NEXT: vcmpt.u32 hi, q1, q2264; CHECK-NEXT: vpsel q0, q0, q1265; CHECK-NEXT: bx lr266entry:267 %c1 = icmp eq <4 x i32> %a, zeroinitializer268 %c2 = icmp ugt <4 x i32> %b, %c269 %o = and <4 x i1> %c1, %c2270 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b271 ret <4 x i32> %s272}273 274define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {275; CHECK-LABEL: cmpule_v4i1:276; CHECK: @ %bb.0: @ %entry277; CHECK-NEXT: vpt.i32 eq, q0, zr278; CHECK-NEXT: vcmpt.u32 cs, q2, q1279; CHECK-NEXT: vpsel q0, q0, q1280; CHECK-NEXT: bx lr281entry:282 %c1 = icmp eq <4 x i32> %a, zeroinitializer283 %c2 = icmp ule <4 x i32> %b, %c284 %o = and <4 x i1> %c1, %c2285 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b286 ret <4 x i32> %s287}288 289define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {290; CHECK-LABEL: cmpuge_v4i1:291; CHECK: @ %bb.0: @ %entry292; CHECK-NEXT: vpt.i32 eq, q0, zr293; CHECK-NEXT: vcmpt.u32 cs, q1, q2294; CHECK-NEXT: vpsel q0, q0, q1295; CHECK-NEXT: bx lr296entry:297 %c1 = icmp eq <4 x i32> %a, zeroinitializer298 %c2 = icmp uge <4 x i32> %b, %c299 %o = and <4 x i1> %c1, %c2300 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b301 ret <4 x i32> %s302}303 304 305define arm_aapcs_vfpcc <4 x i32> @cmpeqr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {306; CHECK-LABEL: cmpeqr_v4i1:307; CHECK: @ %bb.0: @ %entry308; CHECK-NEXT: vpt.i32 eq, q0, zr309; CHECK-NEXT: vcmpt.i32 eq, q1, r0310; CHECK-NEXT: vpsel q0, q0, q1311; CHECK-NEXT: bx lr312entry:313 %c1 = icmp eq <4 x i32> %a, zeroinitializer314 %i = insertelement <4 x i32> undef, i32 %c, i32 0315 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer316 %c2 = icmp eq <4 x i32> %b, %sp317 %o = and <4 x i1> %c1, %c2318 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b319 ret <4 x i32> %s320}321 322define arm_aapcs_vfpcc <4 x i32> @cmpner_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {323; CHECK-LABEL: cmpner_v4i1:324; CHECK: @ %bb.0: @ %entry325; CHECK-NEXT: vpt.i32 eq, q0, zr326; CHECK-NEXT: vcmpt.i32 ne, q1, r0327; CHECK-NEXT: vpsel q0, q0, q1328; CHECK-NEXT: bx lr329entry:330 %c1 = icmp eq <4 x i32> %a, zeroinitializer331 %i = insertelement <4 x i32> undef, i32 %c, i32 0332 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer333 %c2 = icmp ne <4 x i32> %b, %sp334 %o = and <4 x i1> %c1, %c2335 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b336 ret <4 x i32> %s337}338 339define arm_aapcs_vfpcc <4 x i32> @cmpsltr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {340; CHECK-LABEL: cmpsltr_v4i1:341; CHECK: @ %bb.0: @ %entry342; CHECK-NEXT: vpt.i32 eq, q0, zr343; CHECK-NEXT: vcmpt.s32 lt, q1, r0344; CHECK-NEXT: vpsel q0, q0, q1345; CHECK-NEXT: bx lr346entry:347 %c1 = icmp eq <4 x i32> %a, zeroinitializer348 %i = insertelement <4 x i32> undef, i32 %c, i32 0349 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer350 %c2 = icmp slt <4 x i32> %b, %sp351 %o = and <4 x i1> %c1, %c2352 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b353 ret <4 x i32> %s354}355 356define arm_aapcs_vfpcc <4 x i32> @cmpsgtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {357; CHECK-LABEL: cmpsgtr_v4i1:358; CHECK: @ %bb.0: @ %entry359; CHECK-NEXT: vpt.i32 eq, q0, zr360; CHECK-NEXT: vcmpt.s32 gt, q1, r0361; CHECK-NEXT: vpsel q0, q0, q1362; CHECK-NEXT: bx lr363entry:364 %c1 = icmp eq <4 x i32> %a, zeroinitializer365 %i = insertelement <4 x i32> undef, i32 %c, i32 0366 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer367 %c2 = icmp sgt <4 x i32> %b, %sp368 %o = and <4 x i1> %c1, %c2369 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b370 ret <4 x i32> %s371}372 373define arm_aapcs_vfpcc <4 x i32> @cmpsler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {374; CHECK-LABEL: cmpsler_v4i1:375; CHECK: @ %bb.0: @ %entry376; CHECK-NEXT: vpt.i32 eq, q0, zr377; CHECK-NEXT: vcmpt.s32 le, q1, r0378; CHECK-NEXT: vpsel q0, q0, q1379; CHECK-NEXT: bx lr380entry:381 %c1 = icmp eq <4 x i32> %a, zeroinitializer382 %i = insertelement <4 x i32> undef, i32 %c, i32 0383 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer384 %c2 = icmp sle <4 x i32> %b, %sp385 %o = and <4 x i1> %c1, %c2386 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b387 ret <4 x i32> %s388}389 390define arm_aapcs_vfpcc <4 x i32> @cmpsger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {391; CHECK-LABEL: cmpsger_v4i1:392; CHECK: @ %bb.0: @ %entry393; CHECK-NEXT: vpt.i32 eq, q0, zr394; CHECK-NEXT: vcmpt.s32 ge, q1, r0395; CHECK-NEXT: vpsel q0, q0, q1396; CHECK-NEXT: bx lr397entry:398 %c1 = icmp eq <4 x i32> %a, zeroinitializer399 %i = insertelement <4 x i32> undef, i32 %c, i32 0400 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer401 %c2 = icmp sge <4 x i32> %b, %sp402 %o = and <4 x i1> %c1, %c2403 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b404 ret <4 x i32> %s405}406 407define arm_aapcs_vfpcc <4 x i32> @cmpultr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {408; CHECK-LABEL: cmpultr_v4i1:409; CHECK: @ %bb.0: @ %entry410; CHECK-NEXT: vdup.32 q2, r0411; CHECK-NEXT: vpt.i32 eq, q0, zr412; CHECK-NEXT: vcmpt.u32 hi, q2, q1413; CHECK-NEXT: vpsel q0, q0, q1414; CHECK-NEXT: bx lr415entry:416 %c1 = icmp eq <4 x i32> %a, zeroinitializer417 %i = insertelement <4 x i32> undef, i32 %c, i32 0418 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer419 %c2 = icmp ult <4 x i32> %b, %sp420 %o = and <4 x i1> %c1, %c2421 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b422 ret <4 x i32> %s423}424 425define arm_aapcs_vfpcc <4 x i32> @cmpugtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {426; CHECK-LABEL: cmpugtr_v4i1:427; CHECK: @ %bb.0: @ %entry428; CHECK-NEXT: vpt.i32 eq, q0, zr429; CHECK-NEXT: vcmpt.u32 hi, q1, r0430; CHECK-NEXT: vpsel q0, q0, q1431; CHECK-NEXT: bx lr432entry:433 %c1 = icmp eq <4 x i32> %a, zeroinitializer434 %i = insertelement <4 x i32> undef, i32 %c, i32 0435 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer436 %c2 = icmp ugt <4 x i32> %b, %sp437 %o = and <4 x i1> %c1, %c2438 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b439 ret <4 x i32> %s440}441 442define arm_aapcs_vfpcc <4 x i32> @cmpuler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {443; CHECK-LABEL: cmpuler_v4i1:444; CHECK: @ %bb.0: @ %entry445; CHECK-NEXT: vdup.32 q2, r0446; CHECK-NEXT: vpt.i32 eq, q0, zr447; CHECK-NEXT: vcmpt.u32 cs, q2, q1448; CHECK-NEXT: vpsel q0, q0, q1449; CHECK-NEXT: bx lr450entry:451 %c1 = icmp eq <4 x i32> %a, zeroinitializer452 %i = insertelement <4 x i32> undef, i32 %c, i32 0453 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer454 %c2 = icmp ule <4 x i32> %b, %sp455 %o = and <4 x i1> %c1, %c2456 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b457 ret <4 x i32> %s458}459 460define arm_aapcs_vfpcc <4 x i32> @cmpuger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {461; CHECK-LABEL: cmpuger_v4i1:462; CHECK: @ %bb.0: @ %entry463; CHECK-NEXT: vpt.i32 eq, q0, zr464; CHECK-NEXT: vcmpt.u32 cs, q1, r0465; CHECK-NEXT: vpsel q0, q0, q1466; CHECK-NEXT: bx lr467entry:468 %c1 = icmp eq <4 x i32> %a, zeroinitializer469 %i = insertelement <4 x i32> undef, i32 %c, i32 0470 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer471 %c2 = icmp uge <4 x i32> %b, %sp472 %o = and <4 x i1> %c1, %c2473 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b474 ret <4 x i32> %s475}476 477 478 479define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {480; CHECK-LABEL: cmpeqz_v8i1:481; CHECK: @ %bb.0: @ %entry482; CHECK-NEXT: vorr q2, q0, q1483; CHECK-NEXT: vcmp.i16 eq, q2, zr484; CHECK-NEXT: vpsel q0, q0, q1485; CHECK-NEXT: bx lr486entry:487 %c1 = icmp eq <8 x i16> %a, zeroinitializer488 %c2 = icmp eq <8 x i16> %b, zeroinitializer489 %o = and <8 x i1> %c1, %c2490 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b491 ret <8 x i16> %s492}493 494define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {495; CHECK-LABEL: cmpeq_v8i1:496; CHECK: @ %bb.0: @ %entry497; CHECK-NEXT: vpt.i16 eq, q0, zr498; CHECK-NEXT: vcmpt.i16 eq, q1, q2499; CHECK-NEXT: vpsel q0, q0, q1500; CHECK-NEXT: bx lr501entry:502 %c1 = icmp eq <8 x i16> %a, zeroinitializer503 %c2 = icmp eq <8 x i16> %b, %c504 %o = and <8 x i1> %c1, %c2505 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b506 ret <8 x i16> %s507}508 509define arm_aapcs_vfpcc <8 x i16> @cmpeqr_v8i1(<8 x i16> %a, <8 x i16> %b, i16 %c) {510; CHECK-LABEL: cmpeqr_v8i1:511; CHECK: @ %bb.0: @ %entry512; CHECK-NEXT: vpt.i16 eq, q0, zr513; CHECK-NEXT: vcmpt.i16 eq, q1, r0514; CHECK-NEXT: vpsel q0, q0, q1515; CHECK-NEXT: bx lr516entry:517 %c1 = icmp eq <8 x i16> %a, zeroinitializer518 %i = insertelement <8 x i16> undef, i16 %c, i32 0519 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer520 %c2 = icmp eq <8 x i16> %b, %sp521 %o = and <8 x i1> %c1, %c2522 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b523 ret <8 x i16> %s524}525 526 527define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {528; CHECK-LABEL: cmpeqz_v16i1:529; CHECK: @ %bb.0: @ %entry530; CHECK-NEXT: vorr q2, q0, q1531; CHECK-NEXT: vcmp.i8 eq, q2, zr532; CHECK-NEXT: vpsel q0, q0, q1533; CHECK-NEXT: bx lr534entry:535 %c1 = icmp eq <16 x i8> %a, zeroinitializer536 %c2 = icmp eq <16 x i8> %b, zeroinitializer537 %o = and <16 x i1> %c1, %c2538 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b539 ret <16 x i8> %s540}541 542define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {543; CHECK-LABEL: cmpeq_v16i1:544; CHECK: @ %bb.0: @ %entry545; CHECK-NEXT: vpt.i8 eq, q0, zr546; CHECK-NEXT: vcmpt.i8 eq, q1, q2547; CHECK-NEXT: vpsel q0, q0, q1548; CHECK-NEXT: bx lr549entry:550 %c1 = icmp eq <16 x i8> %a, zeroinitializer551 %c2 = icmp eq <16 x i8> %b, %c552 %o = and <16 x i1> %c1, %c2553 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b554 ret <16 x i8> %s555}556 557define arm_aapcs_vfpcc <16 x i8> @cmpeqr_v16i1(<16 x i8> %a, <16 x i8> %b, i8 %c) {558; CHECK-LABEL: cmpeqr_v16i1:559; CHECK: @ %bb.0: @ %entry560; CHECK-NEXT: vpt.i8 eq, q0, zr561; CHECK-NEXT: vcmpt.i8 eq, q1, r0562; CHECK-NEXT: vpsel q0, q0, q1563; CHECK-NEXT: bx lr564entry:565 %c1 = icmp eq <16 x i8> %a, zeroinitializer566 %i = insertelement <16 x i8> undef, i8 %c, i32 0567 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer568 %c2 = icmp eq <16 x i8> %b, %sp569 %o = and <16 x i1> %c1, %c2570 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b571 ret <16 x i8> %s572}573 574 575define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {576; CHECK-LABEL: cmpeqz_v2i1:577; CHECK: @ %bb.0: @ %entry578; CHECK-NEXT: vorr q2, q0, q1579; CHECK-NEXT: vmov r0, r1, d4580; CHECK-NEXT: orrs r0, r1581; CHECK-NEXT: mov.w r1, #0582; CHECK-NEXT: csetm r0, eq583; CHECK-NEXT: bfi r1, r0, #0, #8584; CHECK-NEXT: vmov r0, r2, d5585; CHECK-NEXT: orrs r0, r2586; CHECK-NEXT: csetm r0, eq587; CHECK-NEXT: bfi r1, r0, #8, #8588; CHECK-NEXT: vmsr p0, r1589; CHECK-NEXT: vpsel q0, q0, q1590; CHECK-NEXT: bx lr591entry:592 %c1 = icmp eq <2 x i64> %a, zeroinitializer593 %c2 = icmp eq <2 x i64> %b, zeroinitializer594 %o = and <2 x i1> %c1, %c2595 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b596 ret <2 x i64> %s597}598 599define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {600; CHECK-LABEL: cmpeq_v2i1:601; CHECK: @ %bb.0: @ %entry602; CHECK-NEXT: vmov r0, r1, d4603; CHECK-NEXT: vmov r2, r3, d2604; CHECK-NEXT: eors r1, r3605; CHECK-NEXT: eors r0, r2606; CHECK-NEXT: orrs r0, r1607; CHECK-NEXT: vmov r1, r2, d0608; CHECK-NEXT: orrs r1, r2609; CHECK-NEXT: vmov r12, r2, d5610; CHECK-NEXT: cset r1, eq611; CHECK-NEXT: cmp r0, #0612; CHECK-NEXT: csel r0, zr, r1, ne613; CHECK-NEXT: movs r1, #0614; CHECK-NEXT: rsbs r0, r0, #0615; CHECK-NEXT: bfi r1, r0, #0, #8616; CHECK-NEXT: vmov r3, r0, d3617; CHECK-NEXT: eors r0, r2618; CHECK-NEXT: eor.w r2, r3, r12619; CHECK-NEXT: orrs r0, r2620; CHECK-NEXT: vmov r2, r3, d1621; CHECK-NEXT: orrs r2, r3622; CHECK-NEXT: cset r2, eq623; CHECK-NEXT: cmp r0, #0624; CHECK-NEXT: csel r0, zr, r2, ne625; CHECK-NEXT: rsbs r0, r0, #0626; CHECK-NEXT: bfi r1, r0, #8, #8627; CHECK-NEXT: vmsr p0, r1628; CHECK-NEXT: vpsel q0, q0, q1629; CHECK-NEXT: bx lr630entry:631 %c1 = icmp eq <2 x i64> %a, zeroinitializer632 %c2 = icmp eq <2 x i64> %b, %c633 %o = and <2 x i1> %c1, %c2634 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b635 ret <2 x i64> %s636}637 638define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c) {639; CHECK-LABEL: cmpeqr_v2i1:640; CHECK: @ %bb.0: @ %entry641; CHECK-NEXT: vmov r2, r3, d2642; CHECK-NEXT: eors r3, r1643; CHECK-NEXT: eors r2, r0644; CHECK-NEXT: orr.w r12, r2, r3645; CHECK-NEXT: vmov r3, r2, d0646; CHECK-NEXT: orrs r2, r3647; CHECK-NEXT: mov.w r3, #0648; CHECK-NEXT: cset r2, eq649; CHECK-NEXT: cmp.w r12, #0650; CHECK-NEXT: csel r2, zr, r2, ne651; CHECK-NEXT: rsbs r2, r2, #0652; CHECK-NEXT: bfi r3, r2, #0, #8653; CHECK-NEXT: vmov r12, r2, d3654; CHECK-NEXT: eors r1, r2655; CHECK-NEXT: eor.w r0, r0, r12656; CHECK-NEXT: orrs r0, r1657; CHECK-NEXT: vmov r1, r2, d1658; CHECK-NEXT: orrs r1, r2659; CHECK-NEXT: cset r1, eq660; CHECK-NEXT: cmp r0, #0661; CHECK-NEXT: csel r0, zr, r1, ne662; CHECK-NEXT: rsbs r0, r0, #0663; CHECK-NEXT: bfi r3, r0, #8, #8664; CHECK-NEXT: vmsr p0, r3665; CHECK-NEXT: vpsel q0, q0, q1666; CHECK-NEXT: bx lr667entry:668 %c1 = icmp eq <2 x i64> %a, zeroinitializer669 %i = insertelement <2 x i64> undef, i64 %c, i32 0670 %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer671 %c2 = icmp eq <2 x i64> %b, %sp672 %o = and <2 x i1> %c1, %c2673 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b674 ret <2 x i64> %s675}676