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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4 5define arm_aapcs_vfpcc <4 x i32> @build_true_v4i1(<4 x i32> %a, <4 x i32> %b) {6; CHECK-LABEL: build_true_v4i1:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: bx lr9entry:10 %s = select <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i32> %a, <4 x i32> %b11 ret <4 x i32> %s12}13 14define arm_aapcs_vfpcc <4 x i32> @build_false_v4i1(<4 x i32> %a, <4 x i32> %b) {15; CHECK-LABEL: build_false_v4i1:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vmov q0, q118; CHECK-NEXT: bx lr19entry:20 %s = select <4 x i1> <i1 0, i1 0, i1 0, i1 0>, <4 x i32> %a, <4 x i32> %b21 ret <4 x i32> %s22}23 24define arm_aapcs_vfpcc <4 x i32> @build_upper_v4i1(<4 x i32> %a, <4 x i32> %b) {25; CHECK-LABEL: build_upper_v4i1:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: mov.w r0, #6528028; CHECK-NEXT: vmsr p0, r029; CHECK-NEXT: vpsel q0, q0, q130; CHECK-NEXT: bx lr31entry:32 %s = select <4 x i1> <i1 0, i1 0, i1 1, i1 1>, <4 x i32> %a, <4 x i32> %b33 ret <4 x i32> %s34}35 36define arm_aapcs_vfpcc <4 x i32> @build_lower_v4i1(<4 x i32> %a, <4 x i32> %b) {37; CHECK-LABEL: build_lower_v4i1:38; CHECK: @ %bb.0: @ %entry39; CHECK-NEXT: movs r0, #25540; CHECK-NEXT: vmsr p0, r041; CHECK-NEXT: vpsel q0, q0, q142; CHECK-NEXT: bx lr43entry:44 %s = select <4 x i1> <i1 1, i1 1, i1 0, i1 0>, <4 x i32> %a, <4 x i32> %b45 ret <4 x i32> %s46}47 48 49define arm_aapcs_vfpcc <8 x i16> @build_true_v8i1(<8 x i16> %a, <8 x i16> %b) {50; CHECK-LABEL: build_true_v8i1:51; CHECK: @ %bb.0: @ %entry52; CHECK-NEXT: bx lr53entry:54 %s = select <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <8 x i16> %a, <8 x i16> %b55 ret <8 x i16> %s56}57 58define arm_aapcs_vfpcc <8 x i16> @build_false_v8i1(<8 x i16> %a, <8 x i16> %b) {59; CHECK-LABEL: build_false_v8i1:60; CHECK: @ %bb.0: @ %entry61; CHECK-NEXT: vmov q0, q162; CHECK-NEXT: bx lr63entry:64 %s = select <8 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>, <8 x i16> %a, <8 x i16> %b65 ret <8 x i16> %s66}67 68define arm_aapcs_vfpcc <8 x i16> @build_upper_v8i1(<8 x i16> %a, <8 x i16> %b) {69; CHECK-LABEL: build_upper_v8i1:70; CHECK: @ %bb.0: @ %entry71; CHECK-NEXT: mov.w r0, #6528072; CHECK-NEXT: vmsr p0, r073; CHECK-NEXT: vpsel q0, q0, q174; CHECK-NEXT: bx lr75entry:76 %s = select <8 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1>, <8 x i16> %a, <8 x i16> %b77 ret <8 x i16> %s78}79 80define arm_aapcs_vfpcc <8 x i16> @build_lower_v8i1(<8 x i16> %a, <8 x i16> %b) {81; CHECK-LABEL: build_lower_v8i1:82; CHECK: @ %bb.0: @ %entry83; CHECK-NEXT: movs r0, #25584; CHECK-NEXT: vmsr p0, r085; CHECK-NEXT: vpsel q0, q0, q186; CHECK-NEXT: bx lr87entry:88 %s = select <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0>, <8 x i16> %a, <8 x i16> %b89 ret <8 x i16> %s90}91 92 93define arm_aapcs_vfpcc <16 x i8> @build_true_v16i1(<16 x i8> %a, <16 x i8> %b) {94; CHECK-LABEL: build_true_v16i1:95; CHECK: @ %bb.0: @ %entry96; CHECK-NEXT: bx lr97entry:98 %s = select <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i8> %a, <16 x i8> %b99 ret <16 x i8> %s100}101 102define arm_aapcs_vfpcc <16 x i8> @build_false_v16i1(<16 x i8> %a, <16 x i8> %b) {103; CHECK-LABEL: build_false_v16i1:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vmov q0, q1106; CHECK-NEXT: bx lr107entry:108 %s = select <16 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>, <16 x i8> %a, <16 x i8> %b109 ret <16 x i8> %s110}111 112define arm_aapcs_vfpcc <16 x i8> @build_upper_v16i1(<16 x i8> %a, <16 x i8> %b) {113; CHECK-LABEL: build_upper_v16i1:114; CHECK: @ %bb.0: @ %entry115; CHECK-NEXT: mov.w r0, #65280116; CHECK-NEXT: vmsr p0, r0117; CHECK-NEXT: vpsel q0, q0, q1118; CHECK-NEXT: bx lr119entry:120 %s = select <16 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i8> %a, <16 x i8> %b121 ret <16 x i8> %s122}123 124define arm_aapcs_vfpcc <16 x i8> @build_lower_v16i1(<16 x i8> %a, <16 x i8> %b) {125; CHECK-LABEL: build_lower_v16i1:126; CHECK: @ %bb.0: @ %entry127; CHECK-NEXT: movs r0, #255128; CHECK-NEXT: vmsr p0, r0129; CHECK-NEXT: vpsel q0, q0, q1130; CHECK-NEXT: bx lr131entry:132 %s = select <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>, <16 x i8> %a, <16 x i8> %b133 ret <16 x i8> %s134}135 136 137define arm_aapcs_vfpcc <2 x i64> @build_true_v2i1(<2 x i64> %a, <2 x i64> %b) {138; CHECK-LABEL: build_true_v2i1:139; CHECK: @ %bb.0: @ %entry140; CHECK-NEXT: bx lr141entry:142 %s = select <2 x i1> <i1 1, i1 1>, <2 x i64> %a, <2 x i64> %b143 ret <2 x i64> %s144}145 146define arm_aapcs_vfpcc <2 x i64> @build_false_v2i1(<2 x i64> %a, <2 x i64> %b) {147; CHECK-LABEL: build_false_v2i1:148; CHECK: @ %bb.0: @ %entry149; CHECK-NEXT: vmov q0, q1150; CHECK-NEXT: bx lr151entry:152 %s = select <2 x i1> <i1 0, i1 0>, <2 x i64> %a, <2 x i64> %b153 ret <2 x i64> %s154}155 156define arm_aapcs_vfpcc <2 x i64> @build_upper_v2i1(<2 x i64> %a, <2 x i64> %b) {157; CHECK-LABEL: build_upper_v2i1:158; CHECK: @ %bb.0: @ %entry159; CHECK-NEXT: mov.w r0, #65280160; CHECK-NEXT: vmsr p0, r0161; CHECK-NEXT: vpsel q0, q0, q1162; CHECK-NEXT: bx lr163entry:164 %s = select <2 x i1> <i1 0, i1 1>, <2 x i64> %a, <2 x i64> %b165 ret <2 x i64> %s166}167 168define arm_aapcs_vfpcc <2 x i64> @build_lower_v2i1(<2 x i64> %a, <2 x i64> %b) {169; CHECK-LABEL: build_lower_v2i1:170; CHECK: @ %bb.0: @ %entry171; CHECK-NEXT: movs r0, #255172; CHECK-NEXT: vmsr p0, r0173; CHECK-NEXT: vpsel q0, q0, q1174; CHECK-NEXT: bx lr175entry:176 %s = select <2 x i1> <i1 1, i1 0>, <2 x i64> %a, <2 x i64> %b177 ret <2 x i64> %s178}179