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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4 5define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {6; CHECK-LABEL: build_var0_v4i1:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: cmp r0, r19; CHECK-NEXT: mov.w r1, #010; CHECK-NEXT: csetm r0, lo11; CHECK-NEXT: bfi r1, r0, #0, #412; CHECK-NEXT: vmsr p0, r113; CHECK-NEXT: vpsel q0, q0, q114; CHECK-NEXT: bx lr15entry:16 %c = icmp ult i32 %s, %t17 %vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 018 %r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b19 ret <4 x i32> %r20}21 22define arm_aapcs_vfpcc <4 x i32> @build_var3_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {23; CHECK-LABEL: build_var3_v4i1:24; CHECK: @ %bb.0: @ %entry25; CHECK-NEXT: cmp r0, r126; CHECK-NEXT: mov.w r1, #027; CHECK-NEXT: csetm r0, lo28; CHECK-NEXT: bfi r1, r0, #12, #429; CHECK-NEXT: vmsr p0, r130; CHECK-NEXT: vpsel q0, q0, q131; CHECK-NEXT: bx lr32entry:33 %c = icmp ult i32 %s, %t34 %vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 335 %r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b36 ret <4 x i32> %r37}38 39define arm_aapcs_vfpcc <4 x i32> @build_varN_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {40; CHECK-LABEL: build_varN_v4i1:41; CHECK: @ %bb.0: @ %entry42; CHECK-NEXT: cmp r0, r143; CHECK-NEXT: csetm r0, lo44; CHECK-NEXT: vmsr p0, r045; CHECK-NEXT: vpsel q0, q0, q146; CHECK-NEXT: bx lr47entry:48 %c = icmp ult i32 %s, %t49 %vc1 = insertelement <4 x i1> undef, i1 %c, i64 050 %vc4 = shufflevector <4 x i1> %vc1, <4 x i1> undef, <4 x i32> zeroinitializer51 %r = select <4 x i1> %vc4, <4 x i32> %a, <4 x i32> %b52 ret <4 x i32> %r53}54 55 56define arm_aapcs_vfpcc <8 x i16> @build_var0_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {57; CHECK-LABEL: build_var0_v8i1:58; CHECK: @ %bb.0: @ %entry59; CHECK-NEXT: cmp r0, r160; CHECK-NEXT: mov.w r1, #061; CHECK-NEXT: csetm r0, lo62; CHECK-NEXT: bfi r1, r0, #0, #263; CHECK-NEXT: vmsr p0, r164; CHECK-NEXT: vpsel q0, q0, q165; CHECK-NEXT: bx lr66entry:67 %c = icmp ult i32 %s, %t68 %vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 069 %r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b70 ret <8 x i16> %r71}72 73define arm_aapcs_vfpcc <8 x i16> @build_var3_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {74; CHECK-LABEL: build_var3_v8i1:75; CHECK: @ %bb.0: @ %entry76; CHECK-NEXT: cmp r0, r177; CHECK-NEXT: mov.w r1, #078; CHECK-NEXT: csetm r0, lo79; CHECK-NEXT: bfi r1, r0, #6, #280; CHECK-NEXT: vmsr p0, r181; CHECK-NEXT: vpsel q0, q0, q182; CHECK-NEXT: bx lr83entry:84 %c = icmp ult i32 %s, %t85 %vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 386 %r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b87 ret <8 x i16> %r88}89 90define arm_aapcs_vfpcc <8 x i16> @build_varN_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {91; CHECK-LABEL: build_varN_v8i1:92; CHECK: @ %bb.0: @ %entry93; CHECK-NEXT: cmp r0, r194; CHECK-NEXT: csetm r0, lo95; CHECK-NEXT: vmsr p0, r096; CHECK-NEXT: vpsel q0, q0, q197; CHECK-NEXT: bx lr98entry:99 %c = icmp ult i32 %s, %t100 %vc1 = insertelement <8 x i1> undef, i1 %c, i64 0101 %vc4 = shufflevector <8 x i1> %vc1, <8 x i1> undef, <8 x i32> zeroinitializer102 %r = select <8 x i1> %vc4, <8 x i16> %a, <8 x i16> %b103 ret <8 x i16> %r104}105 106 107define arm_aapcs_vfpcc <16 x i8> @build_var0_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {108; CHECK-LABEL: build_var0_v16i1:109; CHECK: @ %bb.0: @ %entry110; CHECK-NEXT: cmp r0, r1111; CHECK-NEXT: mov.w r1, #0112; CHECK-NEXT: csetm r0, lo113; CHECK-NEXT: bfi r1, r0, #0, #1114; CHECK-NEXT: vmsr p0, r1115; CHECK-NEXT: vpsel q0, q0, q1116; CHECK-NEXT: bx lr117entry:118 %c = icmp ult i32 %s, %t119 %vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 0120 %r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b121 ret <16 x i8> %r122}123 124define arm_aapcs_vfpcc <16 x i8> @build_var3_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {125; CHECK-LABEL: build_var3_v16i1:126; CHECK: @ %bb.0: @ %entry127; CHECK-NEXT: cmp r0, r1128; CHECK-NEXT: mov.w r1, #0129; CHECK-NEXT: csetm r0, lo130; CHECK-NEXT: bfi r1, r0, #3, #1131; CHECK-NEXT: vmsr p0, r1132; CHECK-NEXT: vpsel q0, q0, q1133; CHECK-NEXT: bx lr134entry:135 %c = icmp ult i32 %s, %t136 %vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 3137 %r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b138 ret <16 x i8> %r139}140 141define arm_aapcs_vfpcc <16 x i8> @build_varN_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {142; CHECK-LABEL: build_varN_v16i1:143; CHECK: @ %bb.0: @ %entry144; CHECK-NEXT: cmp r0, r1145; CHECK-NEXT: csetm r0, lo146; CHECK-NEXT: vmsr p0, r0147; CHECK-NEXT: vpsel q0, q0, q1148; CHECK-NEXT: bx lr149entry:150 %c = icmp ult i32 %s, %t151 %vc1 = insertelement <16 x i1> undef, i1 %c, i64 0152 %vc4 = shufflevector <16 x i1> %vc1, <16 x i1> undef, <16 x i32> zeroinitializer153 %r = select <16 x i1> %vc4, <16 x i8> %a, <16 x i8> %b154 ret <16 x i8> %r155}156 157 158define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {159; CHECK-LABEL: build_var0_v2i1:160; CHECK: @ %bb.0: @ %entry161; CHECK-NEXT: cmp r0, r1162; CHECK-NEXT: mov.w r1, #0163; CHECK-NEXT: csetm r0, lo164; CHECK-NEXT: bfi r1, r0, #0, #8165; CHECK-NEXT: vmsr p0, r1166; CHECK-NEXT: vpsel q0, q0, q1167; CHECK-NEXT: bx lr168entry:169 %c = icmp ult i32 %s, %t170 %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 0171 %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b172 ret <2 x i64> %r173}174 175define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {176; CHECK-LABEL: build_var1_v2i1:177; CHECK: @ %bb.0: @ %entry178; CHECK-NEXT: cmp r0, r1179; CHECK-NEXT: mov.w r1, #0180; CHECK-NEXT: csetm r0, lo181; CHECK-NEXT: bfi r1, r0, #8, #8182; CHECK-NEXT: vmsr p0, r1183; CHECK-NEXT: vpsel q0, q0, q1184; CHECK-NEXT: bx lr185entry:186 %c = icmp ult i32 %s, %t187 %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 1188 %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b189 ret <2 x i64> %r190}191 192define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {193; CHECK-LABEL: build_varN_v2i1:194; CHECK: @ %bb.0: @ %entry195; CHECK-NEXT: cmp r0, r1196; CHECK-NEXT: csetm r0, lo197; CHECK-NEXT: vmsr p0, r0198; CHECK-NEXT: vpsel q0, q0, q1199; CHECK-NEXT: bx lr200entry:201 %c = icmp ult i32 %s, %t202 %vc1 = insertelement <2 x i1> undef, i1 %c, i64 0203 %vc4 = shufflevector <2 x i1> %vc1, <2 x i1> undef, <2 x i32> zeroinitializer204 %r = select <2 x i1> %vc4, <2 x i64> %a, <2 x i64> %b205 ret <2 x i64> %r206}207