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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc i32 @build_v2i_v2i1_1() {5; CHECK-LABEL: build_v2i_v2i1_1:6; CHECK: @ %bb.0:7; CHECK-NEXT: movw r0, #655358; CHECK-NEXT: bx lr9 %r = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> <i1 1, i1 1>)10 ret i32 %r11}12define arm_aapcs_vfpcc i32 @build_v2i_v2i1_0() {13; CHECK-LABEL: build_v2i_v2i1_0:14; CHECK: @ %bb.0:15; CHECK-NEXT: movs r0, #016; CHECK-NEXT: bx lr17 %r = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> <i1 0, i1 0>)18 ret i32 %r19}20define arm_aapcs_vfpcc i32 @build_v2i_v2i1_5() {21; CHECK-LABEL: build_v2i_v2i1_5:22; CHECK: @ %bb.0:23; CHECK-NEXT: mov.w r0, #6528024; CHECK-NEXT: bx lr25 %r = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> <i1 0, i1 1>)26 ret i32 %r27}28 29define arm_aapcs_vfpcc i32 @build_v2i_v4i1_1() {30; CHECK-LABEL: build_v2i_v4i1_1:31; CHECK: @ %bb.0:32; CHECK-NEXT: movw r0, #6553533; CHECK-NEXT: bx lr34 %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 1, i1 1, i1 1, i1 1>)35 ret i32 %r36}37define arm_aapcs_vfpcc i32 @build_v2i_v4i1_0() {38; CHECK-LABEL: build_v2i_v4i1_0:39; CHECK: @ %bb.0:40; CHECK-NEXT: movs r0, #041; CHECK-NEXT: bx lr42 %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 0, i1 0, i1 0>)43 ret i32 %r44}45define arm_aapcs_vfpcc i32 @build_v2i_v4i1_5() {46; CHECK-LABEL: build_v2i_v4i1_5:47; CHECK: @ %bb.0:48; CHECK-NEXT: movw r0, #6168049; CHECK-NEXT: bx lr50 %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)51 ret i32 %r52}53 54define arm_aapcs_vfpcc i32 @build_v2i_v8i1_1() {55; CHECK-LABEL: build_v2i_v8i1_1:56; CHECK: @ %bb.0:57; CHECK-NEXT: movw r0, #6553558; CHECK-NEXT: bx lr59 %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>)60 ret i32 %r61}62define arm_aapcs_vfpcc i32 @build_v2i_v8i1_0() {63; CHECK-LABEL: build_v2i_v8i1_0:64; CHECK: @ %bb.0:65; CHECK-NEXT: movs r0, #066; CHECK-NEXT: bx lr67 %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>)68 ret i32 %r69}70define arm_aapcs_vfpcc i32 @build_v2i_v8i1_5() {71; CHECK-LABEL: build_v2i_v8i1_5:72; CHECK: @ %bb.0:73; CHECK-NEXT: movw r0, #5242874; CHECK-NEXT: bx lr75 %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)76 ret i32 %r77}78 79define arm_aapcs_vfpcc i32 @build_v2i_v16i1_1() {80; CHECK-LABEL: build_v2i_v16i1_1:81; CHECK: @ %bb.0:82; CHECK-NEXT: movw r0, #6553583; CHECK-NEXT: bx lr84 %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>)85 ret i32 %r86}87define arm_aapcs_vfpcc i32 @build_v2i_v16i1_0() {88; CHECK-LABEL: build_v2i_v16i1_0:89; CHECK: @ %bb.0:90; CHECK-NEXT: movs r0, #091; CHECK-NEXT: bx lr92 %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>)93 ret i32 %r94}95define arm_aapcs_vfpcc i32 @build_v2i_v16i1_5() {96; CHECK-LABEL: build_v2i_v16i1_5:97; CHECK: @ %bb.0:98; CHECK-NEXT: movw r0, #4369099; CHECK-NEXT: bx lr100 %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)101 ret i32 %r102}103 104 105 106define arm_aapcs_vfpcc <2 x i64> @build_i2v_v2i1_1() {107; CHECK-LABEL: build_i2v_v2i1_1:108; CHECK: @ %bb.0:109; CHECK-NEXT: movw r0, #65535110; CHECK-NEXT: vmov.i32 q0, #0x0111; CHECK-NEXT: vmsr p0, r0112; CHECK-NEXT: vmov.i8 q1, #0xff113; CHECK-NEXT: vpsel q0, q1, q0114; CHECK-NEXT: bx lr115 %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 65535)116 %r = select <2 x i1> %c, <2 x i64> <i64 18446744073709551615, i64 18446744073709551615>, <2 x i64> <i64 0, i64 0>117 ret <2 x i64> %r118}119define arm_aapcs_vfpcc <2 x i64> @build_i2v_v2i1_0() {120; CHECK-LABEL: build_i2v_v2i1_0:121; CHECK: @ %bb.0:122; CHECK-NEXT: movs r0, #0123; CHECK-NEXT: vmov.i32 q0, #0x0124; CHECK-NEXT: vmsr p0, r0125; CHECK-NEXT: vmov.i8 q1, #0xff126; CHECK-NEXT: vpsel q0, q1, q0127; CHECK-NEXT: bx lr128 %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 0)129 %r = select <2 x i1> %c, <2 x i64> <i64 18446744073709551615, i64 18446744073709551615>, <2 x i64> <i64 0, i64 0>130 ret <2 x i64> %r131}132define arm_aapcs_vfpcc <2 x i64> @build_i2v_v2i1_5() {133; CHECK-LABEL: build_i2v_v2i1_5:134; CHECK: @ %bb.0:135; CHECK-NEXT: movw r0, #61680136; CHECK-NEXT: vmov.i32 q0, #0x0137; CHECK-NEXT: vmsr p0, r0138; CHECK-NEXT: vmov.i8 q1, #0xff139; CHECK-NEXT: vpsel q0, q1, q0140; CHECK-NEXT: bx lr141 %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 61680)142 %r = select <2 x i1> %c, <2 x i64> <i64 18446744073709551615, i64 18446744073709551615>, <2 x i64> <i64 0, i64 0>143 ret <2 x i64> %r144}145 146define arm_aapcs_vfpcc <4 x i32> @build_i2v_v4i1_1() {147; CHECK-LABEL: build_i2v_v4i1_1:148; CHECK: @ %bb.0:149; CHECK-NEXT: movw r0, #65535150; CHECK-NEXT: vmov.i32 q0, #0x0151; CHECK-NEXT: vmsr p0, r0152; CHECK-NEXT: vmov.i8 q1, #0xff153; CHECK-NEXT: vpsel q0, q1, q0154; CHECK-NEXT: bx lr155 %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 65535)156 %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>157 ret <4 x i32> %r158}159define arm_aapcs_vfpcc <4 x i32> @build_i2v_v4i1_0() {160; CHECK-LABEL: build_i2v_v4i1_0:161; CHECK: @ %bb.0:162; CHECK-NEXT: movs r0, #0163; CHECK-NEXT: vmov.i32 q0, #0x0164; CHECK-NEXT: vmsr p0, r0165; CHECK-NEXT: vmov.i8 q1, #0xff166; CHECK-NEXT: vpsel q0, q1, q0167; CHECK-NEXT: bx lr168 %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 0)169 %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>170 ret <4 x i32> %r171}172define arm_aapcs_vfpcc <4 x i32> @build_i2v_v4i1_5() {173; CHECK-LABEL: build_i2v_v4i1_5:174; CHECK: @ %bb.0:175; CHECK-NEXT: movw r0, #61680176; CHECK-NEXT: vmov.i32 q0, #0x0177; CHECK-NEXT: vmsr p0, r0178; CHECK-NEXT: vmov.i8 q1, #0xff179; CHECK-NEXT: vpsel q0, q1, q0180; CHECK-NEXT: bx lr181 %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 61680)182 %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>183 ret <4 x i32> %r184}185 186define arm_aapcs_vfpcc <8 x i16> @build_i2v_v8i1_1() {187; CHECK-LABEL: build_i2v_v8i1_1:188; CHECK: @ %bb.0:189; CHECK-NEXT: movw r0, #65535190; CHECK-NEXT: vmov.i32 q0, #0x0191; CHECK-NEXT: vmsr p0, r0192; CHECK-NEXT: vmov.i8 q1, #0xff193; CHECK-NEXT: vpsel q0, q1, q0194; CHECK-NEXT: bx lr195 %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 65535)196 %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>197 ret <8 x i16> %r198}199define arm_aapcs_vfpcc <8 x i16> @build_i2v_v8i1_0() {200; CHECK-LABEL: build_i2v_v8i1_0:201; CHECK: @ %bb.0:202; CHECK-NEXT: movs r0, #0203; CHECK-NEXT: vmov.i32 q0, #0x0204; CHECK-NEXT: vmsr p0, r0205; CHECK-NEXT: vmov.i8 q1, #0xff206; CHECK-NEXT: vpsel q0, q1, q0207; CHECK-NEXT: bx lr208 %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 0)209 %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>210 ret <8 x i16> %r211}212define arm_aapcs_vfpcc <8 x i16> @build_i2v_v8i1_5() {213; CHECK-LABEL: build_i2v_v8i1_5:214; CHECK: @ %bb.0:215; CHECK-NEXT: movw r0, #52428216; CHECK-NEXT: vmov.i32 q0, #0x0217; CHECK-NEXT: vmsr p0, r0218; CHECK-NEXT: vmov.i8 q1, #0xff219; CHECK-NEXT: vpsel q0, q1, q0220; CHECK-NEXT: bx lr221 %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428)222 %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>223 ret <8 x i16> %r224}225 226define arm_aapcs_vfpcc <16 x i8> @build_i2v_v16i1_1() {227; CHECK-LABEL: build_i2v_v16i1_1:228; CHECK: @ %bb.0:229; CHECK-NEXT: movw r0, #65535230; CHECK-NEXT: vmov.i32 q0, #0x0231; CHECK-NEXT: vmsr p0, r0232; CHECK-NEXT: vmov.i8 q1, #0xff233; CHECK-NEXT: vpsel q0, q1, q0234; CHECK-NEXT: bx lr235 %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 65535)236 %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>237 ret <16 x i8> %r238}239define arm_aapcs_vfpcc <16 x i8> @build_i2v_v16i1_0() {240; CHECK-LABEL: build_i2v_v16i1_0:241; CHECK: @ %bb.0:242; CHECK-NEXT: movs r0, #0243; CHECK-NEXT: vmov.i32 q0, #0x0244; CHECK-NEXT: vmsr p0, r0245; CHECK-NEXT: vmov.i8 q1, #0xff246; CHECK-NEXT: vpsel q0, q1, q0247; CHECK-NEXT: bx lr248 %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 0)249 %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>250 ret <16 x i8> %r251}252define arm_aapcs_vfpcc <16 x i8> @build_i2v_v16i1_5() {253; CHECK-LABEL: build_i2v_v16i1_5:254; CHECK: @ %bb.0:255; CHECK-NEXT: movw r0, #43690256; CHECK-NEXT: vmov.i32 q0, #0x0257; CHECK-NEXT: vmsr p0, r0258; CHECK-NEXT: vmov.i8 q1, #0xff259; CHECK-NEXT: vpsel q0, q1, q0260; CHECK-NEXT: bx lr261 %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 43690)262 %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>263 ret <16 x i8> %r264}265 266 267define arm_aapcs_vfpcc i32 @build_i2v2i_v2i1_5() {268; CHECK-LABEL: build_i2v2i_v2i1_5:269; CHECK: @ %bb.0:270; CHECK-NEXT: movw r0, #61680271; CHECK-NEXT: bx lr272 %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 61680)273 %r = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %c)274 ret i32 %r275}276define arm_aapcs_vfpcc i32 @build_i2v2i_v4i1_5() {277; CHECK-LABEL: build_i2v2i_v4i1_5:278; CHECK: @ %bb.0:279; CHECK-NEXT: movw r0, #61680280; CHECK-NEXT: bx lr281 %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 61680)282 %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %c)283 ret i32 %r284}285define arm_aapcs_vfpcc i32 @build_i2v2i_v8i1_5() {286; CHECK-LABEL: build_i2v2i_v8i1_5:287; CHECK: @ %bb.0:288; CHECK-NEXT: movw r0, #52428289; CHECK-NEXT: bx lr290 %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428)291 %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %c)292 ret i32 %r293}294define arm_aapcs_vfpcc i32 @build_i2v2i_v16i1_5() {295; CHECK-LABEL: build_i2v2i_v16i1_5:296; CHECK: @ %bb.0:297; CHECK-NEXT: movw r0, #43690298; CHECK-NEXT: bx lr299 %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 43690)300 %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %c)301 ret i32 %r302}303 304 305define arm_aapcs_vfpcc <2 x i64> @build_v2i2v_v4i1_v2i1_5() {306; CHECK-LABEL: build_v2i2v_v4i1_v2i1_5:307; CHECK: @ %bb.0:308; CHECK-NEXT: movw r0, #61680309; CHECK-NEXT: vmov.i32 q0, #0x0310; CHECK-NEXT: vmsr p0, r0311; CHECK-NEXT: vmov.i8 q1, #0xff312; CHECK-NEXT: vpsel q0, q1, q0313; CHECK-NEXT: bx lr314 %b = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)315 %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %b)316 %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> zeroinitializer317 ret <2 x i64> %r318}319define arm_aapcs_vfpcc <2 x i64> @build_v2i2v_v8i1_v2i1_5() {320; CHECK-LABEL: build_v2i2v_v8i1_v2i1_5:321; CHECK: @ %bb.0:322; CHECK-NEXT: movw r0, #52428323; CHECK-NEXT: vmov.i32 q0, #0x0324; CHECK-NEXT: vmsr p0, r0325; CHECK-NEXT: vmov.i8 q1, #0xff326; CHECK-NEXT: vpsel q0, q1, q0327; CHECK-NEXT: bx lr328 %b = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)329 %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %b)330 %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> zeroinitializer331 ret <2 x i64> %r332}333define arm_aapcs_vfpcc <2 x i64> @build_v2i2v_v16i1_v2i1_5() {334; CHECK-LABEL: build_v2i2v_v16i1_v2i1_5:335; CHECK: @ %bb.0:336; CHECK-NEXT: movw r0, #43690337; CHECK-NEXT: vmov.i32 q0, #0x0338; CHECK-NEXT: vmsr p0, r0339; CHECK-NEXT: vmov.i8 q1, #0xff340; CHECK-NEXT: vpsel q0, q1, q0341; CHECK-NEXT: bx lr342 %b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)343 %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %b)344 %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> zeroinitializer345 ret <2 x i64> %r346}347 348define arm_aapcs_vfpcc <4 x i32> @build_v2i2v_v4i1_v4i1_5() {349; CHECK-LABEL: build_v2i2v_v4i1_v4i1_5:350; CHECK: @ %bb.0:351; CHECK-NEXT: movw r0, #61680352; CHECK-NEXT: vmov.i32 q0, #0x0353; CHECK-NEXT: vmsr p0, r0354; CHECK-NEXT: vmov.i8 q1, #0xff355; CHECK-NEXT: vpsel q0, q1, q0356; CHECK-NEXT: bx lr357 %b = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)358 %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %b)359 %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>360 ret <4 x i32> %r361}362define arm_aapcs_vfpcc <4 x i32> @build_v2i2v_v8i1_v4i1_5() {363; CHECK-LABEL: build_v2i2v_v8i1_v4i1_5:364; CHECK: @ %bb.0:365; CHECK-NEXT: movw r0, #52428366; CHECK-NEXT: vmov.i32 q0, #0x0367; CHECK-NEXT: vmsr p0, r0368; CHECK-NEXT: vmov.i8 q1, #0xff369; CHECK-NEXT: vpsel q0, q1, q0370; CHECK-NEXT: bx lr371 %b = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)372 %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %b)373 %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>374 ret <4 x i32> %r375}376define arm_aapcs_vfpcc <4 x i32> @build_v2i2v_v16i1_v4i1_5() {377; CHECK-LABEL: build_v2i2v_v16i1_v4i1_5:378; CHECK: @ %bb.0:379; CHECK-NEXT: movw r0, #43690380; CHECK-NEXT: vmov.i32 q0, #0x0381; CHECK-NEXT: vmsr p0, r0382; CHECK-NEXT: vmov.i8 q1, #0xff383; CHECK-NEXT: vpsel q0, q1, q0384; CHECK-NEXT: bx lr385 %b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)386 %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %b)387 %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>388 ret <4 x i32> %r389}390 391define arm_aapcs_vfpcc <8 x i16> @build_v2i2v_v4i1_v8i1_5() {392; CHECK-LABEL: build_v2i2v_v4i1_v8i1_5:393; CHECK: @ %bb.0:394; CHECK-NEXT: movw r0, #61680395; CHECK-NEXT: vmov.i32 q0, #0x0396; CHECK-NEXT: vmsr p0, r0397; CHECK-NEXT: vmov.i8 q1, #0xff398; CHECK-NEXT: vpsel q0, q1, q0399; CHECK-NEXT: bx lr400 %b = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)401 %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %b)402 %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>403 ret <8 x i16> %r404}405define arm_aapcs_vfpcc <8 x i16> @build_v2i2v_v8i1_v8i1_5() {406; CHECK-LABEL: build_v2i2v_v8i1_v8i1_5:407; CHECK: @ %bb.0:408; CHECK-NEXT: movw r0, #52428409; CHECK-NEXT: vmov.i32 q0, #0x0410; CHECK-NEXT: vmsr p0, r0411; CHECK-NEXT: vmov.i8 q1, #0xff412; CHECK-NEXT: vpsel q0, q1, q0413; CHECK-NEXT: bx lr414 %b = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)415 %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %b)416 %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>417 ret <8 x i16> %r418}419define arm_aapcs_vfpcc <8 x i16> @build_v2i2v_v16i1_v8i1_5() {420; CHECK-LABEL: build_v2i2v_v16i1_v8i1_5:421; CHECK: @ %bb.0:422; CHECK-NEXT: movw r0, #43690423; CHECK-NEXT: vmov.i32 q0, #0x0424; CHECK-NEXT: vmsr p0, r0425; CHECK-NEXT: vmov.i8 q1, #0xff426; CHECK-NEXT: vpsel q0, q1, q0427; CHECK-NEXT: bx lr428 %b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)429 %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %b)430 %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>431 ret <8 x i16> %r432}433 434define arm_aapcs_vfpcc <16 x i8> @build_v2i2v_v4i1_v16i1_5() {435; CHECK-LABEL: build_v2i2v_v4i1_v16i1_5:436; CHECK: @ %bb.0:437; CHECK-NEXT: movw r0, #61680438; CHECK-NEXT: vmov.i32 q0, #0x0439; CHECK-NEXT: vmsr p0, r0440; CHECK-NEXT: vmov.i8 q1, #0xff441; CHECK-NEXT: vpsel q0, q1, q0442; CHECK-NEXT: bx lr443 %b = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)444 %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %b)445 %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>446 ret <16 x i8> %r447}448define arm_aapcs_vfpcc <16 x i8> @build_v2i2v_v8i1_v16i1_5() {449; CHECK-LABEL: build_v2i2v_v8i1_v16i1_5:450; CHECK: @ %bb.0:451; CHECK-NEXT: movw r0, #52428452; CHECK-NEXT: vmov.i32 q0, #0x0453; CHECK-NEXT: vmsr p0, r0454; CHECK-NEXT: vmov.i8 q1, #0xff455; CHECK-NEXT: vpsel q0, q1, q0456; CHECK-NEXT: bx lr457 %b = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)458 %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %b)459 %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>460 ret <16 x i8> %r461}462define arm_aapcs_vfpcc <16 x i8> @build_v2i2v_v16i1_v16i1_5() {463; CHECK-LABEL: build_v2i2v_v16i1_v16i1_5:464; CHECK: @ %bb.0:465; CHECK-NEXT: movw r0, #43690466; CHECK-NEXT: vmov.i32 q0, #0x0467; CHECK-NEXT: vmsr p0, r0468; CHECK-NEXT: vmov.i8 q1, #0xff469; CHECK-NEXT: vpsel q0, q1, q0470; CHECK-NEXT: bx lr471 %b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)472 %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %b)473 %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>474 ret <16 x i8> %r475}476 477declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>)478declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)479declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)480declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)481 482declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32)483declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)484declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)485declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)486