381 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc void @reg(<8 x i16> %acc0, <8 x i16> %acc1, ptr nocapture %px, i16 signext %p0) {5; CHECK-LABEL: reg:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: .save {r4, r6, r7, lr}8; CHECK-NEXT: push {r4, r6, r7, lr}9; CHECK-NEXT: movw r1, #5242810; CHECK-NEXT: vmsr p0, r111; CHECK-NEXT: vpstete12; CHECK-NEXT: vaddvt.s16 r12, q113; CHECK-NEXT: vaddve.s16 r2, q114; CHECK-NEXT: vaddvt.s16 r4, q015; CHECK-NEXT: vaddve.s16 r6, q016; CHECK-NEXT: strd r2, r12, [r0, #8]17; CHECK-NEXT: strd r6, r4, [r0]18; CHECK-NEXT: pop {r4, r6, r7, pc}19entry:20 %0 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 13107)21 %1 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %0)22 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428)23 %3 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %2)24 %4 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %0)25 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %2)26 store i32 %1, ptr %px, align 427 %arrayidx1 = getelementptr inbounds i32, ptr %px, i32 128 store i32 %3, ptr %arrayidx1, align 429 %arrayidx2 = getelementptr inbounds i32, ptr %px, i32 230 store i32 %4, ptr %arrayidx2, align 431 %arrayidx3 = getelementptr inbounds i32, ptr %px, i32 332 store i32 %5, ptr %arrayidx3, align 433 ret void34}35 36 37define arm_aapcs_vfpcc void @const(<8 x i16> %acc0, <8 x i16> %acc1, ptr nocapture %px, i16 signext %p0) {38; CHECK-LABEL: const:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: .save {r4, r6, r7, lr}41; CHECK-NEXT: push {r4, r6, r7, lr}42; CHECK-NEXT: vmsr p0, r143; CHECK-NEXT: vpsttee44; CHECK-NEXT: vaddvt.s16 r12, q145; CHECK-NEXT: vaddvt.s16 r2, q046; CHECK-NEXT: vaddve.s16 r4, q147; CHECK-NEXT: vaddve.s16 r6, q048; CHECK-NEXT: stm.w r0, {r2, r6, r12}49; CHECK-NEXT: str r4, [r0, #12]50; CHECK-NEXT: pop {r4, r6, r7, pc}51entry:52 %0 = zext i16 %p0 to i3253 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)54 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %1)55 %3 = xor i16 %p0, -156 %4 = zext i16 %3 to i3257 %5 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)58 %6 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %5)59 %7 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %1)60 %8 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %5)61 store i32 %2, ptr %px, align 462 %arrayidx1 = getelementptr inbounds i32, ptr %px, i32 163 store i32 %6, ptr %arrayidx1, align 464 %arrayidx2 = getelementptr inbounds i32, ptr %px, i32 265 store i32 %7, ptr %arrayidx2, align 466 %arrayidx3 = getelementptr inbounds i32, ptr %px, i32 367 store i32 %8, ptr %arrayidx3, align 468 ret void69}70 71 72 73define arm_aapcs_vfpcc <4 x i32> @xorvpnot_i32(<4 x i32> %acc0, i16 signext %p0) {74; CHECK-LABEL: xorvpnot_i32:75; CHECK: @ %bb.0: @ %entry76; CHECK-NEXT: vmsr p0, r077; CHECK-NEXT: vmov.i32 q1, #0x078; CHECK-NEXT: vpnot79; CHECK-NEXT: vpsel q0, q0, q180; CHECK-NEXT: bx lr81entry:82 %l3 = xor i16 %p0, -183 %l4 = zext i16 %l3 to i3284 %l5 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l4)85 %l6 = select <4 x i1> %l5, <4 x i32> %acc0, <4 x i32> zeroinitializer86 ret <4 x i32> %l687}88 89define arm_aapcs_vfpcc <8 x i16> @xorvpnot_i16(<8 x i16> %acc0, i16 signext %p0) {90; CHECK-LABEL: xorvpnot_i16:91; CHECK: @ %bb.0: @ %entry92; CHECK-NEXT: vmsr p0, r093; CHECK-NEXT: vmov.i32 q1, #0x094; CHECK-NEXT: vpnot95; CHECK-NEXT: vpsel q0, q0, q196; CHECK-NEXT: bx lr97entry:98 %l3 = xor i16 %p0, -199 %l4 = zext i16 %l3 to i32100 %l5 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %l4)101 %l6 = select <8 x i1> %l5, <8 x i16> %acc0, <8 x i16> zeroinitializer102 ret <8 x i16> %l6103}104 105define arm_aapcs_vfpcc <16 x i8> @xorvpnot_i8(<16 x i8> %acc0, i16 signext %p0) {106; CHECK-LABEL: xorvpnot_i8:107; CHECK: @ %bb.0: @ %entry108; CHECK-NEXT: vmsr p0, r0109; CHECK-NEXT: vmov.i32 q1, #0x0110; CHECK-NEXT: vpnot111; CHECK-NEXT: vpsel q0, q0, q1112; CHECK-NEXT: bx lr113entry:114 %l3 = xor i16 %p0, -1115 %l4 = zext i16 %l3 to i32116 %l5 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %l4)117 %l6 = select <16 x i1> %l5, <16 x i8> %acc0, <16 x i8> zeroinitializer118 ret <16 x i8> %l6119}120 121define arm_aapcs_vfpcc <16 x i8> @xorvpnot_i8_2(<16 x i8> %acc0, i32 %p0) {122; CHECK-LABEL: xorvpnot_i8_2:123; CHECK: @ %bb.0: @ %entry124; CHECK-NEXT: vmsr p0, r0125; CHECK-NEXT: vmov.i32 q1, #0x0126; CHECK-NEXT: vpnot127; CHECK-NEXT: vpsel q0, q0, q1128; CHECK-NEXT: bx lr129entry:130 %l3 = xor i32 %p0, 65535131 %l5 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %l3)132 %l6 = select <16 x i1> %l5, <16 x i8> %acc0, <16 x i8> zeroinitializer133 ret <16 x i8> %l6134}135 136 137 138define arm_aapcs_vfpcc i32 @const_mask_1(<4 x i32> %0, <4 x i32> %1, i32 %2) {139; CHECK-LABEL: const_mask_1:140; CHECK: @ %bb.0:141; CHECK-NEXT: movs r1, #1142; CHECK-NEXT: vmsr p0, r1143; CHECK-NEXT: vpsttee144; CHECK-NEXT: vaddvat.s32 r0, q0145; CHECK-NEXT: vaddvat.s32 r0, q1146; CHECK-NEXT: vaddvae.s32 r0, q0147; CHECK-NEXT: vaddvae.s32 r0, q1148; CHECK-NEXT: bx lr149 %4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1)150 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)151 %6 = add i32 %5, %2152 %7 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)153 %8 = add i32 %6, %7154 %9 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 65534)155 %10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %9)156 %11 = add i32 %8, %10157 %12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %9)158 %13 = add i32 %11, %12159 ret i32 %13160}161 162define arm_aapcs_vfpcc i32 @const_mask_not1(<4 x i32> %0, <4 x i32> %1, i32 %2) {163; CHECK-LABEL: const_mask_not1:164; CHECK: @ %bb.0:165; CHECK-NEXT: movs r1, #1166; CHECK-NEXT: vmsr p0, r1167; CHECK-NEXT: movw r1, #65533168; CHECK-NEXT: vpstt169; CHECK-NEXT: vaddvat.s32 r0, q0170; CHECK-NEXT: vaddvat.s32 r0, q1171; CHECK-NEXT: vmsr p0, r1172; CHECK-NEXT: vpstt173; CHECK-NEXT: vaddvat.s32 r0, q0174; CHECK-NEXT: vaddvat.s32 r0, q1175; CHECK-NEXT: bx lr176 %4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1)177 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)178 %6 = add i32 %5, %2179 %7 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)180 %8 = add i32 %6, %7181 %9 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 65533)182 %10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %9)183 %11 = add i32 %8, %10184 %12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %9)185 %13 = add i32 %11, %12186 ret i32 %13187}188 189define arm_aapcs_vfpcc i32 @const_mask_1234(<4 x i32> %0, <4 x i32> %1, i32 %2) {190; CHECK-LABEL: const_mask_1234:191; CHECK: @ %bb.0:192; CHECK-NEXT: movw r1, #1234193; CHECK-NEXT: vmsr p0, r1194; CHECK-NEXT: vpsttee195; CHECK-NEXT: vaddvat.s32 r0, q0196; CHECK-NEXT: vaddvat.s32 r0, q1197; CHECK-NEXT: vaddvae.s32 r0, q0198; CHECK-NEXT: vaddvae.s32 r0, q1199; CHECK-NEXT: bx lr200 %4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)201 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)202 %6 = add i32 %5, %2203 %7 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)204 %8 = add i32 %6, %7205 %9 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)206 %10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %9)207 %11 = add i32 %8, %10208 %12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %9)209 %13 = add i32 %11, %12210 ret i32 %13211}212 213define arm_aapcs_vfpcc i32 @const_mask_abab(<4 x i32> %0, <4 x i32> %1, i32 %2) {214; CHECK-LABEL: const_mask_abab:215; CHECK: @ %bb.0:216; CHECK-NEXT: movw r1, #1234217; CHECK-NEXT: vmsr p0, r1218; CHECK-NEXT: vpstete219; CHECK-NEXT: vaddvat.s32 r0, q0220; CHECK-NEXT: vaddvae.s32 r0, q1221; CHECK-NEXT: vaddvat.s32 r0, q1222; CHECK-NEXT: vaddvae.s32 r0, q0223; CHECK-NEXT: bx lr224 %4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)225 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)226 %6 = add i32 %5, %2227 %7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)228 %8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %7)229 %9 = add i32 %6, %8230 %10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)231 %11 = add i32 %9, %10232 %12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %7)233 %13 = add i32 %11, %12234 ret i32 %13235}236 237define arm_aapcs_vfpcc i32 @const_mask_abbreakab(<4 x i32> %0, <4 x i32> %1, i32 %2) {238; CHECK-LABEL: const_mask_abbreakab:239; CHECK: @ %bb.0:240; CHECK-NEXT: movw r1, #1234241; CHECK-NEXT: vmsr p0, r1242; CHECK-NEXT: vpste243; CHECK-NEXT: vaddvat.s32 r0, q0244; CHECK-NEXT: vaddvae.s32 r0, q1245; CHECK-NEXT: vpnot246; CHECK-NEXT: vadd.i32 q1, q0, r0247; CHECK-NEXT: vpste248; CHECK-NEXT: vaddvat.s32 r0, q1249; CHECK-NEXT: vaddvae.s32 r0, q0250; CHECK-NEXT: bx lr251 %4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)252 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)253 %6 = add i32 %5, %2254 %7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)255 %8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %7)256 %9 = add i32 %6, %8257 %si = insertelement <4 x i32> undef, i32 %9, i32 0258 %s = shufflevector <4 x i32> %si, <4 x i32> undef, <4 x i32> zeroinitializer259 %nadd = add <4 x i32> %0, %s260 %10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %nadd, i32 0, <4 x i1> %4)261 %11 = add i32 %9, %10262 %12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %7)263 %13 = add i32 %11, %12264 ret i32 %13265}266 267define arm_aapcs_vfpcc i32 @const_mask_break(<4 x i32> %0, <4 x i32> %1, i32 %2) {268; CHECK-LABEL: const_mask_break:269; CHECK: @ %bb.0:270; CHECK-NEXT: movw r1, #1234271; CHECK-NEXT: vmsr p0, r1272; CHECK-NEXT: vpstt273; CHECK-NEXT: vaddvat.s32 r0, q0274; CHECK-NEXT: vaddvat.s32 r0, q1275; CHECK-NEXT: vpnot276; CHECK-NEXT: vadd.i32 q1, q0, r0277; CHECK-NEXT: vpstt278; CHECK-NEXT: vaddvat.s32 r0, q1279; CHECK-NEXT: vaddvat.s32 r0, q0280; CHECK-NEXT: bx lr281 %4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)282 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)283 %6 = add i32 %5, %2284 %7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)285 %8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)286 %9 = add i32 %6, %8287 %si = insertelement <4 x i32> undef, i32 %9, i32 0288 %s = shufflevector <4 x i32> %si, <4 x i32> undef, <4 x i32> zeroinitializer289 %nadd = add <4 x i32> %0, %s290 %10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %nadd, i32 0, <4 x i1> %7)291 %11 = add i32 %9, %10292 %12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %7)293 %13 = add i32 %11, %12294 ret i32 %13295}296 297define arm_aapcs_vfpcc i32 @const_mask_threepred(<4 x i32> %0, <4 x i32> %1, i32 %2) {298; CHECK-LABEL: const_mask_threepred:299; CHECK: @ %bb.0:300; CHECK-NEXT: movw r1, #1234301; CHECK-NEXT: vmsr p0, r1302; CHECK-NEXT: movw r1, #64300303; CHECK-NEXT: vpstt304; CHECK-NEXT: vaddvat.s32 r0, q0305; CHECK-NEXT: vaddvat.s32 r0, q1306; CHECK-NEXT: vmsr p0, r1307; CHECK-NEXT: movw r1, #64301308; CHECK-NEXT: vpst309; CHECK-NEXT: vaddvat.s32 r0, q1310; CHECK-NEXT: vmsr p0, r1311; CHECK-NEXT: vpstt312; CHECK-NEXT: vaddvat.s32 r0, q1313; CHECK-NEXT: vaddvat.s32 r0, q0314; CHECK-NEXT: bx lr315 %4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)316 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)317 %6 = add i32 %5, %2318 %7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)319 %8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)320 %9 = add i32 %6, %8321 %n7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64300)322 %n8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %n7)323 %n9 = add i32 %9, %n8324 %10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %7)325 %11 = add i32 %n9, %10326 %12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %7)327 %13 = add i32 %11, %12328 ret i32 %13329}330 331define arm_aapcs_vfpcc i32 @const_mask_threepredabab(<4 x i32> %0, <4 x i32> %1, i32 %2) {332; CHECK-LABEL: const_mask_threepredabab:333; CHECK: @ %bb.0:334; CHECK-NEXT: .pad #4335; CHECK-NEXT: sub sp, #4336; CHECK-NEXT: movw r1, #1234337; CHECK-NEXT: vmsr p0, r1338; CHECK-NEXT: vstr p0, [sp] @ 4-byte Spill339; CHECK-NEXT: vpst340; CHECK-NEXT: vaddvat.s32 r0, q0341; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload342; CHECK-NEXT: vpnot343; CHECK-NEXT: vpst344; CHECK-NEXT: vaddvat.s32 r0, q1345; CHECK-NEXT: vpt.s32 gt, q1, q0346; CHECK-NEXT: vaddvat.s32 r0, q1347; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload348; CHECK-NEXT: vpste349; CHECK-NEXT: vaddvat.s32 r0, q1350; CHECK-NEXT: vaddvae.s32 r0, q0351; CHECK-NEXT: add sp, #4352; CHECK-NEXT: bx lr353 %4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)354 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)355 %6 = add i32 %5, %2356 %7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)357 %8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %7)358 %9 = add i32 %6, %8359 %n7 = icmp slt <4 x i32> %0, %1360 %n8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %n7)361 %n9 = add i32 %9, %n8362 %10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)363 %11 = add i32 %n9, %10364 %12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %7)365 %13 = add i32 %11, %12366 ret i32 %13367}368 369 370declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)371declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)372declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)373 374declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)375declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)376declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)377 378declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)379declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>)380declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>)381