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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - -verify-machineinstrs | FileCheck %s3 4--- |5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"6 target triple = "thumbv8.1m.main-none-unknown-eabi"7 8 define arm_aapcs_vfpcc void @reg(<8 x i16> %acc0, <8 x i16> %acc1, ptr nocapture %px, i16 signext %p0) #0 {9 entry:10 %0 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 13107)11 %1 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %0)12 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428)13 %3 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %2)14 %4 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %0)15 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %2)16 store i32 %1, ptr %px, align 417 %arrayidx1 = getelementptr inbounds i32, ptr %px, i32 118 store i32 %3, ptr %arrayidx1, align 419 %arrayidx2 = getelementptr inbounds i32, ptr %px, i32 220 store i32 %4, ptr %arrayidx2, align 421 %arrayidx3 = getelementptr inbounds i32, ptr %px, i32 322 store i32 %5, ptr %arrayidx3, align 423 ret void24 }25 26 declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #127 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #128 declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #129 30 attributes #0 = { "target-features"="+mve" }31 32...33---34name: reg35alignment: 236tracksRegLiveness: true37registers:38 - { id: 0, class: mqpr, preferred-register: '' }39 - { id: 1, class: mqpr, preferred-register: '' }40 - { id: 2, class: gpr, preferred-register: '' }41 - { id: 3, class: gpr, preferred-register: '' }42 - { id: 4, class: rgpr, preferred-register: '' }43 - { id: 5, class: vccr, preferred-register: '' }44 - { id: 6, class: tgpreven, preferred-register: '' }45 - { id: 7, class: rgpr, preferred-register: '' }46 - { id: 8, class: vccr, preferred-register: '' }47 - { id: 9, class: tgpreven, preferred-register: '' }48 - { id: 10, class: tgpreven, preferred-register: '' }49 - { id: 11, class: tgpreven, preferred-register: '' }50liveins:51 - { reg: '$q0', virtual-reg: '%0' }52 - { reg: '$q1', virtual-reg: '%1' }53 - { reg: '$r0', virtual-reg: '%2' }54body: |55 bb.0.entry:56 liveins: $q0, $q1, $r057 58 ; CHECK-LABEL: name: reg59 ; CHECK: liveins: $q0, $q1, $r060 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r062 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:mqpr = COPY $q163 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:mqpr = COPY $q064 ; CHECK-NEXT: [[t2MOVi16_:%[0-9]+]]:rgpr = t2MOVi16 52428, 14 /* CC::al */, $noreg65 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vccr = COPY [[t2MOVi16_]]66 ; CHECK-NEXT: [[MVE_VADDVs16no_acc:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY2]], 1, [[COPY3]], $noreg67 ; CHECK-NEXT: [[t2MOVi16_1:%[0-9]+]]:rgpr = t2MOVi16 13107, 14 /* CC::al */, $noreg68 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vccr = COPY [[t2MOVi16_1]]69 ; CHECK-NEXT: [[MVE_VADDVs16no_acc1:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY2]], 1, [[COPY4]], $noreg70 ; CHECK-NEXT: [[MVE_VADDVs16no_acc2:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY1]], 1, [[COPY4]], $noreg71 ; CHECK-NEXT: [[MVE_VADDVs16no_acc3:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY1]], 1, [[COPY3]], $noreg72 ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.px)73 ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc]], [[COPY]], 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx1)74 ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc2]], [[COPY]], 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx2)75 ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc3]], [[COPY]], 12, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx3)76 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg77 %2:gpr = COPY $r078 %1:mqpr = COPY $q179 %0:mqpr = COPY $q080 %4:rgpr = t2MOVi16 52428, 14 /* CC::al */, $noreg81 %5:vccr = COPY %482 %6:tgpreven = MVE_VADDVs16no_acc %0, 1, %5, $noreg83 t2STRi12 killed %6, %2, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx1)84 %7:rgpr = t2MOVi16 13107, 14 /* CC::al */, $noreg85 %8:vccr = COPY %786 %9:tgpreven = MVE_VADDVs16no_acc %0, 1, %8, $noreg87 t2STRi12 killed %9, %2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.px)88 %10:tgpreven = MVE_VADDVs16no_acc %1, 1, %8, $noreg89 t2STRi12 killed %10, %2, 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx2)90 %11:tgpreven = MVE_VADDVs16no_acc %1, 1, %5, $noreg91 t2STRi12 killed %11, %2, 12, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx3)92 tBX_RET 14 /* CC::al */, $noreg93 94...95