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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVE3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVEFP4 5define arm_aapcs_vfpcc <4 x i32> @sext_v4i1_v4i32(<4 x i32> %src) {6; CHECK-LABEL: sext_v4i1_v4i32:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vmov.i32 q1, #0x09; CHECK-NEXT: vmov.i8 q2, #0xff10; CHECK-NEXT: vcmp.s32 gt, q0, zr11; CHECK-NEXT: vpsel q0, q2, q112; CHECK-NEXT: bx lr13entry:14 %c = icmp sgt <4 x i32> %src, zeroinitializer15 %0 = sext <4 x i1> %c to <4 x i32>16 ret <4 x i32> %017}18 19define arm_aapcs_vfpcc <4 x i32> @sext_v4i1_v4f32(<4 x float> %src1, <4 x float> %src2) {20; CHECK-MVE-LABEL: sext_v4i1_v4f32:21; CHECK-MVE: @ %bb.0: @ %entry22; CHECK-MVE-NEXT: vcmp.f32 s2, s623; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr24; CHECK-MVE-NEXT: vcmp.f32 s0, s425; CHECK-MVE-NEXT: csetm r0, ne26; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr27; CHECK-MVE-NEXT: vcmp.f32 s3, s728; CHECK-MVE-NEXT: csetm r1, ne29; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr30; CHECK-MVE-NEXT: vcmp.f32 s1, s531; CHECK-MVE-NEXT: vmov q2[2], q2[0], r1, r032; CHECK-MVE-NEXT: csetm r0, ne33; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr34; CHECK-MVE-NEXT: csetm r1, ne35; CHECK-MVE-NEXT: vmov q2[3], q2[1], r1, r036; CHECK-MVE-NEXT: vmov q0, q237; CHECK-MVE-NEXT: bx lr38;39; CHECK-MVEFP-LABEL: sext_v4i1_v4f32:40; CHECK-MVEFP: @ %bb.0: @ %entry41; CHECK-MVEFP-NEXT: vmov.i32 q2, #0x042; CHECK-MVEFP-NEXT: vmov.i8 q3, #0xff43; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, q144; CHECK-MVEFP-NEXT: vpsel q0, q3, q245; CHECK-MVEFP-NEXT: bx lr46entry:47 %c = fcmp une <4 x float> %src1, %src248 %0 = sext <4 x i1> %c to <4 x i32>49 ret <4 x i32> %050}51 52define arm_aapcs_vfpcc <8 x i16> @sext_v8i1_v8i16(<8 x i16> %src) {53; CHECK-LABEL: sext_v8i1_v8i16:54; CHECK: @ %bb.0: @ %entry55; CHECK-NEXT: vmov.i16 q1, #0x056; CHECK-NEXT: vmov.i8 q2, #0xff57; CHECK-NEXT: vcmp.s16 gt, q0, zr58; CHECK-NEXT: vpsel q0, q2, q159; CHECK-NEXT: bx lr60entry:61 %c = icmp sgt <8 x i16> %src, zeroinitializer62 %0 = sext <8 x i1> %c to <8 x i16>63 ret <8 x i16> %064}65 66define arm_aapcs_vfpcc <8 x i16> @sext_v8i1_v8f16(<8 x half> %src1, <8 x half> %src2) {67; CHECK-MVE-LABEL: sext_v8i1_v8f16:68; CHECK-MVE: @ %bb.0: @ %entry69; CHECK-MVE-NEXT: .save {r4, lr}70; CHECK-MVE-NEXT: push {r4, lr}71; CHECK-MVE-NEXT: vcmp.f16 s3, s772; CHECK-MVE-NEXT: vmovx.f16 s8, s673; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr74; CHECK-MVE-NEXT: vmovx.f16 s10, s275; CHECK-MVE-NEXT: vcmp.f16 s10, s876; CHECK-MVE-NEXT: vmovx.f16 s8, s577; CHECK-MVE-NEXT: vmovx.f16 s10, s178; CHECK-MVE-NEXT: csetm r12, ne79; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr80; CHECK-MVE-NEXT: vcmp.f16 s10, s881; CHECK-MVE-NEXT: csetm lr, ne82; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr83; CHECK-MVE-NEXT: vcmp.f16 s2, s684; CHECK-MVE-NEXT: vmovx.f16 s2, s485; CHECK-MVE-NEXT: vmovx.f16 s6, s086; CHECK-MVE-NEXT: csetm r2, ne87; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr88; CHECK-MVE-NEXT: vcmp.f16 s6, s289; CHECK-MVE-NEXT: vmovx.f16 s2, s390; CHECK-MVE-NEXT: csetm r3, ne91; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr92; CHECK-MVE-NEXT: vcmp.f16 s1, s593; CHECK-MVE-NEXT: csetm r0, ne94; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr95; CHECK-MVE-NEXT: vcmp.f16 s0, s496; CHECK-MVE-NEXT: vmovx.f16 s0, s797; CHECK-MVE-NEXT: csetm r1, ne98; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr99; CHECK-MVE-NEXT: vcmp.f16 s2, s0100; CHECK-MVE-NEXT: csetm r4, ne101; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr102; CHECK-MVE-NEXT: vmov.16 q0[0], r4103; CHECK-MVE-NEXT: vmov.16 q0[1], r0104; CHECK-MVE-NEXT: vmov.16 q0[2], r1105; CHECK-MVE-NEXT: vmov.16 q0[3], r2106; CHECK-MVE-NEXT: vmov.16 q0[4], r3107; CHECK-MVE-NEXT: vmov.16 q0[5], lr108; CHECK-MVE-NEXT: vmov.16 q0[6], r12109; CHECK-MVE-NEXT: csetm r0, ne110; CHECK-MVE-NEXT: vmov.16 q0[7], r0111; CHECK-MVE-NEXT: pop {r4, pc}112;113; CHECK-MVEFP-LABEL: sext_v8i1_v8f16:114; CHECK-MVEFP: @ %bb.0: @ %entry115; CHECK-MVEFP-NEXT: vmov.i16 q2, #0x0116; CHECK-MVEFP-NEXT: vmov.i8 q3, #0xff117; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, q1118; CHECK-MVEFP-NEXT: vpsel q0, q3, q2119; CHECK-MVEFP-NEXT: bx lr120entry:121 %c = fcmp une <8 x half> %src1, %src2122 %0 = sext <8 x i1> %c to <8 x i16>123 ret <8 x i16> %0124}125 126define arm_aapcs_vfpcc <16 x i8> @sext_v16i1_v16i8(<16 x i8> %src) {127; CHECK-LABEL: sext_v16i1_v16i8:128; CHECK: @ %bb.0: @ %entry129; CHECK-NEXT: vmov.i8 q1, #0x0130; CHECK-NEXT: vmov.i8 q2, #0xff131; CHECK-NEXT: vcmp.s8 gt, q0, zr132; CHECK-NEXT: vpsel q0, q2, q1133; CHECK-NEXT: bx lr134entry:135 %c = icmp sgt <16 x i8> %src, zeroinitializer136 %0 = sext <16 x i1> %c to <16 x i8>137 ret <16 x i8> %0138}139 140define arm_aapcs_vfpcc <2 x i64> @sext_v2i1_v2i64(<2 x i64> %src) {141; CHECK-LABEL: sext_v2i1_v2i64:142; CHECK: @ %bb.0: @ %entry143; CHECK-NEXT: vmov r0, r1, d1144; CHECK-NEXT: mov.w r12, #0145; CHECK-NEXT: vmov r2, r3, d0146; CHECK-NEXT: rsbs r0, r0, #0147; CHECK-NEXT: sbcs.w r0, r12, r1148; CHECK-NEXT: csetm r0, lt149; CHECK-NEXT: rsbs r1, r2, #0150; CHECK-NEXT: sbcs.w r1, r12, r3151; CHECK-NEXT: csetm r1, lt152; CHECK-NEXT: vmov q0[2], q0[0], r1, r0153; CHECK-NEXT: vmov q0[3], q0[1], r1, r0154; CHECK-NEXT: bx lr155entry:156 %c = icmp sgt <2 x i64> %src, zeroinitializer157 %0 = sext <2 x i1> %c to <2 x i64>158 ret <2 x i64> %0159}160 161define arm_aapcs_vfpcc <2 x i64> @sext_v2i1_v2f64(<2 x double> %src) {162; CHECK-MVE-LABEL: sext_v2i1_v2f64:163; CHECK-MVE: @ %bb.0: @ %entry164; CHECK-MVE-NEXT: .save {r4, r5, r6, lr}165; CHECK-MVE-NEXT: push {r4, r5, r6, lr}166; CHECK-MVE-NEXT: .vsave {d8, d9}167; CHECK-MVE-NEXT: vpush {d8, d9}168; CHECK-MVE-NEXT: vmov q4, q0169; CHECK-MVE-NEXT: vldr d0, .LCPI6_0170; CHECK-MVE-NEXT: vmov r0, r1, d9171; CHECK-MVE-NEXT: vmov r4, r5, d0172; CHECK-MVE-NEXT: mov r2, r4173; CHECK-MVE-NEXT: mov r3, r5174; CHECK-MVE-NEXT: bl __aeabi_dcmpeq175; CHECK-MVE-NEXT: vmov r2, r1, d8176; CHECK-MVE-NEXT: cmp r0, #0177; CHECK-MVE-NEXT: mov r3, r5178; CHECK-MVE-NEXT: csetm r6, eq179; CHECK-MVE-NEXT: mov r0, r2180; CHECK-MVE-NEXT: mov r2, r4181; CHECK-MVE-NEXT: bl __aeabi_dcmpeq182; CHECK-MVE-NEXT: cmp r0, #0183; CHECK-MVE-NEXT: csetm r0, eq184; CHECK-MVE-NEXT: vmov q0[2], q0[0], r0, r6185; CHECK-MVE-NEXT: vmov q0[3], q0[1], r0, r6186; CHECK-MVE-NEXT: vpop {d8, d9}187; CHECK-MVE-NEXT: pop {r4, r5, r6, pc}188; CHECK-MVE-NEXT: .p2align 3189; CHECK-MVE-NEXT: @ %bb.1:190; CHECK-MVE-NEXT: .LCPI6_0:191; CHECK-MVE-NEXT: .long 0 @ double 0192; CHECK-MVE-NEXT: .long 0193;194; CHECK-MVEFP-LABEL: sext_v2i1_v2f64:195; CHECK-MVEFP: @ %bb.0: @ %entry196; CHECK-MVEFP-NEXT: .save {r4, r5, r6, lr}197; CHECK-MVEFP-NEXT: push {r4, r5, r6, lr}198; CHECK-MVEFP-NEXT: .vsave {d8, d9}199; CHECK-MVEFP-NEXT: vpush {d8, d9}200; CHECK-MVEFP-NEXT: vmov q4, q0201; CHECK-MVEFP-NEXT: vldr d0, .LCPI6_0202; CHECK-MVEFP-NEXT: vmov r0, r1, d8203; CHECK-MVEFP-NEXT: vmov r4, r5, d0204; CHECK-MVEFP-NEXT: mov r2, r4205; CHECK-MVEFP-NEXT: mov r3, r5206; CHECK-MVEFP-NEXT: bl __aeabi_dcmpeq207; CHECK-MVEFP-NEXT: mov r6, r0208; CHECK-MVEFP-NEXT: vmov r0, r1, d9209; CHECK-MVEFP-NEXT: mov r2, r4210; CHECK-MVEFP-NEXT: mov r3, r5211; CHECK-MVEFP-NEXT: bl __aeabi_dcmpeq212; CHECK-MVEFP-NEXT: cmp r0, #0213; CHECK-MVEFP-NEXT: csetm r0, eq214; CHECK-MVEFP-NEXT: cmp r6, #0215; CHECK-MVEFP-NEXT: csetm r1, eq216; CHECK-MVEFP-NEXT: vmov q0[2], q0[0], r1, r0217; CHECK-MVEFP-NEXT: vmov q0[3], q0[1], r1, r0218; CHECK-MVEFP-NEXT: vpop {d8, d9}219; CHECK-MVEFP-NEXT: pop {r4, r5, r6, pc}220; CHECK-MVEFP-NEXT: .p2align 3221; CHECK-MVEFP-NEXT: @ %bb.1:222; CHECK-MVEFP-NEXT: .LCPI6_0:223; CHECK-MVEFP-NEXT: .long 0 @ double 0224; CHECK-MVEFP-NEXT: .long 0225entry:226 %c = fcmp une <2 x double> %src, zeroinitializer227 %0 = sext <2 x i1> %c to <2 x i64>228 ret <2 x i64> %0229}230 231 232define arm_aapcs_vfpcc <4 x i32> @zext_v4i1_v4i32(<4 x i32> %src) {233; CHECK-LABEL: zext_v4i1_v4i32:234; CHECK: @ %bb.0: @ %entry235; CHECK-NEXT: vmov.i32 q1, #0x0236; CHECK-NEXT: vmov.i32 q2, #0x1237; CHECK-NEXT: vcmp.s32 gt, q0, zr238; CHECK-NEXT: vpsel q0, q2, q1239; CHECK-NEXT: bx lr240entry:241 %c = icmp sgt <4 x i32> %src, zeroinitializer242 %0 = zext <4 x i1> %c to <4 x i32>243 ret <4 x i32> %0244}245 246define arm_aapcs_vfpcc <4 x i32> @zext_v4i1_v4f32(<4 x float> %src1, <4 x float> %src2) {247; CHECK-MVE-LABEL: zext_v4i1_v4f32:248; CHECK-MVE: @ %bb.0: @ %entry249; CHECK-MVE-NEXT: vcmp.f32 s2, s6250; CHECK-MVE-NEXT: vmov.i32 q2, #0x1251; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr252; CHECK-MVE-NEXT: vcmp.f32 s0, s4253; CHECK-MVE-NEXT: csetm r0, ne254; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr255; CHECK-MVE-NEXT: vcmp.f32 s3, s7256; CHECK-MVE-NEXT: csetm r1, ne257; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr258; CHECK-MVE-NEXT: vcmp.f32 s1, s5259; CHECK-MVE-NEXT: vmov q3[2], q3[0], r1, r0260; CHECK-MVE-NEXT: csetm r0, ne261; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr262; CHECK-MVE-NEXT: csetm r1, ne263; CHECK-MVE-NEXT: vmov q3[3], q3[1], r1, r0264; CHECK-MVE-NEXT: vand q0, q3, q2265; CHECK-MVE-NEXT: bx lr266;267; CHECK-MVEFP-LABEL: zext_v4i1_v4f32:268; CHECK-MVEFP: @ %bb.0: @ %entry269; CHECK-MVEFP-NEXT: vmov.i32 q2, #0x0270; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x1271; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, q1272; CHECK-MVEFP-NEXT: vpsel q0, q3, q2273; CHECK-MVEFP-NEXT: bx lr274entry:275 %c = fcmp une <4 x float> %src1, %src2276 %0 = zext <4 x i1> %c to <4 x i32>277 ret <4 x i32> %0278}279 280define arm_aapcs_vfpcc <8 x i16> @zext_v8i1_v8i16(<8 x i16> %src) {281; CHECK-LABEL: zext_v8i1_v8i16:282; CHECK: @ %bb.0: @ %entry283; CHECK-NEXT: vmov.i16 q1, #0x0284; CHECK-NEXT: vmov.i16 q2, #0x1285; CHECK-NEXT: vcmp.s16 gt, q0, zr286; CHECK-NEXT: vpsel q0, q2, q1287; CHECK-NEXT: bx lr288entry:289 %c = icmp sgt <8 x i16> %src, zeroinitializer290 %0 = zext <8 x i1> %c to <8 x i16>291 ret <8 x i16> %0292}293 294define arm_aapcs_vfpcc <8 x i16> @zext_v8i1_v8f16(<8 x half> %src1, <8 x half> %src2) {295; CHECK-MVE-LABEL: zext_v8i1_v8f16:296; CHECK-MVE: @ %bb.0: @ %entry297; CHECK-MVE-NEXT: .save {r4, lr}298; CHECK-MVE-NEXT: push {r4, lr}299; CHECK-MVE-NEXT: vcmp.f16 s3, s7300; CHECK-MVE-NEXT: vmovx.f16 s8, s6301; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr302; CHECK-MVE-NEXT: vmovx.f16 s10, s2303; CHECK-MVE-NEXT: vcmp.f16 s10, s8304; CHECK-MVE-NEXT: csetm r12, ne305; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr306; CHECK-MVE-NEXT: vcmp.f16 s2, s6307; CHECK-MVE-NEXT: vmovx.f16 s2, s5308; CHECK-MVE-NEXT: vmovx.f16 s6, s1309; CHECK-MVE-NEXT: csetm lr, ne310; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr311; CHECK-MVE-NEXT: vcmp.f16 s6, s2312; CHECK-MVE-NEXT: vmovx.f16 s2, s4313; CHECK-MVE-NEXT: vmovx.f16 s6, s0314; CHECK-MVE-NEXT: csetm r2, ne315; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr316; CHECK-MVE-NEXT: vcmp.f16 s1, s5317; CHECK-MVE-NEXT: csetm r3, ne318; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr319; CHECK-MVE-NEXT: vcmp.f16 s6, s2320; CHECK-MVE-NEXT: vmovx.f16 s2, s3321; CHECK-MVE-NEXT: csetm r0, ne322; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr323; CHECK-MVE-NEXT: vcmp.f16 s0, s4324; CHECK-MVE-NEXT: vmovx.f16 s0, s7325; CHECK-MVE-NEXT: csetm r1, ne326; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr327; CHECK-MVE-NEXT: vcmp.f16 s2, s0328; CHECK-MVE-NEXT: vmov.i16 q0, #0x1329; CHECK-MVE-NEXT: csetm r4, ne330; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr331; CHECK-MVE-NEXT: vmov.16 q1[0], r4332; CHECK-MVE-NEXT: vmov.16 q1[1], r1333; CHECK-MVE-NEXT: vmov.16 q1[2], r0334; CHECK-MVE-NEXT: vmov.16 q1[3], r3335; CHECK-MVE-NEXT: vmov.16 q1[4], r2336; CHECK-MVE-NEXT: vmov.16 q1[5], lr337; CHECK-MVE-NEXT: vmov.16 q1[6], r12338; CHECK-MVE-NEXT: csetm r0, ne339; CHECK-MVE-NEXT: vmov.16 q1[7], r0340; CHECK-MVE-NEXT: vand q0, q1, q0341; CHECK-MVE-NEXT: pop {r4, pc}342;343; CHECK-MVEFP-LABEL: zext_v8i1_v8f16:344; CHECK-MVEFP: @ %bb.0: @ %entry345; CHECK-MVEFP-NEXT: vmov.i16 q2, #0x0346; CHECK-MVEFP-NEXT: vmov.i16 q3, #0x1347; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, q1348; CHECK-MVEFP-NEXT: vpsel q0, q3, q2349; CHECK-MVEFP-NEXT: bx lr350entry:351 %c = fcmp une <8 x half> %src1, %src2352 %0 = zext <8 x i1> %c to <8 x i16>353 ret <8 x i16> %0354}355 356define arm_aapcs_vfpcc <16 x i8> @zext_v16i1_v16i8(<16 x i8> %src) {357; CHECK-LABEL: zext_v16i1_v16i8:358; CHECK: @ %bb.0: @ %entry359; CHECK-NEXT: vmov.i8 q1, #0x0360; CHECK-NEXT: vmov.i8 q2, #0x1361; CHECK-NEXT: vcmp.s8 gt, q0, zr362; CHECK-NEXT: vpsel q0, q2, q1363; CHECK-NEXT: bx lr364entry:365 %c = icmp sgt <16 x i8> %src, zeroinitializer366 %0 = zext <16 x i1> %c to <16 x i8>367 ret <16 x i8> %0368}369 370define arm_aapcs_vfpcc <2 x i64> @zext_v2i1_v2i64(<2 x i64> %src) {371; CHECK-LABEL: zext_v2i1_v2i64:372; CHECK: @ %bb.0: @ %entry373; CHECK-NEXT: vmov r0, r1, d1374; CHECK-NEXT: mov.w r12, #0375; CHECK-NEXT: vmov r2, r3, d0376; CHECK-NEXT: vldr s1, .LCPI12_0377; CHECK-NEXT: vmov.f32 s3, s1378; CHECK-NEXT: rsbs r0, r0, #0379; CHECK-NEXT: sbcs.w r0, r12, r1380; CHECK-NEXT: cset r0, lt381; CHECK-NEXT: rsbs r1, r2, #0382; CHECK-NEXT: sbcs.w r1, r12, r3383; CHECK-NEXT: vmov s2, r0384; CHECK-NEXT: cset r0, lt385; CHECK-NEXT: vmov s0, r0386; CHECK-NEXT: bx lr387; CHECK-NEXT: .p2align 2388; CHECK-NEXT: @ %bb.1:389; CHECK-NEXT: .LCPI12_0:390; CHECK-NEXT: .long 0x00000000 @ float 0391entry:392 %c = icmp sgt <2 x i64> %src, zeroinitializer393 %0 = zext <2 x i1> %c to <2 x i64>394 ret <2 x i64> %0395}396 397define arm_aapcs_vfpcc <2 x i64> @zext_v2i1_v2f64(<2 x double> %src) {398; CHECK-MVE-LABEL: zext_v2i1_v2f64:399; CHECK-MVE: @ %bb.0: @ %entry400; CHECK-MVE-NEXT: .save {r4, r5, r6, lr}401; CHECK-MVE-NEXT: push {r4, r5, r6, lr}402; CHECK-MVE-NEXT: .vsave {d8, d9}403; CHECK-MVE-NEXT: vpush {d8, d9}404; CHECK-MVE-NEXT: vmov q4, q0405; CHECK-MVE-NEXT: vldr d0, .LCPI13_0406; CHECK-MVE-NEXT: vmov r0, r1, d9407; CHECK-MVE-NEXT: vmov r4, r5, d0408; CHECK-MVE-NEXT: mov r2, r4409; CHECK-MVE-NEXT: mov r3, r5410; CHECK-MVE-NEXT: bl __aeabi_dcmpeq411; CHECK-MVE-NEXT: vmov r2, r1, d8412; CHECK-MVE-NEXT: adr r3, .LCPI13_1413; CHECK-MVE-NEXT: cmp r0, #0414; CHECK-MVE-NEXT: vldrw.u32 q4, [r3]415; CHECK-MVE-NEXT: mov r3, r5416; CHECK-MVE-NEXT: csetm r6, eq417; CHECK-MVE-NEXT: mov r0, r2418; CHECK-MVE-NEXT: mov r2, r4419; CHECK-MVE-NEXT: bl __aeabi_dcmpeq420; CHECK-MVE-NEXT: cmp r0, #0421; CHECK-MVE-NEXT: csetm r0, eq422; CHECK-MVE-NEXT: vmov q0[2], q0[0], r0, r6423; CHECK-MVE-NEXT: vand q0, q0, q4424; CHECK-MVE-NEXT: vpop {d8, d9}425; CHECK-MVE-NEXT: pop {r4, r5, r6, pc}426; CHECK-MVE-NEXT: .p2align 4427; CHECK-MVE-NEXT: @ %bb.1:428; CHECK-MVE-NEXT: .LCPI13_1:429; CHECK-MVE-NEXT: .long 1 @ 0x1430; CHECK-MVE-NEXT: .long 0 @ 0x0431; CHECK-MVE-NEXT: .long 1 @ 0x1432; CHECK-MVE-NEXT: .long 0 @ 0x0433; CHECK-MVE-NEXT: .LCPI13_0:434; CHECK-MVE-NEXT: .long 0 @ double 0435; CHECK-MVE-NEXT: .long 0436;437; CHECK-MVEFP-LABEL: zext_v2i1_v2f64:438; CHECK-MVEFP: @ %bb.0: @ %entry439; CHECK-MVEFP-NEXT: .save {r4, r5, r6, lr}440; CHECK-MVEFP-NEXT: push {r4, r5, r6, lr}441; CHECK-MVEFP-NEXT: .vsave {d8, d9}442; CHECK-MVEFP-NEXT: vpush {d8, d9}443; CHECK-MVEFP-NEXT: vmov q4, q0444; CHECK-MVEFP-NEXT: vldr d0, .LCPI13_0445; CHECK-MVEFP-NEXT: vmov r0, r1, d8446; CHECK-MVEFP-NEXT: vmov r4, r5, d0447; CHECK-MVEFP-NEXT: mov r2, r4448; CHECK-MVEFP-NEXT: mov r3, r5449; CHECK-MVEFP-NEXT: bl __aeabi_dcmpeq450; CHECK-MVEFP-NEXT: mov r6, r0451; CHECK-MVEFP-NEXT: vmov r0, r1, d9452; CHECK-MVEFP-NEXT: mov r2, r4453; CHECK-MVEFP-NEXT: mov r3, r5454; CHECK-MVEFP-NEXT: bl __aeabi_dcmpeq455; CHECK-MVEFP-NEXT: cmp r0, #0456; CHECK-MVEFP-NEXT: vldr s1, .LCPI13_1457; CHECK-MVEFP-NEXT: cset r0, eq458; CHECK-MVEFP-NEXT: cmp r6, #0459; CHECK-MVEFP-NEXT: vmov s2, r0460; CHECK-MVEFP-NEXT: cset r0, eq461; CHECK-MVEFP-NEXT: vmov s0, r0462; CHECK-MVEFP-NEXT: vmov.f32 s3, s1463; CHECK-MVEFP-NEXT: vpop {d8, d9}464; CHECK-MVEFP-NEXT: pop {r4, r5, r6, pc}465; CHECK-MVEFP-NEXT: .p2align 3466; CHECK-MVEFP-NEXT: @ %bb.1:467; CHECK-MVEFP-NEXT: .LCPI13_0:468; CHECK-MVEFP-NEXT: .long 0 @ double 0469; CHECK-MVEFP-NEXT: .long 0470; CHECK-MVEFP-NEXT: .LCPI13_1:471; CHECK-MVEFP-NEXT: .long 0x00000000 @ float 0472entry:473 %c = fcmp une <2 x double> %src, zeroinitializer474 %0 = zext <2 x i1> %c to <2 x i64>475 ret <2 x i64> %0476}477 478 479define arm_aapcs_vfpcc <4 x i32> @trunc_v4i1_v4i32(<4 x i32> %src) {480; CHECK-LABEL: trunc_v4i1_v4i32:481; CHECK: @ %bb.0: @ %entry482; CHECK-NEXT: vmov.i32 q2, #0x1483; CHECK-NEXT: vmov.i32 q1, #0x0484; CHECK-NEXT: vand q2, q0, q2485; CHECK-NEXT: vcmp.i32 ne, q2, zr486; CHECK-NEXT: vpsel q0, q0, q1487; CHECK-NEXT: bx lr488entry:489 %0 = trunc <4 x i32> %src to <4 x i1>490 %1 = select <4 x i1> %0, <4 x i32> %src, <4 x i32> zeroinitializer491 ret <4 x i32> %1492}493 494define arm_aapcs_vfpcc <8 x i16> @trunc_v8i1_v8i16(<8 x i16> %src) {495; CHECK-LABEL: trunc_v8i1_v8i16:496; CHECK: @ %bb.0: @ %entry497; CHECK-NEXT: vmov.i16 q2, #0x1498; CHECK-NEXT: vmov.i32 q1, #0x0499; CHECK-NEXT: vand q2, q0, q2500; CHECK-NEXT: vcmp.i16 ne, q2, zr501; CHECK-NEXT: vpsel q0, q0, q1502; CHECK-NEXT: bx lr503entry:504 %0 = trunc <8 x i16> %src to <8 x i1>505 %1 = select <8 x i1> %0, <8 x i16> %src, <8 x i16> zeroinitializer506 ret <8 x i16> %1507}508 509define arm_aapcs_vfpcc <16 x i8> @trunc_v16i1_v16i8(<16 x i8> %src) {510; CHECK-LABEL: trunc_v16i1_v16i8:511; CHECK: @ %bb.0: @ %entry512; CHECK-NEXT: vmov.i8 q2, #0x1513; CHECK-NEXT: vmov.i32 q1, #0x0514; CHECK-NEXT: vand q2, q0, q2515; CHECK-NEXT: vcmp.i8 ne, q2, zr516; CHECK-NEXT: vpsel q0, q0, q1517; CHECK-NEXT: bx lr518entry:519 %0 = trunc <16 x i8> %src to <16 x i1>520 %1 = select <16 x i1> %0, <16 x i8> %src, <16 x i8> zeroinitializer521 ret <16 x i8> %1522}523 524define arm_aapcs_vfpcc <2 x i64> @trunc_v2i1_v2i64(<2 x i64> %src) {525; CHECK-LABEL: trunc_v2i1_v2i64:526; CHECK: @ %bb.0: @ %entry527; CHECK-NEXT: vmov r1, s0528; CHECK-NEXT: movs r0, #0529; CHECK-NEXT: vmov.i32 q1, #0x0530; CHECK-NEXT: and r1, r1, #1531; CHECK-NEXT: rsbs r1, r1, #0532; CHECK-NEXT: bfi r0, r1, #0, #8533; CHECK-NEXT: vmov r1, s2534; CHECK-NEXT: and r1, r1, #1535; CHECK-NEXT: rsbs r1, r1, #0536; CHECK-NEXT: bfi r0, r1, #8, #8537; CHECK-NEXT: vmsr p0, r0538; CHECK-NEXT: vpsel q0, q0, q1539; CHECK-NEXT: bx lr540entry:541 %0 = trunc <2 x i64> %src to <2 x i1>542 %1 = select <2 x i1> %0, <2 x i64> %src, <2 x i64> zeroinitializer543 ret <2 x i64> %1544}545 546 547define arm_aapcs_vfpcc <4 x float> @uitofp_v4i1_v4f32(<4 x i32> %src) {548; CHECK-MVE-LABEL: uitofp_v4i1_v4f32:549; CHECK-MVE: @ %bb.0: @ %entry550; CHECK-MVE-NEXT: vcmp.s32 gt, q0, zr551; CHECK-MVE-NEXT: vmrs r0, p0552; CHECK-MVE-NEXT: ubfx r2, r0, #12, #1553; CHECK-MVE-NEXT: ubfx r1, r0, #8, #1554; CHECK-MVE-NEXT: vmov s0, r2555; CHECK-MVE-NEXT: ubfx r2, r0, #4, #1556; CHECK-MVE-NEXT: and r0, r0, #1557; CHECK-MVE-NEXT: vcvt.f32.u32 s3, s0558; CHECK-MVE-NEXT: vmov s0, r1559; CHECK-MVE-NEXT: vcvt.f32.u32 s2, s0560; CHECK-MVE-NEXT: vmov s0, r2561; CHECK-MVE-NEXT: vcvt.f32.u32 s1, s0562; CHECK-MVE-NEXT: vmov s0, r0563; CHECK-MVE-NEXT: vcvt.f32.u32 s0, s0564; CHECK-MVE-NEXT: bx lr565;566; CHECK-MVEFP-LABEL: uitofp_v4i1_v4f32:567; CHECK-MVEFP: @ %bb.0: @ %entry568; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0569; CHECK-MVEFP-NEXT: vmov.f32 q2, #1.000000e+00570; CHECK-MVEFP-NEXT: vcmp.s32 gt, q0, zr571; CHECK-MVEFP-NEXT: vpsel q0, q2, q1572; CHECK-MVEFP-NEXT: bx lr573entry:574 %c = icmp sgt <4 x i32> %src, zeroinitializer575 %0 = uitofp <4 x i1> %c to <4 x float>576 ret <4 x float> %0577}578 579define arm_aapcs_vfpcc <4 x float> @sitofp_v4i1_v4f32(<4 x i32> %src) {580; CHECK-MVE-LABEL: sitofp_v4i1_v4f32:581; CHECK-MVE: @ %bb.0: @ %entry582; CHECK-MVE-NEXT: vcmp.s32 gt, q0, zr583; CHECK-MVE-NEXT: vmrs r0, p0584; CHECK-MVE-NEXT: and r1, r0, #1585; CHECK-MVE-NEXT: ubfx r2, r0, #8, #1586; CHECK-MVE-NEXT: ubfx r3, r0, #4, #1587; CHECK-MVE-NEXT: ubfx r0, r0, #12, #1588; CHECK-MVE-NEXT: rsbs r2, r2, #0589; CHECK-MVE-NEXT: rsbs r0, r0, #0590; CHECK-MVE-NEXT: vmov s0, r0591; CHECK-MVE-NEXT: rsbs r0, r3, #0592; CHECK-MVE-NEXT: vcvt.f32.s32 s3, s0593; CHECK-MVE-NEXT: vmov s0, r2594; CHECK-MVE-NEXT: vcvt.f32.s32 s2, s0595; CHECK-MVE-NEXT: vmov s0, r0596; CHECK-MVE-NEXT: rsbs r0, r1, #0597; CHECK-MVE-NEXT: vcvt.f32.s32 s1, s0598; CHECK-MVE-NEXT: vmov s0, r0599; CHECK-MVE-NEXT: vcvt.f32.s32 s0, s0600; CHECK-MVE-NEXT: bx lr601;602; CHECK-MVEFP-LABEL: sitofp_v4i1_v4f32:603; CHECK-MVEFP: @ %bb.0: @ %entry604; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0605; CHECK-MVEFP-NEXT: vmov.f32 q2, #-1.000000e+00606; CHECK-MVEFP-NEXT: vcmp.s32 gt, q0, zr607; CHECK-MVEFP-NEXT: vpsel q0, q2, q1608; CHECK-MVEFP-NEXT: bx lr609entry:610 %c = icmp sgt <4 x i32> %src, zeroinitializer611 %0 = sitofp <4 x i1> %c to <4 x float>612 ret <4 x float> %0613}614 615define arm_aapcs_vfpcc <4 x float> @fptoui_v4i1_v4f32(<4 x float> %src) {616; CHECK-MVE-LABEL: fptoui_v4i1_v4f32:617; CHECK-MVE: @ %bb.0: @ %entry618; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2619; CHECK-MVE-NEXT: vldr s10, .LCPI20_0620; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s1621; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s3622; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0623; CHECK-MVE-NEXT: vmov.f32 s8, #1.000000e+00624; CHECK-MVE-NEXT: vmov r3, s2625; CHECK-MVE-NEXT: vmov r2, s6626; CHECK-MVE-NEXT: vmov r1, s4627; CHECK-MVE-NEXT: vmov r0, s0628; CHECK-MVE-NEXT: cmp r3, #0629; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s8630; CHECK-MVE-NEXT: cmp r2, #0631; CHECK-MVE-NEXT: vseleq.f32 s1, s10, s8632; CHECK-MVE-NEXT: cmp r1, #0633; CHECK-MVE-NEXT: vseleq.f32 s3, s10, s8634; CHECK-MVE-NEXT: cmp r0, #0635; CHECK-MVE-NEXT: vseleq.f32 s0, s10, s8636; CHECK-MVE-NEXT: bx lr637; CHECK-MVE-NEXT: .p2align 2638; CHECK-MVE-NEXT: @ %bb.1:639; CHECK-MVE-NEXT: .LCPI20_0:640; CHECK-MVE-NEXT: .long 0x00000000 @ float 0641;642; CHECK-MVEFP-LABEL: fptoui_v4i1_v4f32:643; CHECK-MVEFP: @ %bb.0: @ %entry644; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0645; CHECK-MVEFP-NEXT: vmov.f32 q2, #1.000000e+00646; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr647; CHECK-MVEFP-NEXT: vpsel q0, q2, q1648; CHECK-MVEFP-NEXT: bx lr649entry:650 %0 = fptoui <4 x float> %src to <4 x i1>651 %s = select <4 x i1> %0, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> zeroinitializer652 ret <4 x float> %s653}654 655define arm_aapcs_vfpcc <4 x float> @fptosi_v4i1_v4f32(<4 x float> %src) {656; CHECK-MVE-LABEL: fptosi_v4i1_v4f32:657; CHECK-MVE: @ %bb.0: @ %entry658; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2659; CHECK-MVE-NEXT: vldr s8, .LCPI21_0660; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s1661; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s3662; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0663; CHECK-MVE-NEXT: vmov.f32 s6, #1.000000e+00664; CHECK-MVE-NEXT: vmov r3, s2665; CHECK-MVE-NEXT: vmov r2, s4666; CHECK-MVE-NEXT: vmov r1, s10667; CHECK-MVE-NEXT: vmov r0, s0668; CHECK-MVE-NEXT: lsls r3, r3, #31669; CHECK-MVE-NEXT: lsl.w r2, r2, #31670; CHECK-MVE-NEXT: vseleq.f32 s2, s8, s6671; CHECK-MVE-NEXT: cmp r2, #0672; CHECK-MVE-NEXT: lsl.w r1, r1, #31673; CHECK-MVE-NEXT: vseleq.f32 s1, s8, s6674; CHECK-MVE-NEXT: cmp r1, #0675; CHECK-MVE-NEXT: lsl.w r0, r0, #31676; CHECK-MVE-NEXT: vseleq.f32 s3, s8, s6677; CHECK-MVE-NEXT: cmp r0, #0678; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s6679; CHECK-MVE-NEXT: bx lr680; CHECK-MVE-NEXT: .p2align 2681; CHECK-MVE-NEXT: @ %bb.1:682; CHECK-MVE-NEXT: .LCPI21_0:683; CHECK-MVE-NEXT: .long 0x00000000 @ float 0684;685; CHECK-MVEFP-LABEL: fptosi_v4i1_v4f32:686; CHECK-MVEFP: @ %bb.0: @ %entry687; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0688; CHECK-MVEFP-NEXT: vmov.f32 q2, #1.000000e+00689; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr690; CHECK-MVEFP-NEXT: vpsel q0, q2, q1691; CHECK-MVEFP-NEXT: bx lr692entry:693 %0 = fptosi <4 x float> %src to <4 x i1>694 %s = select <4 x i1> %0, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> zeroinitializer695 ret <4 x float> %s696}697 698define arm_aapcs_vfpcc <8 x half> @uitofp_v8i1_v8f16(<8 x i16> %src) {699; CHECK-MVE-LABEL: uitofp_v8i1_v8f16:700; CHECK-MVE: @ %bb.0: @ %entry701; CHECK-MVE-NEXT: vcmp.s16 gt, q0, zr702; CHECK-MVE-NEXT: vmrs r0, p0703; CHECK-MVE-NEXT: and r1, r0, #1704; CHECK-MVE-NEXT: ubfx r2, r0, #2, #1705; CHECK-MVE-NEXT: vmov s0, r1706; CHECK-MVE-NEXT: ubfx r1, r0, #4, #1707; CHECK-MVE-NEXT: vmov s2, r2708; CHECK-MVE-NEXT: ubfx r2, r0, #6, #1709; CHECK-MVE-NEXT: vcvt.f16.u32 s2, s2710; CHECK-MVE-NEXT: vcvt.f16.u32 s0, s0711; CHECK-MVE-NEXT: vmov s4, r2712; CHECK-MVE-NEXT: vins.f16 s0, s2713; CHECK-MVE-NEXT: vmov s2, r1714; CHECK-MVE-NEXT: ubfx r1, r0, #8, #1715; CHECK-MVE-NEXT: ubfx r2, r0, #10, #1716; CHECK-MVE-NEXT: vcvt.f16.u32 s1, s2717; CHECK-MVE-NEXT: vcvt.f16.u32 s4, s4718; CHECK-MVE-NEXT: vmov s2, r1719; CHECK-MVE-NEXT: ubfx r1, r0, #12, #1720; CHECK-MVE-NEXT: vins.f16 s1, s4721; CHECK-MVE-NEXT: vmov s4, r2722; CHECK-MVE-NEXT: ubfx r0, r0, #14, #1723; CHECK-MVE-NEXT: vcvt.f16.u32 s4, s4724; CHECK-MVE-NEXT: vcvt.f16.u32 s2, s2725; CHECK-MVE-NEXT: vins.f16 s2, s4726; CHECK-MVE-NEXT: vmov s4, r0727; CHECK-MVE-NEXT: vmov s6, r1728; CHECK-MVE-NEXT: vcvt.f16.u32 s4, s4729; CHECK-MVE-NEXT: vcvt.f16.u32 s3, s6730; CHECK-MVE-NEXT: vins.f16 s3, s4731; CHECK-MVE-NEXT: bx lr732;733; CHECK-MVEFP-LABEL: uitofp_v8i1_v8f16:734; CHECK-MVEFP: @ %bb.0: @ %entry735; CHECK-MVEFP-NEXT: vmov.i16 q1, #0x0736; CHECK-MVEFP-NEXT: vmov.i16 q2, #0x3c00737; CHECK-MVEFP-NEXT: vcmp.s16 gt, q0, zr738; CHECK-MVEFP-NEXT: vpsel q0, q2, q1739; CHECK-MVEFP-NEXT: bx lr740entry:741 %c = icmp sgt <8 x i16> %src, zeroinitializer742 %0 = uitofp <8 x i1> %c to <8 x half>743 ret <8 x half> %0744}745 746define arm_aapcs_vfpcc <8 x half> @sitofp_v8i1_v8f16(<8 x i16> %src) {747; CHECK-MVE-LABEL: sitofp_v8i1_v8f16:748; CHECK-MVE: @ %bb.0: @ %entry749; CHECK-MVE-NEXT: vcmp.s16 gt, q0, zr750; CHECK-MVE-NEXT: vmrs r0, p0751; CHECK-MVE-NEXT: and r1, r0, #1752; CHECK-MVE-NEXT: ubfx r2, r0, #2, #1753; CHECK-MVE-NEXT: rsbs r1, r1, #0754; CHECK-MVE-NEXT: rsbs r2, r2, #0755; CHECK-MVE-NEXT: vmov s0, r2756; CHECK-MVE-NEXT: ubfx r2, r0, #6, #1757; CHECK-MVE-NEXT: vcvt.f16.s32 s2, s0758; CHECK-MVE-NEXT: vmov s0, r1759; CHECK-MVE-NEXT: ubfx r1, r0, #4, #1760; CHECK-MVE-NEXT: rsbs r2, r2, #0761; CHECK-MVE-NEXT: vcvt.f16.s32 s0, s0762; CHECK-MVE-NEXT: rsbs r1, r1, #0763; CHECK-MVE-NEXT: vins.f16 s0, s2764; CHECK-MVE-NEXT: vmov s2, r2765; CHECK-MVE-NEXT: ubfx r2, r0, #10, #1766; CHECK-MVE-NEXT: vmov s4, r1767; CHECK-MVE-NEXT: ubfx r1, r0, #8, #1768; CHECK-MVE-NEXT: rsbs r2, r2, #0769; CHECK-MVE-NEXT: vcvt.f16.s32 s2, s2770; CHECK-MVE-NEXT: vcvt.f16.s32 s1, s4771; CHECK-MVE-NEXT: rsbs r1, r1, #0772; CHECK-MVE-NEXT: vins.f16 s1, s2773; CHECK-MVE-NEXT: vmov s2, r2774; CHECK-MVE-NEXT: vcvt.f16.s32 s4, s2775; CHECK-MVE-NEXT: vmov s2, r1776; CHECK-MVE-NEXT: ubfx r1, r0, #12, #1777; CHECK-MVE-NEXT: ubfx r0, r0, #14, #1778; CHECK-MVE-NEXT: rsbs r1, r1, #0779; CHECK-MVE-NEXT: rsbs r0, r0, #0780; CHECK-MVE-NEXT: vcvt.f16.s32 s2, s2781; CHECK-MVE-NEXT: vins.f16 s2, s4782; CHECK-MVE-NEXT: vmov s4, r0783; CHECK-MVE-NEXT: vmov s6, r1784; CHECK-MVE-NEXT: vcvt.f16.s32 s4, s4785; CHECK-MVE-NEXT: vcvt.f16.s32 s3, s6786; CHECK-MVE-NEXT: vins.f16 s3, s4787; CHECK-MVE-NEXT: bx lr788;789; CHECK-MVEFP-LABEL: sitofp_v8i1_v8f16:790; CHECK-MVEFP: @ %bb.0: @ %entry791; CHECK-MVEFP-NEXT: vmov.i16 q1, #0x0792; CHECK-MVEFP-NEXT: vmov.i16 q2, #0xbc00793; CHECK-MVEFP-NEXT: vcmp.s16 gt, q0, zr794; CHECK-MVEFP-NEXT: vpsel q0, q2, q1795; CHECK-MVEFP-NEXT: bx lr796entry:797 %c = icmp sgt <8 x i16> %src, zeroinitializer798 %0 = sitofp <8 x i1> %c to <8 x half>799 ret <8 x half> %0800}801 802define arm_aapcs_vfpcc <8 x half> @fptoui_v8i1_v8f16(<8 x half> %src) {803; CHECK-MVE-LABEL: fptoui_v8i1_v8f16:804; CHECK-MVE: @ %bb.0: @ %entry805; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s0806; CHECK-MVE-NEXT: vmovx.f16 s0, s0807; CHECK-MVE-NEXT: vcvt.s32.f16 s0, s0808; CHECK-MVE-NEXT: vmov r0, s4809; CHECK-MVE-NEXT: vmov r1, s0810; CHECK-MVE-NEXT: vldr.16 s8, .LCPI24_0811; CHECK-MVE-NEXT: vmov.f16 s6, #1.000000e+00812; CHECK-MVE-NEXT: vmovx.f16 s10, s1813; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10814; CHECK-MVE-NEXT: cmp r1, #0815; CHECK-MVE-NEXT: vmov r1, s10816; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6817; CHECK-MVE-NEXT: cmp r0, #0818; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s6819; CHECK-MVE-NEXT: vmovx.f16 s10, s3820; CHECK-MVE-NEXT: vins.f16 s0, s4821; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s1822; CHECK-MVE-NEXT: vmov r0, s4823; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10824; CHECK-MVE-NEXT: cmp r1, #0825; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6826; CHECK-MVE-NEXT: cmp r0, #0827; CHECK-MVE-NEXT: vseleq.f16 s1, s8, s6828; CHECK-MVE-NEXT: vins.f16 s1, s4829; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s2830; CHECK-MVE-NEXT: vmovx.f16 s2, s2831; CHECK-MVE-NEXT: vmov r0, s4832; CHECK-MVE-NEXT: vcvt.s32.f16 s2, s2833; CHECK-MVE-NEXT: vmov r1, s2834; CHECK-MVE-NEXT: cmp r1, #0835; CHECK-MVE-NEXT: vmov r1, s10836; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6837; CHECK-MVE-NEXT: cmp r0, #0838; CHECK-MVE-NEXT: vseleq.f16 s2, s8, s6839; CHECK-MVE-NEXT: vins.f16 s2, s4840; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s3841; CHECK-MVE-NEXT: vmov r0, s4842; CHECK-MVE-NEXT: cmp r1, #0843; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6844; CHECK-MVE-NEXT: cmp r0, #0845; CHECK-MVE-NEXT: vseleq.f16 s3, s8, s6846; CHECK-MVE-NEXT: vins.f16 s3, s4847; CHECK-MVE-NEXT: bx lr848; CHECK-MVE-NEXT: .p2align 1849; CHECK-MVE-NEXT: @ %bb.1:850; CHECK-MVE-NEXT: .LCPI24_0:851; CHECK-MVE-NEXT: .short 0x0000 @ half 0852;853; CHECK-MVEFP-LABEL: fptoui_v8i1_v8f16:854; CHECK-MVEFP: @ %bb.0: @ %entry855; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0856; CHECK-MVEFP-NEXT: vmov.i16 q2, #0x3c00857; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr858; CHECK-MVEFP-NEXT: vpsel q0, q2, q1859; CHECK-MVEFP-NEXT: bx lr860entry:861 %0 = fptoui <8 x half> %src to <8 x i1>862 %s = select <8 x i1> %0, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, <8 x half> zeroinitializer863 ret <8 x half> %s864}865 866define arm_aapcs_vfpcc <8 x half> @fptosi_v8i1_v8f16(<8 x half> %src) {867; CHECK-MVE-LABEL: fptosi_v8i1_v8f16:868; CHECK-MVE: @ %bb.0: @ %entry869; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s0870; CHECK-MVE-NEXT: vmovx.f16 s0, s0871; CHECK-MVE-NEXT: vcvt.s32.f16 s0, s0872; CHECK-MVE-NEXT: vmov r0, s4873; CHECK-MVE-NEXT: vmov r1, s0874; CHECK-MVE-NEXT: vldr.16 s8, .LCPI25_0875; CHECK-MVE-NEXT: vmov.f16 s6, #1.000000e+00876; CHECK-MVE-NEXT: vmovx.f16 s10, s1877; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10878; CHECK-MVE-NEXT: lsls r0, r0, #31879; CHECK-MVE-NEXT: lsls r1, r1, #31880; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6881; CHECK-MVE-NEXT: cmp r0, #0882; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s6883; CHECK-MVE-NEXT: vmov r1, s10884; CHECK-MVE-NEXT: vins.f16 s0, s4885; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s1886; CHECK-MVE-NEXT: vmov r0, s4887; CHECK-MVE-NEXT: vmovx.f16 s10, s3888; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10889; CHECK-MVE-NEXT: lsls r1, r1, #31890; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6891; CHECK-MVE-NEXT: lsls r0, r0, #31892; CHECK-MVE-NEXT: cmp r0, #0893; CHECK-MVE-NEXT: vseleq.f16 s1, s8, s6894; CHECK-MVE-NEXT: vins.f16 s1, s4895; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s2896; CHECK-MVE-NEXT: vmovx.f16 s2, s2897; CHECK-MVE-NEXT: vmov r0, s4898; CHECK-MVE-NEXT: vcvt.s32.f16 s2, s2899; CHECK-MVE-NEXT: vmov r1, s2900; CHECK-MVE-NEXT: lsls r0, r0, #31901; CHECK-MVE-NEXT: lsls r1, r1, #31902; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6903; CHECK-MVE-NEXT: cmp r0, #0904; CHECK-MVE-NEXT: vseleq.f16 s2, s8, s6905; CHECK-MVE-NEXT: vmov r1, s10906; CHECK-MVE-NEXT: vins.f16 s2, s4907; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s3908; CHECK-MVE-NEXT: vmov r0, s4909; CHECK-MVE-NEXT: lsls r1, r1, #31910; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6911; CHECK-MVE-NEXT: lsls r0, r0, #31912; CHECK-MVE-NEXT: cmp r0, #0913; CHECK-MVE-NEXT: vseleq.f16 s3, s8, s6914; CHECK-MVE-NEXT: vins.f16 s3, s4915; CHECK-MVE-NEXT: bx lr916; CHECK-MVE-NEXT: .p2align 1917; CHECK-MVE-NEXT: @ %bb.1:918; CHECK-MVE-NEXT: .LCPI25_0:919; CHECK-MVE-NEXT: .short 0x0000 @ half 0920;921; CHECK-MVEFP-LABEL: fptosi_v8i1_v8f16:922; CHECK-MVEFP: @ %bb.0: @ %entry923; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0924; CHECK-MVEFP-NEXT: vmov.i16 q2, #0x3c00925; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr926; CHECK-MVEFP-NEXT: vpsel q0, q2, q1927; CHECK-MVEFP-NEXT: bx lr928entry:929 %0 = fptosi <8 x half> %src to <8 x i1>930 %s = select <8 x i1> %0, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, <8 x half> zeroinitializer931 ret <8 x half> %s932}933 934 935define arm_aapcs_vfpcc <2 x double> @uitofp_v2i1_v2f64(<2 x i64> %src) {936; CHECK-LABEL: uitofp_v2i1_v2f64:937; CHECK: @ %bb.0: @ %entry938; CHECK-NEXT: .save {r4, lr}939; CHECK-NEXT: push {r4, lr}940; CHECK-NEXT: .vsave {d8, d9}941; CHECK-NEXT: vpush {d8, d9}942; CHECK-NEXT: vmov q4, q0943; CHECK-NEXT: movs r4, #0944; CHECK-NEXT: vmov r0, r1, d9945; CHECK-NEXT: rsbs r0, r0, #0946; CHECK-NEXT: sbcs.w r0, r4, r1947; CHECK-NEXT: cset r0, lt948; CHECK-NEXT: bl __aeabi_ui2d949; CHECK-NEXT: vmov r2, r3, d8950; CHECK-NEXT: vmov d9, r0, r1951; CHECK-NEXT: rsbs r2, r2, #0952; CHECK-NEXT: sbcs.w r2, r4, r3953; CHECK-NEXT: cset r2, lt954; CHECK-NEXT: mov r0, r2955; CHECK-NEXT: bl __aeabi_ui2d956; CHECK-NEXT: vmov d8, r0, r1957; CHECK-NEXT: vmov q0, q4958; CHECK-NEXT: vpop {d8, d9}959; CHECK-NEXT: pop {r4, pc}960entry:961 %c = icmp sgt <2 x i64> %src, zeroinitializer962 %0 = uitofp <2 x i1> %c to <2 x double>963 ret <2 x double> %0964}965 966define arm_aapcs_vfpcc <2 x double> @sitofp_v2i1_v2f64(<2 x i64> %src) {967; CHECK-LABEL: sitofp_v2i1_v2f64:968; CHECK: @ %bb.0: @ %entry969; CHECK-NEXT: .save {r4, lr}970; CHECK-NEXT: push {r4, lr}971; CHECK-NEXT: .vsave {d8, d9}972; CHECK-NEXT: vpush {d8, d9}973; CHECK-NEXT: vmov q4, q0974; CHECK-NEXT: movs r4, #0975; CHECK-NEXT: vmov r0, r1, d9976; CHECK-NEXT: rsbs r0, r0, #0977; CHECK-NEXT: sbcs.w r0, r4, r1978; CHECK-NEXT: csetm r0, lt979; CHECK-NEXT: bl __aeabi_i2d980; CHECK-NEXT: vmov r2, r3, d8981; CHECK-NEXT: vmov d9, r0, r1982; CHECK-NEXT: rsbs r2, r2, #0983; CHECK-NEXT: sbcs.w r2, r4, r3984; CHECK-NEXT: csetm r2, lt985; CHECK-NEXT: mov r0, r2986; CHECK-NEXT: bl __aeabi_i2d987; CHECK-NEXT: vmov d8, r0, r1988; CHECK-NEXT: vmov q0, q4989; CHECK-NEXT: vpop {d8, d9}990; CHECK-NEXT: pop {r4, pc}991entry:992 %c = icmp sgt <2 x i64> %src, zeroinitializer993 %0 = sitofp <2 x i1> %c to <2 x double>994 ret <2 x double> %0995}996 997define arm_aapcs_vfpcc <2 x double> @fptoui_v2i1_v2f64(<2 x double> %src) {998; CHECK-LABEL: fptoui_v2i1_v2f64:999; CHECK: @ %bb.0: @ %entry1000; CHECK-NEXT: .save {r4, lr}1001; CHECK-NEXT: push {r4, lr}1002; CHECK-NEXT: .vsave {d8, d9, d10, d11}1003; CHECK-NEXT: vpush {d8, d9, d10, d11}1004; CHECK-NEXT: vmov q4, q01005; CHECK-NEXT: vmov r0, r1, d81006; CHECK-NEXT: bl __aeabi_d2iz1007; CHECK-NEXT: vmov r2, r1, d91008; CHECK-NEXT: movs r4, #01009; CHECK-NEXT: rsbs r0, r0, #01010; CHECK-NEXT: adr r3, .LCPI28_01011; CHECK-NEXT: bfi r4, r0, #0, #81012; CHECK-NEXT: vmov.i32 q4, #0x01013; CHECK-NEXT: vldrw.u32 q5, [r3]1014; CHECK-NEXT: mov r0, r21015; CHECK-NEXT: bl __aeabi_d2iz1016; CHECK-NEXT: rsbs r0, r0, #01017; CHECK-NEXT: bfi r4, r0, #8, #81018; CHECK-NEXT: vmsr p0, r41019; CHECK-NEXT: vpsel q0, q5, q41020; CHECK-NEXT: vpop {d8, d9, d10, d11}1021; CHECK-NEXT: pop {r4, pc}1022; CHECK-NEXT: .p2align 41023; CHECK-NEXT: @ %bb.1:1024; CHECK-NEXT: .LCPI28_0:1025; CHECK-NEXT: .long 0 @ double 11026; CHECK-NEXT: .long 10726932481027; CHECK-NEXT: .long 0 @ double 11028; CHECK-NEXT: .long 10726932481029entry:1030 %0 = fptoui <2 x double> %src to <2 x i1>1031 %s = select <2 x i1> %0, <2 x double> <double 1.0, double 1.0>, <2 x double> zeroinitializer1032 ret <2 x double> %s1033}1034 1035define arm_aapcs_vfpcc <2 x double> @fptosi_v2i1_v2f64(<2 x double> %src) {1036; CHECK-LABEL: fptosi_v2i1_v2f64:1037; CHECK: @ %bb.0: @ %entry1038; CHECK-NEXT: .save {r4, lr}1039; CHECK-NEXT: push {r4, lr}1040; CHECK-NEXT: .vsave {d8, d9, d10, d11}1041; CHECK-NEXT: vpush {d8, d9, d10, d11}1042; CHECK-NEXT: vmov q4, q01043; CHECK-NEXT: vmov r0, r1, d81044; CHECK-NEXT: bl __aeabi_d2iz1045; CHECK-NEXT: vmov r2, r1, d91046; CHECK-NEXT: movs r4, #01047; CHECK-NEXT: adr r3, .LCPI29_01048; CHECK-NEXT: bfi r4, r0, #0, #81049; CHECK-NEXT: vmov.i32 q4, #0x01050; CHECK-NEXT: vldrw.u32 q5, [r3]1051; CHECK-NEXT: mov r0, r21052; CHECK-NEXT: bl __aeabi_d2iz1053; CHECK-NEXT: bfi r4, r0, #8, #81054; CHECK-NEXT: vmsr p0, r41055; CHECK-NEXT: vpsel q0, q5, q41056; CHECK-NEXT: vpop {d8, d9, d10, d11}1057; CHECK-NEXT: pop {r4, pc}1058; CHECK-NEXT: .p2align 41059; CHECK-NEXT: @ %bb.1:1060; CHECK-NEXT: .LCPI29_0:1061; CHECK-NEXT: .long 0 @ double 11062; CHECK-NEXT: .long 10726932481063; CHECK-NEXT: .long 0 @ double 11064; CHECK-NEXT: .long 10726932481065entry:1066 %0 = fptosi <2 x double> %src to <2 x i1>1067 %s = select <2 x i1> %0, <2 x double> <double 1.0, double 1.0>, <2 x double> zeroinitializer1068 ret <2 x double> %s1069}1070