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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-LE3; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-BE4 5define arm_aapcs_vfpcc <4 x i32> @load_v4i1(ptr %src, <4 x i32> %a) {6; CHECK-LE-LABEL: load_v4i1:7; CHECK-LE: @ %bb.0: @ %entry8; CHECK-LE-NEXT: ldrb r0, [r0]9; CHECK-LE-NEXT: vmov.i8 q1, #0x010; CHECK-LE-NEXT: vmov.i8 q2, #0xff11; CHECK-LE-NEXT: vmsr p0, r012; CHECK-LE-NEXT: vpsel q1, q2, q113; CHECK-LE-NEXT: vmov.u8 r0, q1[2]14; CHECK-LE-NEXT: vmov.u8 r1, q1[0]15; CHECK-LE-NEXT: vmov q2[2], q2[0], r1, r016; CHECK-LE-NEXT: vmov.u8 r0, q1[3]17; CHECK-LE-NEXT: vmov.u8 r1, q1[1]18; CHECK-LE-NEXT: vmov.i32 q1, #0x019; CHECK-LE-NEXT: vmov q2[3], q2[1], r1, r020; CHECK-LE-NEXT: vcmp.i32 ne, q2, zr21; CHECK-LE-NEXT: vpsel q0, q0, q122; CHECK-LE-NEXT: bx lr23;24; CHECK-BE-LABEL: load_v4i1:25; CHECK-BE: @ %bb.0: @ %entry26; CHECK-BE-NEXT: ldrb r0, [r0]27; CHECK-BE-NEXT: vmov.i8 q1, #0x028; CHECK-BE-NEXT: vmov.i8 q2, #0xff29; CHECK-BE-NEXT: rbit r0, r030; CHECK-BE-NEXT: lsrs r0, r0, #2831; CHECK-BE-NEXT: vmsr p0, r032; CHECK-BE-NEXT: vpsel q1, q2, q133; CHECK-BE-NEXT: vmov.u8 r0, q1[2]34; CHECK-BE-NEXT: vmov.u8 r1, q1[0]35; CHECK-BE-NEXT: vmov q2[2], q2[0], r1, r036; CHECK-BE-NEXT: vmov.u8 r0, q1[3]37; CHECK-BE-NEXT: vmov.u8 r1, q1[1]38; CHECK-BE-NEXT: vrev64.32 q1, q039; CHECK-BE-NEXT: vmov q2[3], q2[1], r1, r040; CHECK-BE-NEXT: vmov.i32 q0, #0x041; CHECK-BE-NEXT: vcmp.i32 ne, q2, zr42; CHECK-BE-NEXT: vpsel q1, q1, q043; CHECK-BE-NEXT: vrev64.32 q0, q144; CHECK-BE-NEXT: bx lr45entry:46 %c = load <4 x i1>, ptr %src47 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer48 ret <4 x i32> %s49}50 51define arm_aapcs_vfpcc <8 x i16> @load_v8i1(ptr %src, <8 x i16> %a) {52; CHECK-LE-LABEL: load_v8i1:53; CHECK-LE: @ %bb.0: @ %entry54; CHECK-LE-NEXT: ldrb r0, [r0]55; CHECK-LE-NEXT: vmov.i8 q1, #0x056; CHECK-LE-NEXT: vmov.i8 q2, #0xff57; CHECK-LE-NEXT: vmsr p0, r058; CHECK-LE-NEXT: vpsel q2, q2, q159; CHECK-LE-NEXT: vmov.u8 r0, q2[0]60; CHECK-LE-NEXT: vmov.16 q1[0], r061; CHECK-LE-NEXT: vmov.u8 r0, q2[1]62; CHECK-LE-NEXT: vmov.16 q1[1], r063; CHECK-LE-NEXT: vmov.u8 r0, q2[2]64; CHECK-LE-NEXT: vmov.16 q1[2], r065; CHECK-LE-NEXT: vmov.u8 r0, q2[3]66; CHECK-LE-NEXT: vmov.16 q1[3], r067; CHECK-LE-NEXT: vmov.u8 r0, q2[4]68; CHECK-LE-NEXT: vmov.16 q1[4], r069; CHECK-LE-NEXT: vmov.u8 r0, q2[5]70; CHECK-LE-NEXT: vmov.16 q1[5], r071; CHECK-LE-NEXT: vmov.u8 r0, q2[6]72; CHECK-LE-NEXT: vmov.16 q1[6], r073; CHECK-LE-NEXT: vmov.u8 r0, q2[7]74; CHECK-LE-NEXT: vmov.16 q1[7], r075; CHECK-LE-NEXT: vcmp.i16 ne, q1, zr76; CHECK-LE-NEXT: vmov.i32 q1, #0x077; CHECK-LE-NEXT: vpsel q0, q0, q178; CHECK-LE-NEXT: bx lr79;80; CHECK-BE-LABEL: load_v8i1:81; CHECK-BE: @ %bb.0: @ %entry82; CHECK-BE-NEXT: ldrb r0, [r0]83; CHECK-BE-NEXT: vmov.i8 q1, #0x084; CHECK-BE-NEXT: vmov.i8 q2, #0xff85; CHECK-BE-NEXT: rbit r0, r086; CHECK-BE-NEXT: lsrs r0, r0, #2487; CHECK-BE-NEXT: vmsr p0, r088; CHECK-BE-NEXT: vpsel q2, q2, q189; CHECK-BE-NEXT: vmov.u8 r0, q2[0]90; CHECK-BE-NEXT: vmov.16 q1[0], r091; CHECK-BE-NEXT: vmov.u8 r0, q2[1]92; CHECK-BE-NEXT: vmov.16 q1[1], r093; CHECK-BE-NEXT: vmov.u8 r0, q2[2]94; CHECK-BE-NEXT: vmov.16 q1[2], r095; CHECK-BE-NEXT: vmov.u8 r0, q2[3]96; CHECK-BE-NEXT: vmov.16 q1[3], r097; CHECK-BE-NEXT: vmov.u8 r0, q2[4]98; CHECK-BE-NEXT: vmov.16 q1[4], r099; CHECK-BE-NEXT: vmov.u8 r0, q2[5]100; CHECK-BE-NEXT: vmov.16 q1[5], r0101; CHECK-BE-NEXT: vmov.u8 r0, q2[6]102; CHECK-BE-NEXT: vmov.16 q1[6], r0103; CHECK-BE-NEXT: vmov.u8 r0, q2[7]104; CHECK-BE-NEXT: vmov.16 q1[7], r0105; CHECK-BE-NEXT: vcmp.i16 ne, q1, zr106; CHECK-BE-NEXT: vrev64.16 q1, q0107; CHECK-BE-NEXT: vmov.i32 q0, #0x0108; CHECK-BE-NEXT: vpsel q1, q1, q0109; CHECK-BE-NEXT: vrev64.16 q0, q1110; CHECK-BE-NEXT: bx lr111entry:112 %c = load <8 x i1>, ptr %src113 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> zeroinitializer114 ret <8 x i16> %s115}116 117define arm_aapcs_vfpcc <16 x i8> @load_v16i1(ptr %src, <16 x i8> %a) {118; CHECK-LE-LABEL: load_v16i1:119; CHECK-LE: @ %bb.0: @ %entry120; CHECK-LE-NEXT: ldrh r0, [r0]121; CHECK-LE-NEXT: vmov.i32 q1, #0x0122; CHECK-LE-NEXT: vmsr p0, r0123; CHECK-LE-NEXT: vpsel q0, q0, q1124; CHECK-LE-NEXT: bx lr125;126; CHECK-BE-LABEL: load_v16i1:127; CHECK-BE: @ %bb.0: @ %entry128; CHECK-BE-NEXT: ldrh r0, [r0]129; CHECK-BE-NEXT: vrev64.8 q1, q0130; CHECK-BE-NEXT: vmov.i32 q0, #0x0131; CHECK-BE-NEXT: rbit r0, r0132; CHECK-BE-NEXT: lsrs r0, r0, #16133; CHECK-BE-NEXT: vmsr p0, r0134; CHECK-BE-NEXT: vpsel q1, q1, q0135; CHECK-BE-NEXT: vrev64.8 q0, q1136; CHECK-BE-NEXT: bx lr137entry:138 %c = load <16 x i1>, ptr %src139 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> zeroinitializer140 ret <16 x i8> %s141}142 143define arm_aapcs_vfpcc <2 x i64> @load_v2i1(ptr %src, <2 x i64> %a) {144; CHECK-LE-LABEL: load_v2i1:145; CHECK-LE: @ %bb.0: @ %entry146; CHECK-LE-NEXT: ldrb r0, [r0]147; CHECK-LE-NEXT: vmov.i8 q1, #0x0148; CHECK-LE-NEXT: vmov.i8 q2, #0xff149; CHECK-LE-NEXT: vmsr p0, r0150; CHECK-LE-NEXT: vpsel q1, q2, q1151; CHECK-LE-NEXT: vmov.u8 r0, q1[1]152; CHECK-LE-NEXT: vmov.u8 r1, q1[0]153; CHECK-LE-NEXT: vmov q1[2], q1[0], r1, r0154; CHECK-LE-NEXT: vmov q1[3], q1[1], r1, r0155; CHECK-LE-NEXT: vcmp.i32 ne, q1, zr156; CHECK-LE-NEXT: vmov.i32 q1, #0x0157; CHECK-LE-NEXT: vpsel q0, q0, q1158; CHECK-LE-NEXT: bx lr159;160; CHECK-BE-LABEL: load_v2i1:161; CHECK-BE: @ %bb.0: @ %entry162; CHECK-BE-NEXT: ldrb r0, [r0]163; CHECK-BE-NEXT: vmov.i8 q1, #0x0164; CHECK-BE-NEXT: vmov.i8 q2, #0xff165; CHECK-BE-NEXT: rbit r0, r0166; CHECK-BE-NEXT: lsrs r0, r0, #30167; CHECK-BE-NEXT: vmsr p0, r0168; CHECK-BE-NEXT: vpsel q1, q2, q1169; CHECK-BE-NEXT: vmov.u8 r0, q1[1]170; CHECK-BE-NEXT: vmov.u8 r1, q1[0]171; CHECK-BE-NEXT: vmov q1[2], q1[0], r1, r0172; CHECK-BE-NEXT: vmov q1[3], q1[1], r1, r0173; CHECK-BE-NEXT: vcmp.i32 ne, q1, zr174; CHECK-BE-NEXT: vmov.i32 q1, #0x0175; CHECK-BE-NEXT: vpsel q0, q0, q1176; CHECK-BE-NEXT: bx lr177entry:178 %c = load <2 x i1>, ptr %src179 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> zeroinitializer180 ret <2 x i64> %s181}182 183 184define arm_aapcs_vfpcc void @store_v4i1(ptr %dst, <4 x i32> %a) {185; CHECK-LE-LABEL: store_v4i1:186; CHECK-LE: @ %bb.0: @ %entry187; CHECK-LE-NEXT: vcmp.i32 eq, q0, zr188; CHECK-LE-NEXT: movs r3, #0189; CHECK-LE-NEXT: vmrs r1, p0190; CHECK-LE-NEXT: and r2, r1, #1191; CHECK-LE-NEXT: rsbs r2, r2, #0192; CHECK-LE-NEXT: bfi r3, r2, #0, #1193; CHECK-LE-NEXT: ubfx r2, r1, #4, #1194; CHECK-LE-NEXT: rsbs r2, r2, #0195; CHECK-LE-NEXT: bfi r3, r2, #1, #1196; CHECK-LE-NEXT: ubfx r2, r1, #8, #1197; CHECK-LE-NEXT: ubfx r1, r1, #12, #1198; CHECK-LE-NEXT: rsbs r2, r2, #0199; CHECK-LE-NEXT: bfi r3, r2, #2, #1200; CHECK-LE-NEXT: rsbs r1, r1, #0201; CHECK-LE-NEXT: bfi r3, r1, #3, #1202; CHECK-LE-NEXT: strb r3, [r0]203; CHECK-LE-NEXT: bx lr204;205; CHECK-BE-LABEL: store_v4i1:206; CHECK-BE: @ %bb.0: @ %entry207; CHECK-BE-NEXT: vrev64.32 q1, q0208; CHECK-BE-NEXT: movs r3, #0209; CHECK-BE-NEXT: vcmp.i32 eq, q1, zr210; CHECK-BE-NEXT: vmrs r1, p0211; CHECK-BE-NEXT: ubfx r2, r1, #12, #1212; CHECK-BE-NEXT: rsbs r2, r2, #0213; CHECK-BE-NEXT: bfi r3, r2, #0, #1214; CHECK-BE-NEXT: ubfx r2, r1, #8, #1215; CHECK-BE-NEXT: rsbs r2, r2, #0216; CHECK-BE-NEXT: bfi r3, r2, #1, #1217; CHECK-BE-NEXT: ubfx r2, r1, #4, #1218; CHECK-BE-NEXT: and r1, r1, #1219; CHECK-BE-NEXT: rsbs r2, r2, #0220; CHECK-BE-NEXT: bfi r3, r2, #2, #1221; CHECK-BE-NEXT: rsbs r1, r1, #0222; CHECK-BE-NEXT: bfi r3, r1, #3, #1223; CHECK-BE-NEXT: strb r3, [r0]224; CHECK-BE-NEXT: bx lr225entry:226 %c = icmp eq <4 x i32> %a, zeroinitializer227 store <4 x i1> %c, ptr %dst228 ret void229}230 231define arm_aapcs_vfpcc void @store_v8i1(ptr %dst, <8 x i16> %a) {232; CHECK-LE-LABEL: store_v8i1:233; CHECK-LE: @ %bb.0: @ %entry234; CHECK-LE-NEXT: vcmp.i16 eq, q0, zr235; CHECK-LE-NEXT: vmrs r2, p0236; CHECK-LE-NEXT: and r1, r2, #1237; CHECK-LE-NEXT: rsbs r3, r1, #0238; CHECK-LE-NEXT: movs r1, #0239; CHECK-LE-NEXT: bfi r1, r3, #0, #1240; CHECK-LE-NEXT: ubfx r3, r2, #2, #1241; CHECK-LE-NEXT: rsbs r3, r3, #0242; CHECK-LE-NEXT: bfi r1, r3, #1, #1243; CHECK-LE-NEXT: ubfx r3, r2, #4, #1244; CHECK-LE-NEXT: rsbs r3, r3, #0245; CHECK-LE-NEXT: bfi r1, r3, #2, #1246; CHECK-LE-NEXT: ubfx r3, r2, #6, #1247; CHECK-LE-NEXT: rsbs r3, r3, #0248; CHECK-LE-NEXT: bfi r1, r3, #3, #1249; CHECK-LE-NEXT: ubfx r3, r2, #8, #1250; CHECK-LE-NEXT: rsbs r3, r3, #0251; CHECK-LE-NEXT: bfi r1, r3, #4, #1252; CHECK-LE-NEXT: ubfx r3, r2, #10, #1253; CHECK-LE-NEXT: rsbs r3, r3, #0254; CHECK-LE-NEXT: bfi r1, r3, #5, #1255; CHECK-LE-NEXT: ubfx r3, r2, #12, #1256; CHECK-LE-NEXT: ubfx r2, r2, #14, #1257; CHECK-LE-NEXT: rsbs r3, r3, #0258; CHECK-LE-NEXT: bfi r1, r3, #6, #1259; CHECK-LE-NEXT: rsbs r2, r2, #0260; CHECK-LE-NEXT: bfi r1, r2, #7, #1261; CHECK-LE-NEXT: strb r1, [r0]262; CHECK-LE-NEXT: bx lr263;264; CHECK-BE-LABEL: store_v8i1:265; CHECK-BE: @ %bb.0: @ %entry266; CHECK-BE-NEXT: vrev64.16 q1, q0267; CHECK-BE-NEXT: vcmp.i16 eq, q1, zr268; CHECK-BE-NEXT: vmrs r2, p0269; CHECK-BE-NEXT: ubfx r1, r2, #14, #1270; CHECK-BE-NEXT: rsbs r3, r1, #0271; CHECK-BE-NEXT: movs r1, #0272; CHECK-BE-NEXT: bfi r1, r3, #0, #1273; CHECK-BE-NEXT: ubfx r3, r2, #12, #1274; CHECK-BE-NEXT: rsbs r3, r3, #0275; CHECK-BE-NEXT: bfi r1, r3, #1, #1276; CHECK-BE-NEXT: ubfx r3, r2, #10, #1277; CHECK-BE-NEXT: rsbs r3, r3, #0278; CHECK-BE-NEXT: bfi r1, r3, #2, #1279; CHECK-BE-NEXT: ubfx r3, r2, #8, #1280; CHECK-BE-NEXT: rsbs r3, r3, #0281; CHECK-BE-NEXT: bfi r1, r3, #3, #1282; CHECK-BE-NEXT: ubfx r3, r2, #6, #1283; CHECK-BE-NEXT: rsbs r3, r3, #0284; CHECK-BE-NEXT: bfi r1, r3, #4, #1285; CHECK-BE-NEXT: ubfx r3, r2, #4, #1286; CHECK-BE-NEXT: rsbs r3, r3, #0287; CHECK-BE-NEXT: bfi r1, r3, #5, #1288; CHECK-BE-NEXT: ubfx r3, r2, #2, #1289; CHECK-BE-NEXT: and r2, r2, #1290; CHECK-BE-NEXT: rsbs r3, r3, #0291; CHECK-BE-NEXT: bfi r1, r3, #6, #1292; CHECK-BE-NEXT: rsbs r2, r2, #0293; CHECK-BE-NEXT: bfi r1, r2, #7, #1294; CHECK-BE-NEXT: strb r1, [r0]295; CHECK-BE-NEXT: bx lr296entry:297 %c = icmp eq <8 x i16> %a, zeroinitializer298 store <8 x i1> %c, ptr %dst299 ret void300}301 302define arm_aapcs_vfpcc void @store_v16i1(ptr %dst, <16 x i8> %a) {303; CHECK-LE-LABEL: store_v16i1:304; CHECK-LE: @ %bb.0: @ %entry305; CHECK-LE-NEXT: vcmp.i8 eq, q0, zr306; CHECK-LE-NEXT: vmrs r1, p0307; CHECK-LE-NEXT: strh r1, [r0]308; CHECK-LE-NEXT: bx lr309;310; CHECK-BE-LABEL: store_v16i1:311; CHECK-BE: @ %bb.0: @ %entry312; CHECK-BE-NEXT: vrev64.8 q1, q0313; CHECK-BE-NEXT: vcmp.i8 eq, q1, zr314; CHECK-BE-NEXT: vmrs r1, p0315; CHECK-BE-NEXT: rbit r1, r1316; CHECK-BE-NEXT: lsrs r1, r1, #16317; CHECK-BE-NEXT: strh r1, [r0]318; CHECK-BE-NEXT: bx lr319entry:320 %c = icmp eq <16 x i8> %a, zeroinitializer321 store <16 x i1> %c, ptr %dst322 ret void323}324 325define arm_aapcs_vfpcc void @store_v2i1(ptr %dst, <2 x i64> %a) {326; CHECK-LE-LABEL: store_v2i1:327; CHECK-LE: @ %bb.0: @ %entry328; CHECK-LE-NEXT: vmov r1, r2, d0329; CHECK-LE-NEXT: orrs r1, r2330; CHECK-LE-NEXT: mov.w r2, #0331; CHECK-LE-NEXT: csetm r1, eq332; CHECK-LE-NEXT: bfi r2, r1, #0, #1333; CHECK-LE-NEXT: vmov r1, r3, d1334; CHECK-LE-NEXT: orrs r1, r3335; CHECK-LE-NEXT: csetm r1, eq336; CHECK-LE-NEXT: bfi r2, r1, #1, #1337; CHECK-LE-NEXT: strb r2, [r0]338; CHECK-LE-NEXT: bx lr339;340; CHECK-BE-LABEL: store_v2i1:341; CHECK-BE: @ %bb.0: @ %entry342; CHECK-BE-NEXT: vrev64.32 q1, q0343; CHECK-BE-NEXT: vmov r1, r2, d3344; CHECK-BE-NEXT: orrs r1, r2345; CHECK-BE-NEXT: mov.w r2, #0346; CHECK-BE-NEXT: csetm r1, eq347; CHECK-BE-NEXT: bfi r2, r1, #0, #1348; CHECK-BE-NEXT: vmov r1, r3, d2349; CHECK-BE-NEXT: orrs r1, r3350; CHECK-BE-NEXT: csetm r1, eq351; CHECK-BE-NEXT: bfi r2, r1, #1, #1352; CHECK-BE-NEXT: strb r2, [r0]353; CHECK-BE-NEXT: bx lr354entry:355 %c = icmp eq <2 x i64> %a, zeroinitializer356 store <2 x i1> %c, ptr %dst357 ret void358}359 360define arm_aapcs_vfpcc <4 x i32> @load_predcastzext(ptr %i, <4 x i32> %a) {361; CHECK-LE-LABEL: load_predcastzext:362; CHECK-LE: @ %bb.0:363; CHECK-LE-NEXT: ldrh r0, [r0]364; CHECK-LE-NEXT: vmov.i32 q1, #0x0365; CHECK-LE-NEXT: vmsr p0, r0366; CHECK-LE-NEXT: vpsel q0, q0, q1367; CHECK-LE-NEXT: bx lr368;369; CHECK-BE-LABEL: load_predcastzext:370; CHECK-BE: @ %bb.0:371; CHECK-BE-NEXT: ldrh r0, [r0]372; CHECK-BE-NEXT: vrev64.32 q1, q0373; CHECK-BE-NEXT: vmov.i32 q0, #0x0374; CHECK-BE-NEXT: vmsr p0, r0375; CHECK-BE-NEXT: vpsel q1, q1, q0376; CHECK-BE-NEXT: vrev64.32 q0, q1377; CHECK-BE-NEXT: bx lr378 %l = load i16, ptr %i, align 4379 %lz = zext i16 %l to i32380 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %lz)381 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer382 ret <4 x i32> %s383}384 385define arm_aapcs_vfpcc <4 x i32> @load_bc4(ptr %i, <4 x i32> %a) {386; CHECK-LE-LABEL: load_bc4:387; CHECK-LE: @ %bb.0:388; CHECK-LE-NEXT: vldr p0, [r0]389; CHECK-LE-NEXT: vmov.i32 q1, #0x0390; CHECK-LE-NEXT: vpsel q0, q0, q1391; CHECK-LE-NEXT: bx lr392;393; CHECK-BE-LABEL: load_bc4:394; CHECK-BE: @ %bb.0:395; CHECK-BE-NEXT: vldr p0, [r0]396; CHECK-BE-NEXT: vrev64.32 q1, q0397; CHECK-BE-NEXT: vmov.i32 q0, #0x0398; CHECK-BE-NEXT: vpsel q1, q1, q0399; CHECK-BE-NEXT: vrev64.32 q0, q1400; CHECK-BE-NEXT: bx lr401 %l = load i32, ptr %i, align 4402 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)403 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer404 ret <4 x i32> %s405}406 407define arm_aapcs_vfpcc <8 x i16> @load_predcast8(ptr %i, <8 x i16> %a) {408; CHECK-LE-LABEL: load_predcast8:409; CHECK-LE: @ %bb.0:410; CHECK-LE-NEXT: vldr p0, [r0]411; CHECK-LE-NEXT: vmov.i32 q1, #0x0412; CHECK-LE-NEXT: vpsel q0, q0, q1413; CHECK-LE-NEXT: bx lr414;415; CHECK-BE-LABEL: load_predcast8:416; CHECK-BE: @ %bb.0:417; CHECK-BE-NEXT: vldr p0, [r0]418; CHECK-BE-NEXT: vrev64.16 q1, q0419; CHECK-BE-NEXT: vmov.i32 q0, #0x0420; CHECK-BE-NEXT: vpsel q1, q1, q0421; CHECK-BE-NEXT: vrev64.16 q0, q1422; CHECK-BE-NEXT: bx lr423 %l = load i32, ptr %i, align 4424 %c = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %l)425 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> zeroinitializer426 ret <8 x i16> %s427}428 429define arm_aapcs_vfpcc <16 x i8> @load_predcast16(ptr %i, <16 x i8> %a) {430; CHECK-LE-LABEL: load_predcast16:431; CHECK-LE: @ %bb.0:432; CHECK-LE-NEXT: vldr p0, [r0]433; CHECK-LE-NEXT: vmov.i32 q1, #0x0434; CHECK-LE-NEXT: vpsel q0, q0, q1435; CHECK-LE-NEXT: bx lr436;437; CHECK-BE-LABEL: load_predcast16:438; CHECK-BE: @ %bb.0:439; CHECK-BE-NEXT: vldr p0, [r0]440; CHECK-BE-NEXT: vrev64.8 q1, q0441; CHECK-BE-NEXT: vmov.i32 q0, #0x0442; CHECK-BE-NEXT: vpsel q1, q1, q0443; CHECK-BE-NEXT: vrev64.8 q0, q1444; CHECK-BE-NEXT: bx lr445 %l = load i32, ptr %i, align 4446 %c = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %l)447 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> zeroinitializer448 ret <16 x i8> %s449}450 451define arm_aapcs_vfpcc <4 x i32> @load_bc4_align2(ptr %i, <4 x i32> %a) {452; CHECK-LE-LABEL: load_bc4_align2:453; CHECK-LE: @ %bb.0:454; CHECK-LE-NEXT: ldr r0, [r0]455; CHECK-LE-NEXT: vmov.i32 q1, #0x0456; CHECK-LE-NEXT: vmsr p0, r0457; CHECK-LE-NEXT: vpsel q0, q0, q1458; CHECK-LE-NEXT: bx lr459;460; CHECK-BE-LABEL: load_bc4_align2:461; CHECK-BE: @ %bb.0:462; CHECK-BE-NEXT: ldr r0, [r0]463; CHECK-BE-NEXT: vrev64.32 q1, q0464; CHECK-BE-NEXT: vmov.i32 q0, #0x0465; CHECK-BE-NEXT: vmsr p0, r0466; CHECK-BE-NEXT: vpsel q1, q1, q0467; CHECK-BE-NEXT: vrev64.32 q0, q1468; CHECK-BE-NEXT: bx lr469 %l = load i32, ptr %i, align 2470 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)471 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer472 ret <4 x i32> %s473}474 475define arm_aapcs_vfpcc <4 x i32> @load_bc4_offset(ptr %i, <4 x i32> %a) {476; CHECK-LE-LABEL: load_bc4_offset:477; CHECK-LE: @ %bb.0:478; CHECK-LE-NEXT: adds r0, #6479; CHECK-LE-NEXT: vmov.i32 q1, #0x0480; CHECK-LE-NEXT: vldr p0, [r0]481; CHECK-LE-NEXT: vpsel q0, q0, q1482; CHECK-LE-NEXT: bx lr483;484; CHECK-BE-LABEL: load_bc4_offset:485; CHECK-BE: @ %bb.0:486; CHECK-BE-NEXT: adds r0, #6487; CHECK-BE-NEXT: vrev64.32 q1, q0488; CHECK-BE-NEXT: vldr p0, [r0]489; CHECK-BE-NEXT: vmov.i32 q0, #0x0490; CHECK-BE-NEXT: vpsel q1, q1, q0491; CHECK-BE-NEXT: vrev64.32 q0, q1492; CHECK-BE-NEXT: bx lr493 %g = getelementptr inbounds i16, ptr %i, i32 3494 %l = load i32, ptr %g, align 4495 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)496 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer497 ret <4 x i32> %s498}499 500define arm_aapcs_vfpcc <4 x i32> @load_bc4_range4(ptr %i, <4 x i32> %a) {501; CHECK-LE-LABEL: load_bc4_range4:502; CHECK-LE: @ %bb.0:503; CHECK-LE-NEXT: vldr p0, [r0, #4]504; CHECK-LE-NEXT: vmov.i32 q1, #0x0505; CHECK-LE-NEXT: vpsel q0, q0, q1506; CHECK-LE-NEXT: bx lr507;508; CHECK-BE-LABEL: load_bc4_range4:509; CHECK-BE: @ %bb.0:510; CHECK-BE-NEXT: vldr p0, [r0, #4]511; CHECK-BE-NEXT: vrev64.32 q1, q0512; CHECK-BE-NEXT: vmov.i32 q0, #0x0513; CHECK-BE-NEXT: vpsel q1, q1, q0514; CHECK-BE-NEXT: vrev64.32 q0, q1515; CHECK-BE-NEXT: bx lr516 %g = getelementptr inbounds i32, ptr %i, i32 1517 %l = load i32, ptr %g, align 4518 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)519 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer520 ret <4 x i32> %s521}522 523define arm_aapcs_vfpcc <4 x i32> @load_bc4_range(ptr %i, <4 x i32> %a) {524; CHECK-LE-LABEL: load_bc4_range:525; CHECK-LE: @ %bb.0:526; CHECK-LE-NEXT: vldr p0, [r0, #508]527; CHECK-LE-NEXT: vmov.i32 q1, #0x0528; CHECK-LE-NEXT: vpsel q0, q0, q1529; CHECK-LE-NEXT: bx lr530;531; CHECK-BE-LABEL: load_bc4_range:532; CHECK-BE: @ %bb.0:533; CHECK-BE-NEXT: vldr p0, [r0, #508]534; CHECK-BE-NEXT: vrev64.32 q1, q0535; CHECK-BE-NEXT: vmov.i32 q0, #0x0536; CHECK-BE-NEXT: vpsel q1, q1, q0537; CHECK-BE-NEXT: vrev64.32 q0, q1538; CHECK-BE-NEXT: bx lr539 %g = getelementptr inbounds i32, ptr %i, i32 127540 %l = load i32, ptr %g, align 4541 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)542 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer543 ret <4 x i32> %s544}545 546define arm_aapcs_vfpcc <4 x i32> @load_bc4_range2(ptr %i, <4 x i32> %a) {547; CHECK-LE-LABEL: load_bc4_range2:548; CHECK-LE: @ %bb.0:549; CHECK-LE-NEXT: vldr p0, [r0, #-508]550; CHECK-LE-NEXT: vmov.i32 q1, #0x0551; CHECK-LE-NEXT: vpsel q0, q0, q1552; CHECK-LE-NEXT: bx lr553;554; CHECK-BE-LABEL: load_bc4_range2:555; CHECK-BE: @ %bb.0:556; CHECK-BE-NEXT: vldr p0, [r0, #-508]557; CHECK-BE-NEXT: vrev64.32 q1, q0558; CHECK-BE-NEXT: vmov.i32 q0, #0x0559; CHECK-BE-NEXT: vpsel q1, q1, q0560; CHECK-BE-NEXT: vrev64.32 q0, q1561; CHECK-BE-NEXT: bx lr562 %g = getelementptr inbounds i32, ptr %i, i32 -127563 %l = load i32, ptr %g, align 4564 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)565 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer566 ret <4 x i32> %s567}568 569define arm_aapcs_vfpcc <4 x i32> @load_bc4_range3(ptr %i, <4 x i32> %a) {570; CHECK-LE-LABEL: load_bc4_range3:571; CHECK-LE: @ %bb.0:572; CHECK-LE-NEXT: add.w r0, r0, #512573; CHECK-LE-NEXT: vmov.i32 q1, #0x0574; CHECK-LE-NEXT: vldr p0, [r0]575; CHECK-LE-NEXT: vpsel q0, q0, q1576; CHECK-LE-NEXT: bx lr577;578; CHECK-BE-LABEL: load_bc4_range3:579; CHECK-BE: @ %bb.0:580; CHECK-BE-NEXT: add.w r0, r0, #512581; CHECK-BE-NEXT: vrev64.32 q1, q0582; CHECK-BE-NEXT: vldr p0, [r0]583; CHECK-BE-NEXT: vmov.i32 q0, #0x0584; CHECK-BE-NEXT: vpsel q1, q1, q0585; CHECK-BE-NEXT: vrev64.32 q0, q1586; CHECK-BE-NEXT: bx lr587 %g = getelementptr inbounds i32, ptr %i, i32 128588 %l = load i32, ptr %g, align 4589 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)590 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer591 ret <4 x i32> %s592}593 594define arm_aapcs_vfpcc <4 x i32> @load_bc4_range5(ptr %i, <4 x i32> %a) {595; CHECK-LE-LABEL: load_bc4_range5:596; CHECK-LE: @ %bb.0:597; CHECK-LE-NEXT: sub.w r0, r0, #512598; CHECK-LE-NEXT: vmov.i32 q1, #0x0599; CHECK-LE-NEXT: vldr p0, [r0]600; CHECK-LE-NEXT: vpsel q0, q0, q1601; CHECK-LE-NEXT: bx lr602;603; CHECK-BE-LABEL: load_bc4_range5:604; CHECK-BE: @ %bb.0:605; CHECK-BE-NEXT: sub.w r0, r0, #512606; CHECK-BE-NEXT: vrev64.32 q1, q0607; CHECK-BE-NEXT: vldr p0, [r0]608; CHECK-BE-NEXT: vmov.i32 q0, #0x0609; CHECK-BE-NEXT: vpsel q1, q1, q0610; CHECK-BE-NEXT: vrev64.32 q0, q1611; CHECK-BE-NEXT: bx lr612 %g = getelementptr inbounds i32, ptr %i, i32 -128613 %l = load i32, ptr %g, align 4614 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)615 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer616 ret <4 x i32> %s617}618 619declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)620declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)621declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)622